SU983640A1 - Time interval to binary code converter - Google Patents

Description

The invention relates to radio electronics and is used for analog-digital conversion and encoding of information.

A voltage converter into a code, an exponential sweep driver, two comparison circuits, a control trigger, a clock generator, a gate, a digital analogue of the KS circuit, two comparison results memory triggers, an OR circuit, two AND circuits, a delay line, a number- impulse codes, blocking trigger Q.

The disadvantage of the converter is the inability to perform addition and subtraction operations.

The closest in technical essence to the data of the invention is a time interval converter into a binary code comprising a generator, a switching unit made in the form of a trigger and two elements AND, a binary counter and an information output unit associated with it, a time delay unit, element OR, the first input of which is connected to one output of the switching unit and is the output of the lower bit of the converter, the second input is connected

through the time delay unit to another output of the switching unit, the trigger output of the switching unit is connected to the input of the counter 2.

This converter has low speed, low reliability, and also does not allow, along with the encoding of time intervals, to perform addition and subtraction operations.

10 two consecutively entered time intervals in the device with subsequent coding of the result.

The purpose of the invention is to increase fast and increase functionality.

The goal is achieved by the fact that in a time converter into a binary code containing

20 generator of impulses, AND element, the output of which is connected to the first input of the OR element, reversible counter, interlocked delay unit and trigger, three AND-NES elements are inserted, the first input of the device is connected directly to the first input of the first AND-NOT element and through the second element AND-NOT - to the first input of the trigger, the first output

30 of which is connected to the first input of the third NAND element, the output of which is connected to the second input of the OR element, the output of which is connected to the subtract input of the reversible counter, the first output of which is the device output, and the second is connected to the second trigger input, the second input of the device connected to the input of the AND element, whose output through the time delay block is connected to the second input of the third NAND element, the second inputs of the first NAND element and the AND element are connected and connected to the output of the reference impulse generator pulses, the output of the first element AND-NOT is connected to the aid of E (reversible counter stroke. The drawing shows the block diagram of the proposed converter. The converter contains elements AND-NOT 1-3, generator 4 reference pulses, trigger 5, reverse counter b, element OR 7 , element 8, time delay block 9 and inputs 10-12. The device operates as follows: The measurement start impulse is fed to the installation input 12 at zero state and sets all the counters of the counter counter b to the zero state. The measured time interval T arrives at the device input 10 at the input of the AND-NE element 1, to another input of which pulses are delivered from the generator 4 of the reference pulses. From the output of the element N, the pulses deposited in the measured interval t are sent to the summing input of the counter 6, and on its output the information about the pulse duration T appears in the binary code. The measured interval t also enters through the AND-HE 2 element at the first input of the trigger 5 and sets it to the single state. The presence of a logical unit at the direct output of the trigger 5 corresponds to the fact that the information at the output of the counter b is represented in the forward binary code. This information is stored in the counter until the reset pulse arrives at the device input 12. During the addition operation, i.e. when the second time interval Г j is added to the measured time interval 1Г, C2 is fed to the input 10 of the device, and from there to the input of the AND-NE element 1 and passes Nj pulses from the generator 4 reference pulses to the summing input of counter b, on the first output which appears information about the total duration of the intervals f and is presented in binary code. The state at the output of trigger 5 will not change in this case, i.e. on its direct output, the state of the logical unit will remain. This corresponds to the fact that the information on the output of the counter b is represented in the forward binary code. For the operation of subtracting i. when the duration of the second time interval t is subtracted from the duration of the first time interval 7: at f 7T2, i.e. N 7 N2 / impulse, 2 is fed to input 11 of the device and opens element AND 8, thereby passing N, j pulses —c from the generator 4 reference pulses through the element OR 7 to the subtracting input of counter 6, at the first output of which about the difference between the durations of the intervals and f, is presented in the binary ksed. The state of trigger 5 in this case does not change. The presence of a logical unit at the direct output of trigger 5 corresponds to the fact that the information at the first output of counter b is represented in the forward binary code. For the operation of the subtraction provided, i.e. N N, impulse C is fed to the input of the logic element And 8, passes to the subtracting input of the counter b N pulses from the generator 4. With n-impulses N pulses to the subtracting input of the counter b, all the bits of the counter are set to zero resistant. In this case, a pulse appears at the second output of the counter, which arrives at the second input of trigger 5 and sets it to the zero state. The next (N -, + 1) pulse sets all the bits of the counter to one state, and the pulses, starting with (), set the counter bits to the state corresponding to the difference / 1 Nf- () or regrouping we have: i3 ( ) + i, whence it is seen that the obtained value of the difference in the number of pulses NJ, and N, equivalent to the time intervals T f f2, respectively, differs from the true one by 1. The correction is introduced as follows. The signal of the logical unit from the inverted output of the trigger 5 is fed to the input of the element AND-NOT 3 and opens it to pass the delayed delay of the deduced pulse T2 by the block 9 delayed by the block 9 (the delay is necessary to prevent the pulse B and the falling edge from passing to the input of the counter b pulse tj) and then through the element OR 7 to the subtracting input of the counter b. At the same time, the contents of the counter decrease by one, thereby increasing the value of the difference in time intervals t and fj and becomes equal to N: -N / z /

which corresponds to the true value. The presence on the inverse output of the trigger 5 of a logical one, the unit corresponds to the TLV1U, that the information on the first output is represented in the reverse binary code.

Claims (2)

1. Author's certificate of the USSR 497727, cl. H 03 K 13/20, 1974. 2. USSR author's certificate I 354567, cl. H 03 K 13/20, 1971.