SU970670A1 - Pulse duration discriminator - Google Patents

Description

The invention relates to a pulsed technique and can be used for the selection of pulses in duration with an external selection threshold. A device is known that provides for setting a selection threshold from outside, comprising a clock pulse generator, a code comparison element, memory blocks and a code sample, a code register and elements.

However, such a device is difficult and does not provide recovery of the information duration of the selected pulse.

A pulse signal selector is also known, comprising a reference pulse generator, a pulse counter, a decoder, a trigger, a delay element, a BAN logic element, a pulse shaper, and elements,

A disadvantage of the known device is that it selects pulses of only one duration.

Most, b / 1 low to the present invention is a pulse selector in duration, containing a clock pulse generator, the output of which is connected to the first inputs of the first and second elements AND, the outputs of which are

ryh are connected respectively with the first and second inputs of the OR element. the output of which is connected to the counting input of the pulse counter, the output of which is connected to the counting input of the first trigger, the inverter, whose input and the second input of the first element I are connected to the input bus of the selector, and the output of the inverter is connected to the reset input of the pulse counter and to the first input of the third element And, the second input of which is connected to the prmlm output of the first trigger, and the output - with a single input

15 of the second trigger, the zero input of which is connected to the inverse output of the first trigger, and the output to the second input of the second element I 3 ..

20

A disadvantage of the known device is the impossibility of externally controlling the selection threshold, which is determined by the conversion rate of the pulse counter and is strictly specified.

 for a given circuit device that

significantly limits the possibility of using the proposed device in automatic control.

The purpose of the invention is the expansion

Claims (3)

30 functional devices due to the possibility of externally controlling the selection threshold. The goal is achieved by the fact that the device containing the clock pulse generator, zykhod which is connected to the first inputs of the first and second elements And, the investor, whose input is connected to the second input of the first element And1 and connected to the device input bus, trigger, etc. my output of which is connected to the second input of the second element AND, the third element AI of the pulse counter, entered the storage register, the code comparison element and the decoder zero, whose INPUT is connected to the output of the counter, pulses and the first input of the comparison element codes, the second input of which is connected to the output of the register of storage, the input of which is connected to the control bus of the device, and the outputs of the code comparison element and the decoder n are connected respectively to the unit and the zero input of the trigger, the inverse output of which is connected to the third input of the first element And the first input of the third element And, the second input of which is connected to the output and the verter and the third input of the second element And, the output of which is connected to the subtraction input of the pulse counter, the summing and reset inputs of which are connected ootvetstvenno to the outputs of the first and third elements of AND, Figure 1 is given a block diagram of the selector; in fig. 2 time diagrams, where a is the sequence of oscillator clock pulses 17 6 - input pulse; c — impulses arriving at the summing input of counter 2; g is the pulse at the input of the element 3 of the comparison of codes; d - output pulse; e is the pulse at the output of the inverter 7; W impulse at the output element And 9; s pulse at the inverse of the trigger output 6; n - impulses arriving at the input of the subtraction of counter 2; a pulse at the output of the decoder 5. The selector contains a generator of 1 clock pulses, a counter of 2 pulses, an element 3 of comparison of codes, a register 4 of storage, a decoder of 5 nl, a trigger b, an inverter 7, an element of And 8-10, an input bus And, directed to a duy bus 13. The output of the generator 1 is connected to the first inputs of the elements And 8 and 9. The second input of the element And 8 is connected to the input bus 11 of the device. The output of an AND 8 element is dinane with the input of summing gate 2 sum, and the output of element 9 is with the reset input of counter 2. The output of element AND 9 is connected to the subtraction input of counter 2, the output of which is connected to the input of the decoder 5 and to the first input of the comparison element 3 , the second input of which is connected to the output of the register 4, the input of which is connected to the control bus 12 of the device. The output of the comparison element 3 and the output of the de-diffuser 5 are connected respectively to the single and zero inputs of the trigger 6, the inverse output koToporo is connected to the first input of the And 10 element and to the third input of the And 8 element. The third output of the trigger 6 is connected output 13 of the device. In addition, the input pulses arrive at the inverter 7, the output of which is connected to the second input of the element 10 and the third input of the element 9. The selector operates as follows. The input rectangular impulse arrives at the input of the And 8 element (Fig. 2, b) and is filled with the counting pulses of the generator 1 (Fig. 2, a). Thus, the input signal is converted into pulses, the number of which is proportional to the duration of the input pulse. These pulses arrive at the input of the counter-2 counter (Fig.). Counter 2 at its output generates a binary code that enters the first input of the comparison element 3, the code from register 4 arrives at the second input of KoTopioro. Previously, the code corresponding to the selection threshold Tf, is written to register 4 via control bus 12. If the duration of the input pulse satisfies the condition T: fCf, then counter 2 is reset by the falling edge of the input pulse f that passes through the inverter 7 and element 10. In this case, the comparison element 3 does not produce a signal. If the duration of the input signal tr satisfies the condition tv Cs then, after the output of counter 2 sets a code equal to the selection threshold code, comparison element 3 generates a signal of equality of codes (Fig.2, d), which sets trigger b to one state (in the initial state the trigger 6 is in the zero state). Thus, the leading edge of the output pulse is formed (Fig. 2, d). The zero potential from the inverse output of the trigger 6 enters the third input of the element I 8, and prohibits the further passage of the clock pulses from the generator 1 to the input of the summation of the counter 2. The counter 2 stops counting. With the end of the input pulse, a high potential from the output of the inverter 7 (Fig. 2, e) goes to the third input of the element A 9, to the second input of which a high potential comes from the direct output of the trigger b. The clock pulses from the generator 1 pass through the open element AND 9 of the input of the subtraction of counter 2. Start the counting in the opposite direction (Fig. 2) After the number of pulses entering the subtraction of the counter of 2 becomes equal to the previously entered number An impulse (Fig. 2k) appears at the output of the summation of counter 2, at the output of the decoder 5, returning trigger 6 to its initial state. This completes the formation of the output pulse, the duration of which is equal to the duration of the input pulse (Fig. 2, e) Changing the threshold The selection is carried out by changing the code that arrives on the control bus 12. Thus, the proposed device allows the selection of pulses by duration from a sequence of pulses, and the selection selection is set externally by signals on the control bus, and the information duration of the selectable pulse The formula of the invention is a Pulse selector for duration, comprising a clock pulse generator, the output of which is connected to the first inputs of the first and second element And, the inverter, the input of which is connected to the second input of the first element And, and connected to the input bus of the device, a trigger, the direct output of which is connected to the second input of the second element And, the third element And and the pulse counter, which In order to expand its functionality, a storage register, a code comparison element and a zero decoder are entered into it, the input of which is connected to the output of the pulse counter and the first input of the code comparison element, the second input of which is connected to the output of the storage register, cat It is connected to the control bus of the device, and the outputs of the code comparison element and the zero decoder are connected respectively to the single and zero trigger inputs, the inverse output of which is connected to the third input of the first And element and the first input of the third And element, the second input of which is connected to the output of the inverter and the third input of the second element And, the output of which is connected to the input of the subtraction of the pulse counter, the inputs of summation and reset of which are connected respectively to the outputs of the first and third elements I. Sources information ,, taken into account in the examination of 1-. USSR author's certificate 746901, cl. H 03 K 5/18, 1980. 2. USSR author's certificate 540365, cl. H 03 K 5/18, 11.11.75. 3. USSR author's certificate 558394, cl. H 03 K 5/18, 09.02.76 (prototype). d e well and to - t ig.2.