RU1800595C - Multi-channel delayed pulse train generator - Google Patents

Abstract

The invention relates to pulsed technology, is intended for controlling a pulsed accelerator, laser systems, arbitrary waveform generators and can be used in synchronizers, control and computing systems. The purpose of the invention is to simplify the device. A multi-channel delayed pulse generator series comprises a channel counter, a decoder and a single-channel programmable pulse generating unit, which in turn contains a random access memory, an address counter, a number counter, an overflow analyzer, a delay code memory unit, a comparison unit, a clock generator, control triggers, OR element and counter for determining the temporal position of the pulse. 1 ill.

Description

The invention relates to pulsed technology, is intended for controlling pulses by an accelerator, laser systems, arbitrary waveform generators, and can be used in synchronizers, control systems, and computer systems.

The purpose of the invention is to simplify the device.

The drawing shows a block diagram of the proposed device.

A multi-channel delayed pulse generator series consists of a multi-channel block 1 for generating programmed pulses, a counter 2 channels and a decoder 3, Bus 4 start connected to the inputs of the initial installation of block 1 for forming a pulse and counter 2 channels. The outputs 5 of the counter 2 channels are connected to the address inputs 6 of the decoder 3 and the group of inputs 7 code number of the next delay single-channel

programmable pulse generating unit 1. The output 8 of the generated delayed pulse of the single-channel block 1 of forming the programmed pulses is connected to the counting input 9 of the counter 2 and to the gate input 10 of the decoder 3. The group of outputs 11 of the decoder 3 functions as the output bus channels of the channels of the multi-channel generator. The single-channel programmable pulse generating unit 1 comprises a random access memory 12 address counter 13, a number counter 14, an overflow analyzer 15 consisting of triggers 16 and 17, a delay code memory unit 18, a comparison unit 19 consisting of an equality circuit 20 and flip-flops 21.22, a clock generator 23, first and second control flip-flops 24, 25, OR elements 26 and a counter 27 for determining the temporal position of the pulses.

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A multi-channel generator of a series of delayed pulses operates as follows.

When a pulse start is received via bus 4, the counter of 2 channels is set to its initial state and the outputs 5 of the outputs 5 are prepared to receive a pulse; the zero output of decoder 3 and the tube delay code in a single-channel block 1 for generating programmed pulses; Pulse received via bus 4 of the start starts the BP counting in the single-channel block 1 of formation of programmable pulses.

When the moment of time corresponding to the required pulse delay code is reached, the single-channel block 1 for generating programmable pulses generates a pulse at the output 8, which from the input 10 of the decoder 3 goes to the zero output - to the zero channel of the output buses. On the trailing edge of the pulse at the output 8, the channel counter 2 is transferred to the next state by setting the following channel number code,

In this way, the channel numbers and their corresponding pulse start time codes are alternately selected. Pulse delays in subsequent channels are in the order of increasing magnitude.

The application of the invention allows to reduce hardware costs in the technical implementation of the device compared to the prototype by the amount required to build one counter, the bit of which is determined by the required number of output channels, as well as by the difference in the hardware volume of a single-channel block 1 of formation of programmable pulses per The inventive device and prototype, which depends on the maximum value of the delay in the channel, determined in the number of discrete-reference frequency.

Claims (1)

The claims A multi-channel delayed pulse generator series comprising a single-channel programmable pulse generating unit and series-connected channel counter and decoder, characterized in that, in order to simplify the device, the outputs of the channel counter are connected to a group of inputs of the code number of the next delay of a single-channel programmable pulse generating unit, which contains a memory block of the delay code, an address counter, a number counter, the transfer output of which is connected to the input of the overflow analyzer, and the information inputs are connected to the information inputs of the random access memory and the first group of inputs the comparison unit, the second group of inputs of which is connected to the outputs of the delay code memory unit, the output of the clock generator is connected to the counting input of the first of the first trigger and the first input of the OR element, the second input of which is connected to the direct output of the first trigger, with the control inputs of the address counter and random access memory, the inverse output of the first trigger is connected to the control input of the number counter and from the first control input of the overflow analyzer, the output of the OR element connected to the second control input of the overflow analyzer, information address counters are connected to the first address inputs of the delay code memory unit and random access memory a, the transfer output is connected to the inputs of the initial installation of the overflow analyzer and the comparison unit, the information inputs of the number counter are connected to the outputs of the random access memory, and the counting input is connected to the output of the overflow analyzer, the output of the second trigger is connected to the reset input of the number counter, the installation input is connected to the bus start and counter reset input. address and counter. channels, the reset input of the second trigger is connected to the transfer output of the address counter and to the recording input of the counter for determining the temporary position of the pulses, the information inputs of which are connected to the outputs of the delay code memory unit, the counting input is connected to the inverse outputs of the first trigger, the reset input is connected with the output of the comparison unit, the third input of the OR element is connected to the senior information input of the address counter, the group of inputs of the code number of the next delay of the programmable pulse generating unit is dinene with the second address inputs of the delay memory unit. and