SU1206778A1 - Squaring device - Google Patents

Description

The invention relates to computing and can be used in digital computing and functional devices, digital measuring devices, as well as for processing information represented by number-pulse codes,

The purpose of the invention is to increase the speed by reducing the time between cycles during the output signals.

The drawing shows a diagram of the proposed device.

The device contains the first and second counters 1 and 2, trigger 3, groups. elements And 4, input 5 input frequency input 6 clock frequency output 7.

The device works on the following.

Let us assume that in the initial state the trigger 3 is in the zero state, and the counter 2 is not filled. The signal of the logical unit from the inverse output of the trigger 3, applied to the reset reset of counter 1, keeps it in the zero state. The logical zero signal from the direct output of trigger 3, arriving at the inputs of the And 4 elements, keeps it in a closed state. Since counter 2 is not filled, at its output is a logical zero, as a result of which a logical zero and at the D input of trigger 3, the impulses fed to the device at input 5 arriving at the trigger input of trigger 3 confirm its zero state, and the input the counter input of counter 2 is filled in (counter 2 is switched on the leading edge of the input pulses). When the input of the counter 2 arrives at the input 5 of the pulse filling it, the output of the counter 2 is in accordance with the logical unit. This logical unit arrives at the information input of trigger 3. On the falling edge of the pulse at input 5, trigger 3 switches

Editor V. Ivanova

Compiled by A. Zhizhin Tehred T. Tulik

Order 8714/50, Circulation 673 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PIP Patent, Uzhgorod, st. Project, 4

five

in a single state. At the inverse of the output of the trigger 3, a logical zero appears and the counter 1 ceases to be held in the zero state. The logical unit from the direct output of trigger 3, entering the inputs of the And 4 elements, opens them. The information from counter 1 is copied through the elements AND 4 to counter 2 in the return code. Since the reset signal from counter 1 is removed, the pulses of the clock frequency F 1 / T begin to be counted by counter 1. The first pulse of the clock frequency changes the state of counter 1 and, therefore, of counter 2, which tracks the state of counter 1. This leads to the disappearance of the logical unit at the output of counter 2 and the D input of the trigger 3. The next falling edge of the input pulse at input 5 enters the clock edge. trigger input 3, returns it to its original state, which leads to the closure of the elements And 4 and reset

counter 1 with inverse trigger output 3.

Immediately before zeroing the count;, - for the time T between two impulses, the N input pulses themselves have time to write in it,. And the counter 2 at the same time turns on the number corresponding to the reverse code N. After the impulses C 5 fill the counter 2. After N pulses the counter 2 is filled and a logical unit appears at its input and D input of the trigger 3, resulting in the next switching of the trigger 3 on the trailing edge of the pulse at the input 5. Then the processes are repeated.

five

0

45

The pulse duration at the output 7 of the device is determined by the time

fill the counter but T K T or T4

2, which is equal to Tf / T ,.

Proofreader A. Obruchar

Claims (1)

CONSTRUCTION DEVICE In SQUARE, containing a trigger and a first counter, characterized in that, in order to increase speed by reducing the time between cycles of outputting output signals, it contains a group of elements And, the second counter, the counting input of which is connected to the input of the input frequency of the device and the clock input of the trigger, the information input of which is connected to the transfer output of the second counter, the inverse output of the trigger is connected to the output of the device and the reset input of the first counter, the counting output of which is connected to the input of the clock frequency devices, the bit outputs of the first counter are connected to the first inputs of the elements AND groups, the second inputs of which are connected to the direct output of the trigger, the outputs of the elements and groups are connected to the inputs s of the second counter.