SU892412A1 - Digital meter of pulse train duration - Google Patents

Description

I

The invention relates to a radio metering technique and can be used in radio devices for accurate measurement of the pulse pack duration when pulses are passed inside the pack and in the presence of

interference pulses outside the bundle.

t

A device for measuring the duration of a burst of pulses is known, which contains a quantizing oscillator, a time selector, a pulse counter, a control trigger and a scaling circuit in which, to provide a measurement of the duration with an unknown number of pulses, in a burst, the output of the time selector is connected also to the counting input of the counting circuit with, the conversion factor N, the meter input is connected to the reset circuit of the counting circuit, and the trigger input is connected to the pulse counter, with the number N selected by the large number of pulses quantizing generator stacked at the maximum

the interval between adjacent pulses in bundle 1.

The disadvantage of this device is the need to pre-record the number on the counter.

The closest to the proposed technical essence is a device for measuring the duration of a packet of pulses, which contains a generator of pulses, AND-NOT elements, counters, a switching circuit, delay and inhibit elements, a control trigger, a time selector and a NO element, and the meter input is connected through the delay element to the reset circuit of the transfer circuit and to one of the inputs of the control trigger, the output of which is connected to the control input of the prohibition element, which is connected between the input of the meter and the input of the circuit recording the initial number in the pulse counter, additionally the signal input of the time selector is connected to the generator output, and its control input is connected to the output of the element NOT, and the output is connected to the counting input of the counting circuit; the input of the element is NOT connected to the input of the meter 2; The impulse of the initial setup is supplied before the measurement, however, it is not protected from gaps inside the burst and from interference pulses outside the burst. The purpose of the invention is to expand the functionality due to the possibility of measuring the duration of a burst of pulses in the presence of gaps of pulses within the burst and in the presence of impulses of interference outside the burst. The goal is achieved by the fact that a pulse width meter that contains a clock generator, a pulse counter, a control trigger, a scaling circuit two AND-NES, a pulse shaper of normalized duration, a reversible counter, a register, a multiple input element AND NONE and a multiple-input pulse are entered into the measurer. the OR element, and the outputs of the bits of the reversible counter are connected to the inputs of many (the AND-NOT and OR output elements, the output of the multi-input AND-NOT element is connected to the inverse synchronization input of the register and the first input of the first element IS-NOT, the second input of which is connected to the direct output of the pulse shaper of normalized duration, and the third - with the output of the TaJCTOBbix Pulser, the first inputs of the second AND-HEY element and the pulse shaper of the normalized duration, the inverse output of which is connected to the second input the second element ILE, the third input of which is connected to the output of the multi-input element OR and the inverse input to the zeroing of the control trigger, the inverse output of which is connected to the input of the asynchronous device The set to zero of the counter, the code of the second element AND-NOT is connected directly to the inverse input, synchronization of the control of the 1st and through the recalculation circuit "(subtracting the input of the reversible counter, the summing input of which is connected to the output of the first element r AND-NOT, inverse output of the clock generator The pulses are connected to the counting input of the locker, the bit outputs of which are connected to the information inputs of the register. FIG. I shows a block diagram of a device} on (jiir. 2 - time diagrams 24 we operate; Fig. 3 is a driver circuit. The device contains 1 clock pulse generator with forward 2 and inverse 3 outputs, controlling trigger 4 with inverse inputs 5 and 6 settings for synchronization zero and with information input 7, counter 8 with counting input 9 and installation input 10 for zero, register 11 for writing numbers with inverse synchronization input 12, driver of 13 pulses with normalized duration with forward 14 and inverse 15 outputs , two three-input elements AND-NOT 16 and 17, scaling circuit 18, reversible counter 19 with inverse inputs 20 and 21 of summation and subtraction, a multiple-input element AND-NOT 22 with a number of inputs equal to the number of binary bits of the reversible counter, a multiple-input element OR 23 with the same number of inputs. output 14 of the driver 13, 25 is the number in the reversible counter 19; 26 is the output of the multi-input element AND-NOT 22, 27 is the output of the trigger 4, 28 is the number in the counter 8, 29 is the number in the register 11, the driver 13 consists of the sin of the inverters AOR 32, three-input element AND-HE 33, tJK-flip-flops 34 and 35 and the counter 36 pulses. The device works as follows. In the absence of burst pulses, the device is automatically set to the initial state, in which the number on the reverse counter 19 is zero, AND-NE-17 element is locked by the potential of the logical zero from the output of the multi-input element OR 23, and the counter 8 is in the asynchronous zero setting state under the action of the potential of the logical unit of the inverse output of the control trigger 4, register 11 stores the number corresponding to the previous measurement. In such a state, the device remains until the first impulse of the packet arrives at the input of the imaging unit 13. When inputting the importer 13 of the burst pulses, the imaging unit 13 at the output 140 generates positive pulses with a similar duration 9 equal to an integer number η of the periods Tp of the generator 1. At the output 15, these are but 1 times inverted pulses. The first input from the output of the former 13 opens the first element I-LE 16 and the summing input on the PT.

58

20 of the reversible counter 19 enters the pulses, but after the arrival of the first of them the logical signal at the output of the element OR 23 becomes equal to one, the second element of the AND-NOT opens

17 and the control trigger is set to 4 in the unit. After the first pulse is terminated by the first positive voltage drop from the output of the IS-NE element 17, the control trigger 4 switches to one, and then the inverse output starts from zero. 3 of the generator 1 by the counter 8. This continues until the number in the reverse counter 19 again becomes zero, B iiayae between the pulses from the output of the fermirovator 13 to the subtracting input

21 of the reversible counter 19, pulses come from the output of the scaling circuit 18, following with an MHD period, where M is the capacity of the scaling circuit. By the time of receipt of the second pack, for D9rzhenno1. CHu relative to the first; on T,. ,, the number in the reverse counter 19 will be

. equal

p p-wtf

This number must be positive, i.e. the numbers n and M are determined by the inequality W, / t

about -

,

whereTLd u is the minimum possible interval between the impulses in the packKej

T., - ,,, - the maximum interval between

r MrVV "

pulses in a pack, taking into account the possible number of pulses in a pack.

Under the action of next-to-second burst pulses, the number in the reversible counter increases on average and at some point reaches the maximum value (upper threshold) 2-1, where m is the number of bits. At this output

multi-input element AND-NOT 22 at. Each potential of the logical zero, which closes the first element AND-NOT 16, the increase in the number in the reversible counter 19 stops. But after the next pulse from the output 14 of the generator 13 is completed, the number in the reversible counter decreases again, and under the action of the following pack pulses an oscillatory process is established with the maximum number 2-1 attained. At each overshoot from 2 - 1 in the co-chain, a smaller state 2 - 2 at the output of the multi-input element AND-NOT 22 posl 124

positive voltage drop | which the number from counter 8 is rewritten to register 11, the positive perepapad voltage at the input 12 of the synchronization register 11 is delayed by the T-fire condition but the falling edge of the pulses from the output of the imaging unit 13; however, the number corresponding to the interval between the falling front of the first and the falling front is written to the register 11 of the next pulse without mixing by +11 because the resolution to the counting of pulses from the control trigger 4 enters the input 10 of the counter 8 also with a delay on the falling front of the first pulse from the output of the formers Atel 13. On the counting input 9 of the counter 8 pod inverse pulses of the generator 1 so that there is no switching of the number in the counter 8 at the moment of its recording in the register II,

After shuffling the burst pulses, the number in the reversible counter decreases until the initial zero state is reached. In this case, the register 11 is written down the number corresponding to the duration of the interstitial of the first and the last pulse of the packet, and the result of the measurement is not affected by individual pulses of the pulses inside the burst, or by single or small groups of interference pulses outside the burst.

Timing diagrams (FIG. 2) show how the device responds aai skip pulses inside the burst and to groups of impulse interference outside the burst.

Claims (2)

The inverters 30 -32 and the NAND 33 element perform the functions of differentiation and inversion of a positive nanpi differential at input 37. The pulse from the output of element 33 I-LE switches the trigger 34 to one, and the trigger 34 returns to its initial state by a negative differential from the output of the last trigger of the counter 36, which not counts the pulses of the generator 1, sent to the input 38. The capacity of the NVg counter 36 must be equal to n -1. The trigger 35 is required to synchronize the edges of the generated pulse with the clock sequence, i.e. so that the duration of the pulses at the outputs 39 and 40 exactly equal to the number n of periods of the clock sequence at the input 38. The inverted output of the trigger 35 is connected to one of the Inputs of the circuit of the NAND elements to prohibit the triggering of the driver 13 before the formation of the pulses 8 on his vyhotsah. The minimum period of following burnout drops, for example, femme, on-Korof) oe reacts, forming 13 is equal to (n + 1). For example, if the capacitor MO of the meter 36 is equal to 10, the pulse of the pulse at the output of the imager is llTj), and the minimum period is 12Td, invention claims Digital pulse width meter containing the generator of shock pulses, counter, pulses 1, pulses, controllable trigger, scaling circuit and two elements, characterized in that, with the aim of extending the functionality by providing the possibility of measuring the duration of a burst of pulses in the presence of gaps in the burst of the burst and in the presence of impulses of interference beyond the limit) C1i packs, a formaker of pulses of normalized duration, reversible counter, register, multi-input element AND-NOT and multi-input element AND LI are entered into it: the outputs of the bits of the reversible counter are connected to the inputs of the multi-input elements AND-NOT and OR , the output of the multi-input element AND-NOT is connected to the inverse synchronization input of the register and the first input of the first element I28 NOT, the second input of which is connected to the direct output of the pulse shaper of a normalized duration, and the third to the direct output of the generator the clock of the pulse, the first inputs of the second NAND element and the pulse former of normalized duration, the inverse output of which is connected to the second input of the second NAND element, the third input of which is connected to the output of the multi-input element LI and the inverse input of the control unit to zero the trigger, the inverse output of which is connected to the input of the asynchronous setting to zero of the counter, the output of the second NAND element is connected directly to the inverse synchronization input of the control trigger and through the scaling circuit y - to the subtracting input of the reversible counter, the summing input of which is connected to the output of the first element; the inverse output of the clock pulse generator is connected to the counting input of the counter, the outputs of which bits are connected to the information inputs of the register. Sources of information taken into account in the examination 1. The author's certificate of the USSR N 4S7067, CL, G04P 10/00, 1975. 2. USSR author's certificate No. 669332, cl .- G 04 R 10/04, 1979. RLJlJLJl lJlЛJlП- FIG. JT-J1