SU951733A1

SU951733A1 - Device for discrete data transmission and receiving

Info

Publication number: SU951733A1
Application number: SU813243338A
Authority: SU
Inventors: Олег Станиславович Когновицкий; Вячеслав Николаевич Сюрин; Александр Васильевич Буданов
Original assignee: Ленинградский Электротехнический Институт Связи Им.Проф.М.А.Бонч-Бруевича
Priority date: 1981-01-27
Filing date: 1981-01-27
Publication date: 1982-08-15

Description

Изобретение относитс к св зи и может быть использовано дл передачи дискретной информации- с высокой скоростью и достоверностью. Известно устройство дл передачи и приема дискретной информации, содержащее на передаче блок выделени фронта сигнала, триггер, два элемента И и суммирующий счетчик, ко входу которого подключен выход первого элемента И, а на приемной стороне два элемента И, два триггера и суммирующий счетчик 1 }. Однако известное устройство обладает низкой достоверностью передаваемой информации. Цель изобретени - повышение достоверности передаваемой информации, Дл достижени этой цели в устрой ство дл передачи и приема дискретной информации, содержащее на переда ющей стороне блок выделени фронта сигнала, триггер, два элемента И и суммирующий счетчик, ко входу которо го подключен выход первого элемента И, а на приемной стороне - два элемента И, два триггера и суммирующий счетчик, на передающей стороне введены третий элемент И, последовательно соединенные генератор псевдослучайной последовательности (ПСП) и блок задержки, а также последовательно соединенные вычитающий счетчик и элемент ИЛИ, выход которого подключен к первому входу третьего элемента И, выход которого подключен к тактовому входу генератора ПСП и счетному входу вычитающего счетчика, при этом ко входам вычитаюи1его счетчика подключены выходы суммирующего счетчика , к дополнительному входу которого подключен выход . второго элемента И, первый вход которого объединен со входом блока выделени фронта сигнала и вл етс входом устройства, а выход блока выделени фронта сигнала подключен к нулевому входу триггера , единичный вход которого объсдинен со вторым входом второго элемента И и счетным входом суммирующего счетчика и. вл етс вторым входом устройства, при этом выход триггера подключен к первому входу первого элемента И, а выход блока задержки подключен ко входу канала св зи, причем вторые входы первого и третьего элементов И вл ютс соответственно третьим и четвертым входам устройства, на приемной стороне генератор ПСП, блок сравнени и блок выделени ПСП, а также инвертор и последовательно соединенные накопитель , вычит.ающий счетчик и дешифратор , выход которого через последовательно соединенные инвертор и вто рой элемент И подключен к счетному входу вычитающего счетчика и входу второго триггера непосредственно, ко входу управлени которого подключен дополнительный выход накопител , ко входам которого подключены выходы суммирующего счетчика, к счетному входу которого, а также к-тактовому входу генератора ПСП подключен выход первого элемента И, при этом выходы генератора ПСП и блока выделени ПСП подключены ко входам блока сравнени , выход которого подключен к нулевому входу первого триггера, к единичному входу которого подключен выход блока выделени ПСП, ко входу которого подключен выход канала св зи, а пр мой и инверсный выходы первого триггера подключены соответственно к первому входу первого элемента И и входу считывани суммирующего счетчика, при этом вторые входы первого и второго элементов И вл ютс соответственно п тым и шестым входами устройства , седьмым входом которого вл етс вход считывани накопител .The invention relates to communications and can be used to transmit discrete information with high speed and reliability. A device for transmitting and receiving discrete information is known. It contains a signal edge separation unit, a trigger, two AND elements and a summing counter, to whose input the output of the first And element is connected, and on the receiving side two And elements, two triggers and a summing counter . However, the known device has a low accuracy of the transmitted information. The purpose of the invention is to increase the reliability of the transmitted information. To achieve this goal, a device for transmitting and receiving discrete information contains, on the transmitting side, a signal edge selection block, a trigger, two AND elements and a summing counter, to the input of which , and on the receiving side - two elements And, two triggers and a summing counter, on the transmitting side entered the third element And, connected in series to a pseudo-random sequence generator (PSP) and a delay unit, and Also connected in series is a subtracting counter and an OR element whose output is connected to the first input of the third element AND whose output is connected to the clock input of the PSP generator and the counting input of the subtracting counter, and the output of the summing counter are connected to the inputs of the subtracting counter . the second element And, the first input of which is combined with the input of the signal edge selection block and is the device input, and the output of the signal edge selection block is connected to the zero input of the trigger, the single input of which is combined with the second input of the second element And the counting input of the summing counter and. is the second input of the device, while the trigger output is connected to the first input of the first And element, and the output of the delay unit is connected to the input of the communication channel, the second inputs of the first and third And elements being the third and fourth inputs of the device, respectively, on the receiving side The memory bandwidth, the comparison unit and the memory allocation unit, as well as the inverter and the serially connected drive, the subtracting counter and the decoder, the output of which is connected to the counting unit through the serially connected inverter and second element the course of the deducting counter and the input of the second trigger directly, to the control input of which an additional output of the accumulator is connected, to the inputs of which are connected the outputs of the summing counter, to the counting input of which, and to the clock input of the PSP generator, the output of the first element And and the PSP allocation unit is connected to the inputs of the comparison unit, the output of which is connected to the zero input of the first trigger, to the unit input of which the output of the PSP selection unit is connected, to the input of which The output of the communication channel is connected, and the direct and inverse outputs of the first trigger are connected respectively to the first input of the first element AND and to the read input of the summing counter, the second inputs of the first and second elements AND being the fifth and sixth inputs of the device, the seventh input of which is the drive read input.

На фиг. 1 представлена структурна схема предлагаемого устройства; на фиг. 2 - временные диаграммы его работы.FIG. 1 shows a block diagram of the proposed device; in fig. 2 - time diagrams of his work.

Устройство дл передачи и приема дискретной информации содержит на передаче блок 1 выделени фронта сигнала, триггер 2, первый элемент И 3. суммирующий .счетчик k, второй элемент И 5 вычитающий счетчик 6, элемент ИЛИ 7, третий элемент И 8, генератор 9 ПСП, блок 10 задержки, канал 11 св зи, на приемной стороне блок 12 выделени ПСП, блок 13 срав нени , генератор И ПСП, первыйA device for transmitting and receiving discrete information contains on transmission a signal edge selection block 1, trigger 2, first element AND 3. summing counter k, second element AND 5 subtracting counter 6, element OR 7, third element AND 8, generator 9 SRP, delay unit 10, communication channel 11, on the receiving side, block 12, bandwidth allocation, block 13, comparison, generator AND memory bandwidth, first

триггер 15, первый элемент И 16, суммирующий счетчик 17, накопитель 18, вычитающий счетчик 19( дешифратор 20, второй триггер 21, инвертор 22, второй элемент И 23,(I - вход устройства, И - вход опорных импульсов , 111 - вход счетных импульсов, IV, V - входы быстрых тактовых импульсов (БТИ) , VI - вход счетных импульсов , Vn - вход опорных импульсов).trigger 15, first element AND 16, summing counter 17, accumulator 18, subtractive counter 19 (decoder 20, second trigger 21, inverter 22, second element 23, (I is a device input, I is an input of reference pulses, 111 is an input of counting pulses, IV, V - inputs of fast clock pulses (BTI), VI - input of counting pulses, Vn - input of reference pulses).

Устройство работает следующим образом .The device works as follows.

Передаваемый дискретный сигнал фиг. 2о() поступает на вход устройства . На второй вход первого элемента И 3 со входа .111 счетных импульсов поступает последовательность счетных импульсов (СИ), показанна на фиг. 2 . В произвольные относительно передаваемого дискретного сигнала моменты времени на входе 11 по вл ютс импульсы опорной последовательности (фиг. 2(5) , период следовани которых Т до/ркен быть меньше,The transmitted discrete signal of FIG. 2o () is fed to the input device. The second input of the first element And 3 from the input .111 counting pulses receives a sequence of counting pulses (SI), shown in FIG. 2 At arbitrary with respect to the transmitted discrete signal, the time points at the input 11 appear pulses of the reference sequence (Fig. 2 (5), the tracing period of which T to / rken be shorter,

чем минимальна длительность единичного элемента передаваемого дискретного сигнала Т, т.е. КТ. При этом в интервале между двум опорными импульсами не может быть более одного фронта в передаваемом дискретном сигнале. При поступлении опорного импульса на вход считывани суммирующего счетчика 4 последний устанавливаетс в исходное состо ние. Этим же сигналом триггер 2 (фиг. 2е)than the minimum duration of a single element of the transmitted discrete signal T, i.e. CT In this case, in the interval between two reference pulses there can be no more than one edge in the transmitted discrete signal. When the reference pulse arrives at the read input to the summing counter 4, the latter is reset. The same signal trigger 2 (Fig. 2e)

устанавливаетс в единичное состо ние . При этом счетные импульсы через открытый сигналом с выхода триггера 2 первый элемент И 3 поступают на входы суммирующего счетчика kset to one. In this case, the counting pulses through the open signal from the output of the trigger 2, the first element And 3 arrive at the inputs of the summing counter k

(фиг. 2ж). Одновременно под дейстBkteM опорного импульса через второй элемент И 5 производитс запись информации о пол рности входного сигнала в дополнительный разр д суммирующего счетчика k (фиг. 2(). В момент смены пол рности в передаваемом дискретном сигнале нЪ выходе блока 1 выделени фронта сигнала по вл етс сигнал (фиг. 27,), к;,оторый устанавливает триггер 2 в нулевое состо ние .(Fig. 2g). At the same time, the reference pulse through the second element And 5 records information about the polarity of the input signal into the additional discharge of the summing counter k (Fig. 2 (). At the time of changing the polarity in the transmitted discrete signal, H output The signal (Fig. 27,), k ;, which sets trigger 2 to the zero state.

При этом счетные импульсы через первый элемент И 3 не поступают на вход суммирующего счетчика k. ПриIn this case, the counting pulses through the first element And 3 do not arrive at the input of the summing counter k. With

Claims

When the next reference impulse arrives, the readings of summing counter k are rewritten into subtractive counter 6. When a combination other than zero appears, in bits of subtractive counter 6, the third AND 8 element opens through the OR 7 element, through which the clock input of the generator 9 SRP and Fast clock pulses (BTIs) begin to arrive at the counting input of the detracting counter 6, the frequency of which is () times higher than the frequency of the nominal clock pulses (where n is the number of bits of the memory bandwidth generator). Fast clock pulses are applied until subtractive counter 6 is set to zero. In this case, the BTI feed is stopped. Under the action of these fast clocks for a time not exceeding the period of the nominal clock frequency, a phase shift is generated in the generator 9 SRP by the number of steps equal to the decimal digit corresponding to the binary combination of the number of counting pulses (SI received at the input of the summing counter 4. Under the action The TI of the nominal frequency through the delay unit 10 is issued to the input of the channel 11 of the communication channel with a new phase. As can be seen, the said binary combination contains information about the type of transition in the transmitted signal and that what number of periods of counting pulses shift this transition relative to the reference pulse. This allows you to restore the transmitted signal at the reception. The sequence received from the output of the communication channel 11 of the SRP extraction block 12. In the presence of an error-free plot in the received / sequence, using the block 12, the memory bandwidth is determined by the value of its phase. From the output of the memory block 12, the signal that sets the first trigger 15 into one state, which leads to the opening of the first ementa 16 and then to the input of the summing counter 17 and to the input of the generator 1 begins to flow SRP BTI and making t shift previously received (previous) with respect to a received SRP. The shift is carried out until the phases of the indicated sequences coincide, and the signal from the output of the comparator unit 13 sets the first trigger 15 to the zero state. The signal from the inverse output of the first trigger 15 rewrites the readings of the summing up counter 17 into the accumulator 18. The readings of the summing up counter 17 are a binary combination entered on the transmitting side. From the input VII of the reference pulses at the receiving side, at arbitrary moments of time relative to the reference pulses on the transmitting side, the pulses of the receiver reference sequence with a period T arrive. cells of the subtractive counter 19, and the information signal about the type of transition in the transmitted discrete signal is fed to the control input of the second trigger 21 and sets it to the desired state. At the moment of recording a non-zero combination, a zero signal appears at the output of decoder 20 at the output of decoder 20, which through the inverter 22 opens the second element AND 23, through which counting pulses start to flow to the input of subtractive counter 19. When the subtracting counter 19 is set to the initial zero state, a single signal appears at the output of the decoder 20, which causes the second element 23 to close and the counting pulses to the input of the subtracting counter 19 stop. The same signal goes to the second trigger input 21 and sets it to the state corresponding to the information signal of the type of transition. Consequently, during each time interval, the duration of D at the reception, the initial discrete signal restores of the transmission. I. Thus, in the proposed device, an increase in the reliability of the transmitted information is achieved due to the introduction of redundancy and the use of corrective properties of the memory bandwidth. In addition, this device does not require a channel and a phase phasing device, as well as its use provides asin-r chronic input (output) of the transmitted Discrete information; the device provides higher accuracy of restoring the original discrete signal or the same accuracy with less redundancy, which is equivalent to an increase in the transmission rate. Apparatus of the Invention A device for transmitting and receiving discrete information comprising on the transmitting side a signal edge separator, a trigger, two elements, AND, and a summing counter, to the input of which the output of the first element MeHja I is connected, and on the receiving side - two elements, Two triggers and a summing counter, characterized in that, in order to increase the reliability of the transmitted information, a third AND element is introduced on the transmitting side, a pseudo-random sequence generator (PSP) and a block of delays connected in series as well as a series-connected subtractive counter and an OR element, the output of which is connected to the first input of the third element AND, the output of which is connected to the clock input of the PSP generator and the counting input of the subtractive counter, and the outputs of the summing counter are connected to the inputs of the subtractive counter. the input of which is connected to the output of the second element I, the first input of which is combined with the input of the signal edge extraction unit and is the input of the device, and the output of the signal edge selection unit is connected to the trigger trigger input, the unit input of which is combined with the second input of the second element AND and the counting input of the summing counter is the second input of the device, while the trigger output is connected to the first input of the first element AND, and the output of the delay unit is connected to the input of the communication channel, the second inputs of the first and third elements are AND the third and fourth inputs of the device, respectively; at the receiving side, the SRP generator, the comparison unit and the SRTP extraction unit, as well as the inverter f, are connected in series A subtractor and a decoder, the output of which is connected in series to the inverter and the second element I is connected to the counting input of the reading counter and the input of the second trigger directly, to the control input of which is connected an additional output of the accumulator, to the inputs of the summing counter, to the counting input which, as well as to the clock input of the PSP generator, is connected to the output of the first element I, while the outputs of the PSP generator and the PSP extraction unit are connected to the inputs of the comparison unit, The output of which is connected to the zero input of the first trigger, to the single input of which is connected the output of the PSP extraction block, to the input of which the output of the communication channel is connected, and the direct and inverse outputs of the first trigger are connected respectively to the first input of the first And element and to the read input of the totalizer , while the second inputs of the first and second elements And are respectively the fifth and sixth inputs of the device, the seventh input of which is the read input of the storage device. Sources of information taken into account in the examination 1. Budanov A.V. Kognovitsky O.S. Transfer of scattered information on the QM path using the time interval measurement method. Issues of educational institutes of communication L., 976, no. ff 73, p. 72-79 (prototype). b I I I I I I I I I I I I I I I I I I I And MM II I