SU1720164A1 - Device for sequential data exchange with handshaking - Google Patents

Abstract

The invention relates to communication technology. The aim of the invention is to increase throughput. The device contains a receiver with discriminator blocks of pulse duration and readiness for reception and a transmitter with blocks of the shift register and logic of forming data pulses and synchronization, which are manipulated in duration. RS-triggers and a D-trigger are entered into the device, which ensure that data from the information source is entered into the transmitter shift register without confirming readiness to receive. 1 il.

Description

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The invention relates to a communication technique and can be used in the construction of pulse-width manipulation transceivers.

The purpose of the invention is to increase throughput.

The drawing shows a structural electrical circuit of the proposed device.

The device contains 1 clock pulse generator, amplifier 2, low-pass filter 3, shaper 4 rectangular pulses, first counter 5, first decoder 6, first RS flip-flop 7, flip-flop 8, buffer full, first (OR element 9, second block 10 delays, second counter 11, second decoder 12, second RS flip-flop 13, first delay block 14, third RS flip-flop 15 third delay block 16, sixth RS flip-flop 17, fourth delay block 18, first rep-page 19 shift . ha, second D-flip-flop 20, second element

OR 21, consumer information block 22, information source 23, second shift register 24, frequency divider 25, first multiplexer 26, AND element 27, fifth delay block 28, third counter 29, third decoder 30, third D-flip-flop 31, second multiplexer 32, first D-flip-flop 33, shaper 34 short pulses, fifth, fourth RS-flip-flops 35 and 36, fourth D-flip-flop 37, third element OR 38.

A device for receiving and transmitting data operates as follows.

Divider 25 divides the frequency of the clock generator 1 and generates at its four outputs () four sequences of pulses of different duration T1 T2 TZ T4, fed to multiplexer 26. The selection of a series of pulses and their duration at the output of multiplexer 26 depends on the value of the signals at its control inputs. With the help of the imager 34 on the falling edge of each pulse occurs

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synchronizing the counters of the divider 25 to obtain pulses with a ratio of 1/2. Data from source 23 is written in parallel code to register 24.

The data tracking strobe sets counter 29 to zero. Assuming that the D-flip-flop is in state 1, another pulse front from the output of the RS flip-flop 36 D-flip-flop 31 is set to enable the And 27 element to perform a shift in register 24 and counting the number of transmitted bits by the counter 29. In addition, the control inputs of the multiplexers 26 and 32 are set to the values of the signals that provide the formation of pulses of duration T1 and T2. Next, there is a shift on each falling edge of the pulses from the output of the data multiplexer 26 in register 24.

Depending on the value of the next bit, a pulse of duration T1 or T2 is formed. At the end of the transfer, the signal changes at the output of the decoder 30 (the code stored in counter 29 corresponds to the number of transmitted bits in each data field), the D-flip-flop 37 is set to O, and the third element OR 38 sets the D-flip-flop 31 to the state , providing the transmission of synchronization pulses with a duration of TZ or T4, termination of information shift in the register 24 and counting the number of pulses by the counter 29.

The duration of the synchronization pulses depends on the state of the D-flip-flop 33. The information on the D-flip-flop 33 is recorded on each leading edge of the pulse from the output of the RS flip-flop 35 and depends on the readiness of the device to receive. The installation of 1 R-S flip-flops 35 and 36 occurs on the leading edge of the pulses from the outputs of divider 25. The reset of D-flip-flop 33, RS-flip-flops 35 and 36 is performed at the end of the formation cycle of each pulse at the output of multiplexer 26 by a signal from the output of shaper 34.

The delay in entering information about the state of readiness to receive in D-flip-flop 33 for the pause period allows the TZ to prepare during this time to receive data from the communication line by reading the information from the register 19 by the consumer and to transmit a readiness signal to the synchronization pulse generation cycle . As a result, the throughput of the device is increased. A reset of the D flip-flop 33 at the end of each pulse into a state that provides for the formation of pulses of duration T4 is necessary to eliminate the influence on the operation of the transient device.

Upon completion of the transfer of the next field of information, the signal from the output of the decoder 30 is fed to the input of source 23 and informs it of its readiness for transmission,

5 to this signal, the source 23, in the synchronization pulse shaping cycle with a duration of 3 seconds, writes the next data field to the register 24 and resets to the O counter 29. However, the presence of the D flip-flop 37 at the O stage prevents it from receiving through the element OR 38, setting the clocked pulses of the D-flip-flop 31 into a state that ensures the continuation of data transmission until the signal of readiness-to-receive from the remote subscriber is received. After receiving a signal of readiness to receive on the falling edge of the sync pulse, it is set to 1 D-flip-flop 20, signal c. output

0 which sets to 1 D-flip-flop 37, which in turn causes a reset to O of the D-flip-flop 20.

As a result, at the output of the element OR 38, a signal is generated that provides

5 resolution of data transmission on the front of the next clocking pulse. As a result of the presence of the RS flip-flop 36, the front of the clock pulse at the clock input of the D-flip-flop 31 is shifted relative to the falling edge of the pulse at the output of the multiplexer 26 by the amount of pause T1, which increases the throughput of the device. When this occurs, the transition to the data transfer mode is already in progress.

5 forming a synchronization pulse in it. initial stage with a duration of T1.

The analog input signal from the communication line through the input amplifier 2, the low-pass filter 3 and the shaper 4 direct coal pulses are fed to the blocks 5, 11, 19. The pulse arriving at the installation input of the counter 11, allows you to start measuring its duration by counting the pulses from the output of the clock generator 1.

5 Depending on the duration of the input pulses, the decoder 12 is set to 1, the triggers 13, 15, 17.

If the pulse duration is T4, then all the triggers are set to 1;

0 triggers 13 and 15, at T2 - trigger 13. On the falling edge of the input pulse, data is shifted in register 19. A delay is required, provided by delay block 14. At the same time, the number 5 of the received bits is counted by the counter 5. If at least one bit is received, then the signal from the output of the decoder 6 is set to 1 trigger 7, which means the receiver is busy,

After receiving the entire data field with a known fixed number of bits, it is set to 1 trigger 8 and, via the OR element 21, switches the state O to the trigger 7. With the help of the OR element 9 a signal is generated To receive is not ready, arriving at the D input of the trigger 33. memorized on the front of the pulse arriving at the C input of the D flip-flop 33. The Buffer signal is filled from the output of the flip-flop 8 through the delay block 10 to the input of the register 19, prohibiting shift in it. At the same time, it enters block 22. After reading data from register 19, block 22 sets trigger 8 to O.

When synchronization pulses of TZ or T4 duration are received, the flip-flop 7 is reset to zero, the counter is set to zero.5 of the received bits. On the falling edge of the synchronization pulse, a readiness signal is received from trigger 17 to D-flip-flop 20. The latter occurs only when there is no signal at the setup input of D-flip-flop 20 and corresponds to the completion of data transfer. The required delay of the synchronization signals is provided by the delay blocks 16 and 18. As a result, if the information source 23 has entered the data into the register 24 for transmission, then the third D-three of source 37 is set to 1, the second D-flip-flop 20 is reset, and the data transfer continues. If the data is not recorded from the information source 23 to the shift register 24, then only the D-flip-flop 37 is set to 1 and the D flip-flop is set to 20. The data transfer continues after it is written to the register 24.

At the end of the input pulse (during a pause), the trigger 13,15,17 and the counter 11 are reset and the count is terminated last.

The fifth input of the first multiplexer and the first input of the second multiplexer are connected to the output of the delay block 28, since in a real device the D-trigger 31 of the synchronization pulse generation performs the signal delay function.

Claims (1)

Apparatus of the device for serial data communication with handshaking, containing serially connected amplifier, low pass filter, square pulse shaper, first counter, first decoder, first RS trigger, first OR element and first D trigger, successively connected second counter, second descrambler, second RS trigger, first block, delay, first shift register, information consumer block, trigger buffer filled and second delay block, the output of which is connected to the second input of consumer information block and second input of first shift register 5, second second decoder output through serially connected third RS flip-flop and third delay block connected to second the input of the first counter, the first input of the second D-flip-flop and the first input of the second OR element, the second input of which is connected to the second input of the first, the OR element and the trigger output, the buffer is full, the second input The second D-flip-flop is connected to the fourth output. 5 of the delay unit, the output of the direct-angle pulse shaper is connected to the first input of the second counter, the second inputs of the second and third RS-flip-flops and the third input of the first shift register, the output of the clock pulse generator is connected to the second input of the second counter and the first input of the first frequency divider, the first, second, third outputs of which are connected respectively with the first, second, third 5 inputs of the first multiplexer, the output of the third D-flip-flop through the fifth delay block is connected to the first input of the second multiplexer, the output of which is connected to the fourth input of the first multiplexer 0, the fifth input of which and the first input of the element I are connected to the output of the fifth delay unit, the output of the first multiplexer is the output of the device and is connected to the second input of the element I and through a generator of short pulses to the second input of the frequency divider and the second input of the first D-flip-flop , the first output of the information source is connected to the first input of the second shift register, the second input of which and the first input of the third counter are connected to the second output of the information source, the output of the AND element is connected to the third input of the second register the shift country and the second input of the third counter, the output of which is connected to the input of the third decoder, the output of the second shift register is connected to the second input of the second multiplexer, the output of the second OR element is connected to the second input of the first 0 RS-flip-flop, the second output of the first decoder is connected to the second input of the trigger, the buffer is filled, and the third OR element, characterized in that, in order to increase the bandwidth, 5, the fourth, fifth, sixth RS-flip-flops and the fourth D-flip-flop are entered, the fourth output of the frequency divider is connected to the sixth input of the first multiplexer, the output of the fourth D-flip-flop is connected to the first input of the third element OR and the third input of the second D-flip-flop, the output of the third decoder is connected to the input of the information source, the second input of the third OR-element and the first input of the fourth D-flip-flop, the output of the third OR-element is connected to the first input of the third D-flip-flop, the second D-flip-flop Connected to the second input of the fourth D-flip-flop, the output of the short pulse shaper is connected to the first inputs of the fourth and fifth RS-flip-flops, the second inputs of which are connected respectively to 0 the first and third outputs of the frequency divider, the output of the fourth RS flip-flop is connected to the second input of the third D-flip-flop, the output of the fifth RS flip-flop is connected to the third input of the first D-flip-flop, the output of which is connected to the third input of the second multiplexer, the third output of the second the decoder is connected to the first input of the sixth RS flip-flop, the second input of which is connected to the output of the square pulse shaper, the output of the sixth RS-flip-flop is connected to the input of the fourth delay unit.