RU2051471C1 - Method of and device for converting parallel code into period-modulated signal - Google Patents

Abstract

FIELD: digital engineering. SUBSTANCE: method of converting parallel code into period-modulated signal is set of operations for shaping and transmitting start-stop signals in the form of a.c. voltage period of one duration involving sequential transmission of code combinations of data array in the form of a.c. voltage periods, each of them being linearly dependent of respective value of n-bit code transmitted while data array to be transmitted is divided into data blocks of N=mn bits; m data items, each containing n bits, are separated from each block and converted into m a.c. voltage periods. Device implementing this method has data storage and retrieval unit 1, controlled frequency divider 2, pulse counter 3, reference-frequency pulse generator 4, and output 5 of device, all interconnected functionally. EFFECT: facilitated signal transmission over communication channels; improved design of device. 2 cl, 2 dwg

Description

 The invention relates to digital technology and communication and can be used to convert a parallel code into a signal convenient for serial transmission over communication channels without being accompanied by a clock signal (in asynchronous communication systems).

 There are various methods and devices for converting a parallel code into a serial one and transmitting it via communication channels [1] They are based on the reception of digital information in the form of a parallel code, storing it in a storage device (parallel register) and sequential bit-wise extraction of information. Subsequently, sequentially extracted information is used to modulate some subcarrier in amplitude (AM), phase (FM), or frequency (FM). Information transfer can be accompanied by clock signals (synchronous data transfer) or go in start-stop mode.

 However, these methods and devices with a limited frequency band of a communication channel, for example telephone, have a low information transfer rate.

Known methods and devices for transmitting two or more bits of information at the same time, for example, a method of sequential transmission of information using multi-frequency combined coding [2]
Closest to the proposed are the method and device used in various data transfer controllers and providing a sufficiently high speed of information transfer [3]
However, these method and device also have a low information transfer rate.

 The technical result of the invention is to increase throughput while simplifying the technical implementation.

This result is achieved in that in a method for converting a parallel code into a periodically modulated signal, including generating and transmitting start-stop signals in the form of an alternating voltage period of one duration and sequential transmission of code combinations of the information array in the form of alternating voltage periods, each of which is linearly dependent from n bits of the transmitted code, the information array to be transmitted is divided into information blocks of N m ˙ n bits, from each information block m yayut information packages on n bits (bits) each, convert them to m periods of the AC voltage, the duration T _i of each of which is formed according to the law:
T _i (K ˙ 2 ⁿ + l _i ) ˙ T _о , (1) where K is an integer selected from the beginning of the natural series;
l _{i is the} code value of the transmitted n-bit binary code, 0 ≅ l _i ≅ 2 ⁿ 1;
T _{o the} reference time value corresponding to the code value l _i 1;
n bit depth of the transmitted code.

 To achieve this result, in a device containing an information storage and output unit for N n ˙ m bits, a frequency divider controlled by a conversion factor, with n control inputs, n control inputs of which are connected to n outputs of a storage and information output unit, a sync generator whose output is connected with a counting input of a controlled frequency divider, the output of a controlled frequency divider is connected with the output of the device and with the first control input of the information storage and output unit, an additional meter with a capacity of m + 1 is introduced, ny input of which is connected to the output of the frequency divider managed, the output capacity of the counter m + 1 is associated with a second control input of the storage unit and outputting the information managed by a frequency divider is provided with n + 1 control input of which is connected to the output of the counter capacity m + 1.

 In FIG. 1 shows a diagram of a device that implements the proposed method; in FIG. 2 waveforms of signals at various points in the circuit (the number (position) of the waveforms in Fig. 2 coincide with the circuit numbers shown in Fig. 1; in Fig. 3 and 4, improved circuitry of the device.

In FIG. 1 shows an information storage and delivery unit 1 having an information bus D _i , an n-bit output bus D _o , a first control input C providing sequential output of information, a second control input W that allows (providing) parallel recording of information, a controlled frequency divider 2 having n + 1 control input, counting input C and output Q, 3 pulse counter with capacity m + 1, having counting input C and output Q, 4 pulse generator of the reference frequency (period T _o ), output 5 of the device (Fig. 1) and the output signal (Fig. 2) managed cases of Tell 2 frequency, n-bit output bus 6 D _o of the storage unit and outputting information l and conditioned "by weight" l _i transmitted n-bit word (FIG. 2), data input 7 of the apparatus and unit 1 is the storage and delivery of information (FIG. 1) and the change of this information at the input of the device (Fig. 2), the output 8 Q of the counter 3 (Fig. 1) and the voltage waveform at its output (Fig. 2).

 The device operates as follows.

If there is an enable signal at input W of block 1 (from the output of counter 3), information is recorded from input D _i to block 1. At the beginning of the same pulse, the controlled frequency divider at input n + 1 is switched to a mode with a fixed and maximum division coefficient independent of from information on the remaining control inputs (this mode exists in industrial meters, for example, in the 564IE15 chip). The same mode when implemented in a microprocessor system can be programmed in microprocessor circuits, for example, in the 580IV53 chip). From this moment, the start-stop signal period begins to form.

 At the end of the formation of this period, the unit from the n + 1-th control input of the controlled frequency divider 2 is removed and its division coefficient becomes dependent on the information on its control inputs.

 The first n bits set by block 1 translate the controlled frequency divider 2 into a mode with a division coefficient in accordance with [1] In this case, each period of the signals at output 5 of the device will be proportional to the "weight" of information in an n-bit number transmitted in a given period of time.

 After the formation of m periods of the output signal, i.e. after extracting all N bits from the storage unit and issuing information 1, the input of counter 3 receives the m + 1st pulse, and from the output of the counter 3 pulses to the n + 1st control input of the controlled frequency divider 2 and the input W of block 1 a signal that transfers the controlled frequency divider 2 to the start-stop signal generation mode and enables the recording of new information in block 1. From this moment, a new cycle of formation of a series of periods of the output signal begins.

 It should be noted that information can be recorded in block 1 during the entire time the start-stop signal is generated. Everything will depend on the specific execution of the storage and delivery unit of information and the system in which the device is used. Otherwise, the operation of the device will not change.

Claims (2)

1. A method of converting a parallel code into a periodically modulated signal, including the generation and transmission of start-stop signals in the form of an alternating voltage period of one duration and the sequential transmission of code combinations of the information array in the form of alternating voltage periods, each of which linearly depends on the corresponding value of n- bit transmitted code, characterized in that the information array to be transmitted is divided into information blocks of N m · n bits, from each information m th block is isolated on information packages n digits (bits) each converted to m periods of the AC voltage, the length T _i of each of which is formed by law
T _i (k 2 ⁿ + l _i ) T _o ,
where k is an integer selected from the beginning of the natural series;
l _{i is the} code value of the transmitted n-bit binary code;
o ≅ l _i ≅ 2 ⁿ 1;
T _{o the} reference time value corresponding to the code value l _i 1;
n bit depth of the transmitted code.  2. A device for converting a parallel code into a periodically modulated signal, comprising a unit for storing and outputting information on N n · m bits, a frequency divider controlled by a conversion factor, with n control inputs, n control inputs of which are connected to n outputs of the information storage and output unit , a clock generator, the output of which is connected to the counting input of a controlled frequency divider, the output of a controlled frequency divider is connected to the output of the device and the first control input of the information storage and output unit, characterized the fact that it additionally has a counter with a capacity of m + 1, the counting input of which is connected to the output of a controlled frequency divider, the output of a counter with a capacity of m + 1 is connected to the second control input of a unit for storing and issuing information, the controlled frequency divider is equipped with (n + 1) - m control input, which is connected with the output of the counter with a capacity of m + 1.

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