SU1027838A1 - Device for transmitting and receiving discrete information - Google Patents

Description

PSP recognition unit, inverter and counter, successively connected additional comparison unit, first control unit and additional PSP generator, as well as an adder and second control unit, the output of the PSP release unit connected to the input of the PSP identification unit, the other output of which is connected to one input element And, the other input of which is connected to the output of the counter, which is also connected to one input of the first control unit and the first input

the house of the second control unit, another input of which is connected to the output of the comparison unit, another input of which is connected to the output of the adder, the inputs of which are connected respectively to another output of the PSP extraction unit and the output of the multiplier connected to the AND element, and the output ne (his control unit connected to one input of the OR element, the other input of which is connected to the output of the second control unit, also connected to the input of the SRP generator.

The invention relates to communications and can be used to transmit discrete information with high speed and reliability. A device for transmitting and receiving discrete information is known, comprising on the transmitting side a signal edge separator, a trigger, two AND elements and a summing counter, to the input of which the output of the first And element is connected, and on the receiving side two Element elements And, two triggers and a summing counter C 13. However, this device has low reliability of the transmitted information. Closest to the present invention, there is a device for transmitting and receiving discrete information, containing on the transmitting side a signal edge selection unit, the output of which is connected to the zero input of the trigger, whose course is connected to the first input of the first element. And, the output of which is connected to the first input of the summing counter, the second input of which, the single trigger input and the first input of the second element I. . combined and are the first input of the device, the second input of the second element AND is combined with the input of the signal edge extraction unit and is the second input of the device, the output of the second element AND is connected to the third input of a summing counter, the outputs of which are connected to the inputs of the OR element through the subtractive counter, the output of which is connected to one input of the third element I, the output of which is connected to the corresponding input of the detracting counter, the second inputs of the first and third elements AND are the additional inputs of the device, The output of the pseudo-random sequence (PSP) is connected to the delay unit, the output of the communication channel is connected to the receiving side containing the PSP extraction unit, element I, the PRSP generator, the output of which is connected to one input of the comparator unit, the outputs of the summing counter through serially connected accumulator, subtractive counter connected to the inputs of the decoder, the output of which is connected to the input of the output trigger and through an inverter with one input of an additional element And the output of which is connected to the corresponding input m subtracted. the counter, the additional output of the accumulator is connected to another input of the output trigger, one of the inputs of the accumulator and the second input to the additional element I are the additional inputs of device 2. However, the known throughput is insufficient. The purpose of the invention is to increase the throughput capacity. To achieve this goal, a device for transmitting and receiving discrete information contains, on the transmitting side, a signal edge selection unit, the output of which is connected to the zero input of a trigger. the output of which is connected to the first input of the first element AND, the output of which is connected to the first input of the summing counter, the second input of which, the single trigger input and the first input of the second element AND are combined and are the first input of the device, the second input of the second element AND is combined with the input of the signal edge selection unit is the second input of the device, the output of the second element AND is connected to the third input of the summing counter, the outputs of which are connected to the inputs of the OR element, the output of which inn with one input of the third element And whose output is connected to the corresponding input of the subtracting counter, the second inputs of the first and third elements And are the additional inputs of the device, the output of the pseudo-random sequence generator is connected to the delay unit, the output of the communication channel is connected to the receiving side PSP extraction unit, And element, PSP generator, the output of which is connected to one input of the comparator unit, the outputs of the summing counter through a sequentially connected drive, subtracting the counter to is connected to the inputs of the decoder, the output of which is connected to one input of the output trigger and through the inverters one input of an additional element I, the output of which is connected to the corresponding input of the subtracter, an additional output of the storage device is connected to another input of the output trigger, one of the output drives and the other input An additional element And are the additional inputs of the device, a divider is inserted on the transmitting side into two, additional serially connected PSP generator and delay block, also an adder, the output of the third element And is connected to the divider's input into two, the outputs of which are connected to the inputs of the SRP generators, and the outputs of the delay blocks are connected to the inputs of the adder connected to the communication channel, an OR element, a multiplier, serially connected block is entered on the receiving side identification of the memory bandwidth, inverter and counter, serially connected additional comparison unit, first control unit and additional memory bandwidth generator, as well as an adder and second control unit, the output of the memory block selection module dinene with the input of the PSP recognition unit, the other output of which is connected to one input of the And element, another input of which is connected to the output of the counter, also connected to one input of the first control unit and the first input of the second control unit, the other input of which is connected to the output of the comparison unit, the other input of which is connected to the output of the c / mmator, the inputs of which are connected respectively to another output of the PSP extraction unit and the output of the multiplier connected to the AND element, and the output of the first control unit is connected to one input house OR element whose other input is connected to the output of the second control unit ,, also connected to the input of the generator SRP. The drawing shows the structural electrical circuit of the device. The device contains a block 1 of the signal front, trigger 2, element 3, summing counter j, element 5, inputs 6 and 7 of the device, subtracting counter 8, element 9 or 9 of device 10, element And 11, divider 12 into two, generators 13 and T SRP, delay blocks 15, adder 16, communication channel 17, allotment block 18, SRP recognition block 19, inverter 20, estimator 21, control blocks 22 and 23, AND element 24, multiplier 25, comparison block 26, adder 27, comparison block 28, element OR 29, summarize The main counter 30, the generators 31 and 32 of the memory bandwidth, the drive 33. The subtracting counter Z. The decoder 35. The output trigger 36, the inverter 37 and the element 38. The proposed device works as follows. The transmitted discrete signal is fed to the input device. The second input element And 3 from input 7 receives a sequence of counting pulses (SI). At arbitrary relative to the transmitted discrete signal points in time 6, pulses of the reference sequence appear, the period of which T must be less than the minimum duration of a single element of the transmitted discrete signal Td, i.e. . In this case, in the interval between two reference pulses there can be no more than one edge in the transmitted discrete signal. When the reference pulse arrives at the read input of the summing counter C, the latter is reset to its initial state. With the same signal, trigger 2 is set to one. When this SI through an open signal from the output of the trigger 2 element And 3 is fed to the input of the summing counter k. At the same time, by the action of the reference pulse — element I 5 records the polarity of the input signal into the additional discharge of the summing counter C. At the moment of polarity change, the transmitted discrete signal at the output of block 1 appears the signal that sets trigger 2 to zero condition. In this case, the counting pulses through the element 3 do not arrive at the input of the summing counter 4. When the next reference impulse arrives, the readings of the summing counter k are rewritten into the subtractive counter B., When a combination other than zero appears, in the bits of the subtracting counter 8 through the element OR 9 opens the element AND 11, through which the divider 12 into two and the counting input of the subtractive counter 8 will receive fast clock pulses (BTI), the frequency of which is 2 () times the frequency of the sequence of nominal clocks (where n - the number of bits SRP generators). The BTI will be fed until subtractive counter 8 is set to zero. In this case, the BTI feed is stopped. Under the action of fast clocks over a time not exceeding the period of the nominal clock frequency, the phases are shifted by the PSP in generators 13 and I. The total phase change of both PSP corresponds to the number of SI) input to the sum, running counter or combination of the primary code recorded in this counter. Under the action of TI of the nominal frequency from the output of the generators 13 and I, through the delay blocks 15, PSP-1 and PSP-2 are output with new phase values to the inputs of the adder 16, where they are elementwise added and the total sequence is fed further to the input of the communication channel 17. The binary combination of the primary code contains information about the type of transition in the transmitted binary discrete signal and how many periods of the counting pulses this transition is shifted relative to the reference pulse. This allows the transmitted signal to be restored at the reception. The total sequence received from the output of the communication channel 17 is fed to the input of the allocation unit 18 of the first SRP-1, from the output of which this SRP, shifted in phase relative to the total sequence received in the total sequence, is fed to the input of the identification block 19 SRP-1. If the receiver receives a sequence that contains no errors or contains an error-free section of length (where K is the capacity of the counter; n is the number of bits of the PSP-1 generator), then from the output of block 19 follows the zero sequence. This is null. the sequence through the inverter 20 enters the counter 21, which, after filling with a signal from its output, opens element AND 2 and in parallel enters the first inputs of blocks 22 and 23. The error-free n-element portion of the first SRP-1 from block 19 enters through the open element AND 2C to the multiplier 25, which performs the functions of reverse phase shift PSP-1 Until it coincides with the phase of the same sequence, taken as part of the total sequence. The p-element PSP-1 section formed at the output of the multiplier 25 and the p-element section of the total sequence from the output of the PSP-1 extraction unit 18 are fed to the inputs of the adder 27, and an error-free p-element section of the second PSP sequence will be formed at the output of the adder 2, received from communication channel 17 as part of a total sequence. In addition, after filling the counter 21, its output receives a signal at the first inputs of blocks 22 and 23, which, in turn, begin to generate BTIs that arrive at the clock inputs of the generators 31 and 32 and to the OR element 29. BTI produced by blocks 22 and 23, must be shifted in time relative to each other, so that when the input of the element OR 29 Ki is received, pulses from block 22 and K

from block 23 at the output of the element OR 29, their number was equal. Under the action of the BTI, the generators 31 and 32 begin to successively change their state with high frequency. The formation of the BTI will continue until the phases allocated by the SRP coincide with the phases of the sequences produced by the corresponding generators 31 and 32. At the moment of coincidence of the phases, the outputs at the outputs of blocks 26 and 28 produce signals to the second inputs of blocks 22 and 23, which, in turn, terminate the formation of the BTI. In this case, the number of BTIs that have arrived at the input of summing counter 30 is a combination of the primary binary code entered on the transfer into the summing counter k. After the termination of the issuance of the BTI by blocks 22 and 23, the readings of the sum counter 30 are overwritten into the drive 33 (the device on whose command this overwrite is made is not shown). From the input of 6 reference pulses at the reception at arbitrary points in time relative to the reference pulses on the transmission, the receiver receives reference pulses with a period T. Each such pulse records the information combination from

the accumulator 33 in the cells of the subtractive counter Z, and the information signal about the type of transition in the transmitted discrete signal enters

to the control input — an output trigger 36 for setting it to the desired state. At the moment of recording a non-zero combination, a zero signal appears at the output of decoder 35 at the output of decoder 35, which opens element 38 through inverter 37, through which counting pulses start to flow to counter 3 and count 3. When the subtractive counter 3 is set to the initial zero state, a single signal appears at the output of the decoder 35, which leads to the termination of the supply of counting pulses to the input of the subtractor counter Z. This same signal arrives at the counting input of the output trigger 36 and sets it to the state corresponding to the information signal about the type of transition. Consequently, during each temporary inverter with duration T at the reception, the initial discrete signal input into the transmission is restored.

Thus, throughput is increased in the proposed device.

Claims (1)

DEVICE FOR TRANSMITTING AND RECEIVING DISCRETE INFORMATION, containing on the transmitting side a signal edge extraction unit, the output of which is connected to the zero input of the trigger, the output of which is connected to the first input of the first element And, the output of which is connected to the first input of the summing counter, the second input of which is a single input the trigger and the first input of the second AND element are combined and are the first input of the device, the second input of the second AND element is combined with the input of the signal edge allocation unit and is the second input of the device, the output of the second AND element is connected to the third input of the totalizing counter, the outputs of which through the subtracting counter are connected to the inputs of the OR element, the output of which is connected to the first input of the third AND element, the output of which is connected to the corresponding input of the subtracting counter, the second inputs of the first and third AND elements are additional inputs of the device, the output of the pseudo-random sequence generator is connected to the delay unit, the output of the communication channel is connected to the receiving side containing the SRP allocation unit, AND element , the generator PSP, the output of which is connected to one input of the comparison unit, the outputs of the summing counter through a serially connected drive, the subtracting counter are connected to the inputs of the decoder, the output of which is connected to one input g of the output trigger and through an inverter with one input of an additional element And, the output of which is connected with the corresponding input of the subtracting counter, the additional output of the drive is connected to another input of the output trigger, one of the inputs of the drive and the other input of the additional element AND is additional inputs of the device. characterized in that, in order to increase throughput ,. device, into it are introduced on the transmitting side a divider for two, additional series-connected PSP generator and a delay unit, · as well as an adder, the output of the third element And connected to the input of the divider by two, the outputs of which are connected to the inputs of the PSP generators, and the outputs of the delay units connected to the inputs of the adder connected to the communication channel, on the receiving side, an OR element, a multiplier connected in series SU Ί 027838 an SRP recognition unit, an inverter and a counter connected in series to an additional comparison unit, a first control unit and an additional PSP generator, as well as an adder and a second control unit, the output of the PSP allocation unit being connected to the input of the PSP recognition unit, the other output of which is connected to one the input of the element And, the other input of which is connected to the output of the counter, also connected to one input of the first control unit and the first input of the second control unit, the other input of which is connected to the output of the unit I, the other input of which is connected to the output of the adder, the inputs of which are connected respectively to the other output of the PSP allocation unit and the output of the multiplier connected to the AND element, and the output of the first control unit is connected to one input of the OR element, the other input of which is connected to the output of the second block control, also connected to the input of the generator PSG1.