SU1191918A1 - Digital matched filter - Google Patents

Abstract

DIGITAL MATCHED FILTER containing the discriminator of the signal whose output is connected to the information input of the first shift register, the output i-ro (i Г, m; m is the size) of which is connected to the i-th input of the first adder whose output is connected to the inputs the first and second threshold blocks, the outputs of which are connected to the first inputs of the first and second elements, respectively, the second inputs of which are connected to the first output of the clock, the second and third outputs respectively to the input of the first the shift register and the synchronization input of the discriminator of the signal, whose information input is the information input of the filter, whose synchronization input is the external clock generator input, the output of the first delay element is connected to the clock input of the second shift register, the information input of which is connected with the output of the first element AND, the first element OR, characterized in that, in order to increase the noise immunity, the third shift register, the second adder, the third bee block, first and second counters, second delay element, RS trigger, D-trigger, third AND element, second, third and fourth OR element and NO element, the output of which is connected to the first input of the second OR element whose output is connected to the D-input of the D-flip-flop, the output of which is connected to the first input of the third element AND, the output of which is connected to the first installation input of the first counter, the output of which overflow is connected to the input of the element NOT and the first input of the third element OR, the output of which is connected to the counting ( L mu in One of the first counter and the third inputs of the first and second elements are And, the second inputs of which are connected to the R input of the RS flip-flop and the counting input of the second counter, the overflow output of which is connected to the S input of the RS flip-flop, whose output is connected to the second input of the third the OR element, the second input of the third AND element, and the first input of the fourth OR element, the output of which is connected to the setup input of the second counter, the D-trigger trigger input and the input of the first delay element, the output of which is connected to the clock input The third shift register, the information input of which is connected to the output of the second element I and AND is connected to the first input of the first element OR, the output of which is connected to the second input of the fourth element OR, the third input of the third element AND and the input of the second delay element whose output is connected

Description

to the second input of the second element OR, information outputs of the second and third shift registers are connected respectively to the first and second inputs of the second adder, output

which is connected to the input of the third threshold unit, the output of the KOTdporo is the information output of the filter, the output of the first element AND is connected to the second input of the first element OR.

one. .

The invention relates to digital devices for processing complex signals and can be used, in particular, in the development of digital data transmission systems for the synchronization of the transmitting and receiving half sets of the system.

The purpose of the invention is to increase the noise immunity of the filter.

FIG. Figure 1 shows the structural scheme of the proposed device for the case when a complex composite signal to which the filter is tuned consists of 15 blocks of units and zeros that form the modulating M sequential composite signal with code 00011П 01011001 (blocks of units and zeros are formed from opposite, carrying M-sequences, each of which also consists of 15 elements, with unit one being transmitted by the following sequence of elements: 000111101011001); in fig. 2 is a graph of voltage variation (in relative units x) at the output of the first adder when several blocks of a composite signal arrive at the filter input without interference.

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Filter Sfig. 1) contains 1 and 2 clock pulse generators, a signal discriminator 3, shift registers 4, 5 and 6, adders 7 and 8, threshold blocks 9, 10 and 11, elements 12 and 13, element 14, delay element 15 (front impulse); a clock pulse generator 2 (Fig. 1) includes counters 16 and 17 (pulses), an RS flip-flop 18, a D-flip-flop 19, the OR elements 20, 21, and 22, AND 23, the HE element 24 and the delay element 25 , information input 26, information output 27, synchronization input 28.

The device works as follows.

In the absence of a signal at input 26 (composite signal and noise), either bits or zeros will be written to all bits of register 4 shift. As a result, the output of the adder 7 will be a constant voltage equal to 8 or 7 units. The signal from the output of the adder 7 is fed to the inputs of the threshold blocks 9 and 10, the response levels of which are configured so that the threshold block 9 generates a pulse at its output when the input signal is 12, 13, 14 or 15 units, and block 10 - at the input signal equal to 3, 2, 1. or o units. Consequently, at the output of threshold blocks 9 and 10, in the absence of a signal at input 26, there will be zero voltages, and elements 12 and 13 are closed at the second inputs.

Under the action of the leading edges of positive polarity pulses, coming from the output of the generator of pulses I to the counting input of pulse counter 16, the latter changes its state from 10,000 to 01111, and the trigger 18 has a zero voltage applied to its P input in the time interval between by pulses, held in the zero state. When the pulse counter 16 is switched to the state 01111, a negative voltage drop is generated at its output and the trigger 18 is switched to the unit state (the unit-level voltage is acting at the P input of the trigger). The positive voltage drop from the output of the trigger 18 through the element OR 20 is fed to the installation input of the counter 16 pulses and sets it to the state of 10,000, at the output of the counter 16 pulses obviously

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the unit voltage level is set. The trigger 18 remains in a single state. At the end of the clock pulse at the P input of the trigger 18, the latter switches to the zero state. Thus, at the output of trigger 18, pulses of positive polarity will be formed with a duration equal to the duration of the clock pulses and a follow-up period equal to 15 periods of the clock pulse following (or equal to the duration of the composite signal block).

The pulses from the trigger output 18 are cut, the element OR 22 is fed to the counting input of the pulse counter 17, and under the action of the leading edges of these pulses, the pulse counter 17 switches to the 100 state. As a result, the output voltage of the pulse counter 17 is set to a single level voltage, which the element OR 22 is supplied to the inputs of the elements AND 12 and 13 and the counting input of the pulse counter 17, and therefore the effect of the pulses from the output of the trigger 18 on the pulse counter 17 is stopped at its output, the unit level voltage is held.

Under the action of the rising edges of the pulses coming from the output of the element OR 20 to the clock input of the trigger 19, the latter is held in the zero state. (At the D-input of the trigger 19 through the element OR 21 comes the zero level. With the output of the element NOT 24 and the outputs of the elements 12 and 13 through the elements OR 14 and delay 25). Pulses from the output of the element OR 20

through the element 15, the delays of the front of the pulses arrive at the clock inputs of the shift registers 5 and 6 and sequentially write zeros to all their bits (zero potentials at the outputs of the And 12 and 13 elements). Due to the fact that the inputs of the adder 8 are connected to the direct outputs of the bits of the registers 3 and 6 of the shift, at the output of the adder 8, the voltage will be zero. And since the threshold unit 11 is set to operate when the voltage at its input is 12 or more units, the output signal at the output 27 of the device will be absent.

The device arrives at its input 26 of the mixture of the composite signal and

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noise, and the input 28 of the synchronization signal works as follows.

Under the action of signals input to the generator 1 clock pulses, the latter produces pulses synchronous with the operation of the clock generator of the transmitting device. At the end of the reception, the unit 3, under the action of pulses arriving at its synchronization input from the output of generator 1, makes a decision on the recognition of the element of the composite signal, and a single or zero signal is generated at its code. This signal arrives at the information input of the shift register 4 and is recorded in its first bit, under the action of a clock pulse arriving at its clock input from the output of the 1 clock pulse generator. At the same time, the information in the shift register 4 is shifted by 1 bit.

If all decisions on recognition of elements of the composite signal block are taken correctly, then at the time when the signal displayed by the sequence of solutions at the output of the discriminator of signal 3 fills the shift register 4, the output of the adder 7 will be the maximum voltage surge. At other times during the reception of the composite signal, when all its elements are correctly received, the matching of decision sequences and the order of connecting the inputs of the adder 7 to the triggers of the shift register 4 is broken and the output of the slope 7 of the 7 processor will show side emissions of the auto-inverse autocorrelation function (MIFAC) block composite signal. If at the moment of matching (at the moment of filling the shift register 4 with all elements of the composite signal block) the unit of the composite signal was received, then the output signal at the output of the adder 7 will be equal to the signal base (in our case 15). In the case of a block receiving a composite signal zero, the voltage at the output of the adder 7 will be zero.

Fig. 2 shows a graph of the change in the voltage value of the signal Uo) at the output of the adder 7 when the device 26 of the code sequence of the blocks 11001 enters the input 26. At the time t О, the decision sequence from the first 15 signal elements is written to the shift register 4. Ngo block). The duration of the signal element is equal to T. The time limit of the block change occurs at the instants of time t 0, 15T, LST, J45T., 60T, etc. As can be seen from the graph, when changing like blocks of a composite signal, the voltage at the output of the adder 7 remains constant f 7 or 8 units) 5 maximum lateral emissions of the MIFAC of the composite signal block at the output of the adder 7 are formed when changing opposite blocks of the composite signal (10 and 5 units) and not x. The thresholds for triggering threshold blocks 9 and 10 are exceeded. Only at the moment of time when the signal of the composite signal block fills the shift register 4 (OT, 15T, OST, 45T, etc.), the maximum outliers ( 15 for the unit one and O for the unit zero voltage J exceeding the thresholds of the blocking stage 9 and 10. Each time one of the thresholds Gshok is triggered (or), the first element opens at the first input (or 13th) I give "(1 ° o mu) element And from the output of the generator 1 so of the output pulses of the proU. o / nt impulse delayed with respect to the clock pulse at the clock input of the shift register 4. The pulses from the outputs of elements 12 and 13 are sent to the information inputs of the shift registers 5 and 6, respectively, and the inputs of the element S1I 14. Let all blocks be The signal is received correctly. At the same time, the threshold unit 9 will operate at the moments of reception of 4, 5, 6, 7, 9, 11, 12 and 15th blocks of the composite signal, and the threshold unit 10 at the moments of reception of 1, 2, 3, 8, 10f of the 13th and 14th blocks of the composite signal. When receiving the 1st block of the composite signal, a pulse from the output of the element I 13 will pass through the elements of ШШ 14 and 20 to the installation input of the counter 16 pulses, the clock input of the D-trigger I9 and to the input of the element 15 of the pulse front. In this case, the pulse counter 16 is set to the state 10000. In addition, the pulse from the output of the OR 14 unit unit reaches the input of the AND 23 element and through the delay element 25 and the OR 21 element to the D input of the trigger 19. The delay element 15 delays of the leading edge of the pulse at such a time that at the moment the pulse arrives at the clock inputs of registers 5 and 6 of shifts, their transients are completely completed from the leading edges of pulses coming from the outputs of the elements 12 and 13 and into the corresponding re The unit shift register is reliably recorded to 1 in the 1st bit. Thus, when receiving 1to a block of the composite signal and the 1st bit of the shift register 6, one will be written, and zero in shift register 5 will be zero. At the end of the pulse at the clock input VT, rigger 19, under the action of its trailing edge, the D flip-flop will be set to one and the element I 23 will open at the 3rd input. Dp reliable recording of the unit in the D-flip-flop 19 requires that the minimum delay time of the delay element 25 is such that the falling edge of the pulse at the D-input of the trigger 19 occurs after writing the unit to the trigger 19. To meet this condition, the delay element 25 can be performed on two elements in series NO. After a time equal to 15 clock cycles of the generator 1, a pulse of a single level is generated at the output of the trigger 18 (the second input of the element 23), and through the element 13 that is opened at the 1st (the threshold unit 10) and the 3rd (at the output of the counter 17 pulses unit level) to the inputs from the output of the generator 1 will pass a pulse corresponding to the reception of the 2nd block of the composite signal. In this case, the specified pulse goes through elements SHSh 14 and 20 to the installation input from counter 16 with some delay in relation to the triggering moment of trigger 18 at input S. Therefore, the pulse counter 16 is reset to the initial state 10000 and always occurs after triggering 18 input S (under the action of

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pulse arriving at the input of the counter 16 pulses through the element 20 or from the output of trigger 18, or from the output of the element OR 14 and trigger 18 simultaneously). As a result, the element And 23 will open through the 2nd inputs under the action of pulses arriving simultaneously at its first and second inputs (the third input element And 23 is already open) and a pulse is divided at its output. In this case, the pulse counter 17 switches to the initial state 000 and a zero voltage is set at its output. At the end of the pulse at the output of the trigger 18 at the 3 inputs of the elements 12 and 13; a zero level is established, and the D-trigger will remain in the unit state.

Under the action of the 2nd clock pulse generated at the output of the delay element 15, 2-unit will be written into the shift register 6, and zero will be written into the shift register 5. When receiving the 3rd block of the composite signal, the threshold unit 10 will again work. During the formation of a pulse at the output of the threshold unit 10, the pulse generator 1 and the pulse generated at its output will start at the moment the output pulse element 13 arrives at the output pulse. having passed through the element OR 22, will open the element AND 13 through the third entrance. As a result, a pulse from the output of the pulse generator .1 passes through the elements AND 13, OR 14 and AND 23 to the installation input of the pulse counter 17 and keeps it in the initial state. At the end of the pulse at the output of the trigger 18 (the output of the element OR 20), the D-trigger will remain in the unit state, since its unit D output voltage is applied (output from the C4et4HKa output of 16 pulses through the HE 24 and OR 21 elements).

3-unit will be recorded in the 6th shift register when receiving the 3rd block of the composite signal, and the third zero is written into the 5th shift register.

When receiving the 4th composite signal unit, the threshold unit 9 will operate, the trigger 18 and the And 12 element will open on the 3rd inputs. Pulse counter 17 and D-flip-flop 19 are held in the initial and single states, respectively. Counter 16 impulses sbro19188

sets to the initial state. In this case, the unit will be written in the 1st bit of the shift register 5, and in the shift register 6, zero.

The reception of subsequent blocks of the composite signal will be produced similarly to the reception of the 3rd (single) and (zero) blocks of the composite signal.

If before receiving the first block of the composite signal, the zeros were recorded in the shift registers 5 and 6, and all the blocks of the composite signal were received correctly, then with each reception of the next block the voltage value at the output of the adder 8 will take the following values: O, 1, 2 , 3, 2, 3, 4, 5, 5, 4, 5, 6, 7, .15.

If all 15 blocks of the composite signal are correctly received, the sequence of numbers 0001111.01011001 will be written to the shift register 5, and the sequence inverse to the shift register 6 will be written. And since the inputs of the adder 8 are connected to the outputs of those bits of registers 5 and b of the shift in which units are recorded when receiving all the blocks of the composite signal, then at the output of the threshold block 11 at the time of recording the last block of the composite signal at registers 5 and 6 a voltage jump will be generated up to a value of 15 units, and the threshold unit will generate an impulse at its output, which indicates that the last element of the composite signal arrives at the filter input.

If, after setting the pulse counter 17 to the initial state, one of the threshold blocks 9 or 10 falsely triggers due to an increase in the noise level at the filter input during the reception of individual blocks of the composite signal, then they are: pulse from the pulse generator 1 output in this case is not pass through elements 12 and 13, since during the operation of threshold block 9 or 10, in this case, at the moment of arrival of the pulse from the output of generator 1 of pulses, the second inputs of elements 12 and 13 of their third inputs will be zero (the pulse form is triggered by the trigger 18 in this case at the moments of arrival of the expected pulses, i.e. at the moments of complete filling of the 4 shift register with the elements of the composite signal block)

If, after the counter 17 pulses are set to the initial state, due to an increase in the noise level, individual blocks of the composite signal are not accepted, then at the time of trigger 18, the pulse at the output of the threshold blocks 9 and 10 will be absent, and therefore the pulse at the installation input of the counter 17 pulses will also be absent and the latter will not be held in the initial state, but will switch to the next state under the action of the pulse coming to its counting input from the output of the trigger 18 through the IL element And, 22, the shift registers 5 and 6 simultaneously write zeros, and D the trigger 19 will remain in the unit state (the constant voltage of the unit level is applied to its D input).

, If the number of received blocks of the composite signal is less than four (the voltage at the output of pulse counter 17 remains zero), then if the next block of the composite signal is correctly received, the pulse from the output of the pulse generator 1 will pass through the element 12 that is open through two inputs , elements of RShI 14 and And 23 will reset the pulse counter 17 to the initial state, and a unit will be written to the corresponding shift register (5 or 6) (zero is written to another shift register).

Thus, after the end of the reception of the last element of the composite signal, the voltage at the output of the adder 8 abruptly changes to a value equal to the number of correctly received blocks of the composite signal. If this number is 12 or more, then the output 27 of the filter will generate a pulse signaling the reception of the composite signal. If 4 or more blocks of the composite signal are not received, a pulse at the filter output will not be formed and the composite signal will not be received (highlighted). If 4 blocks of the composite signal are not received again, then the counter 17 pulses will go to

state 100, a single level is set at its output, and elements 12 and 13 will open at the third inputs. At the D input of the trigger 19, a zero level is set, and the D flip-flop switches to the zero state under the action of a pulse coming from the output of the flip-flop 18, and the filter thus switches to the reception of the next composite signal.

Consider the operation of the device when one of the threshold blocks 9 or 10 malfunctioning (in this case, an interference impulse will be generated at the threshold of the threshold device) before the threshold block 10 triggers when the first block of the composite signal is received correctly. At the same time, There are three cases; the time interval between the two triggers of the threshold blocks 9 and 10 (or one of the 10th) - the false one and from the action of the 1st block of the composite signal - is more or less than the duration of the block of the composite signal.

In the first case, the interference pulse sets the pulse counter 16 to the initial state, and when the threshold unit 10 is triggered when the 1st composite signal unit is correctly received, the pulse counter 17 is reset to the initial state 000, and the generator 2 generates the output Exit. 1 clock pulses for shift registers 5 and 6 at the expected time points and at their corresponding bits will be recorded in the process of receiving blocks of the composite signal if the number of unaccepted items of the blocks of the composite signal is less than four. If the number of unaccepted blocks is no more than 3, then a pulse is formed at the output 27 of the filter at the moment when the reception of the last element of the composite signal ends.

In the second case, under the action of an interfering pulse, the counter 16 pulses will be set to the initial state, and the D-flip-flop 19 will be set to one. However, at the moment the pulse 18 is formed by the pulse trigger, the pulse at the output of the threshold block 9 or 10 will be absent, a zero voltage will be applied at the D input of the trigger 19. As a result, at the moment of termination of the pulse generated by the trigger 1 8, f the D-flip-flop 19 is set to the zero state and the device will be ready to receive the first and subsequent blocks of the composite signal.

In the third case, under the action of the interference pulse, the D-flip-flop 19 is set to one state, and the counter 16 pulses to the initial 5 state. At the moment when the reception of the 1st composite signal block ends, the pulse counter 16 will be reset to the initial state (trigger 18 in this case is not yet triggered), while trigger 19 U remains in the single state. As a result, information will be recorded in the 5th and shift registers in the corresponding bits of the first and subsequent received blocks of the composite signal.

If the interference pulse arrives at the input of the element And 12 (go 13) simultaneously with the formation of the pulse by the trigger 18, then the pulse from the output of the generator 1 of the pulses that passed through the element 12 and (13), OR 14 and 20, and the pulse from the output of the trigger 18, passed through the element OR 20, are merged at the output of the element OR 20 into one and at the moment of their termination the ts-trigger, h 19 switches to a single co-generator 2 - to

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Claims (1)

A DIGITAL AGREED FILTER containing a signal discriminator, the output of which is connected to the information input of the first shift register, the output of the ith (i = 1, m; m is the bit) discharge of which is connected to the i-th input of the first adder, the output of which is connected to the inputs of the first and second threshold blocks, the outputs of which are connected to the first inputs of the first and second AND elements, respectively, the second inputs of which are connected to the first output of the clock generator, the second and third outputs, respectively, to the clock input of the first register and the shift and the synchronization input of the signal discriminator ,, inform · the madion input of which is the information input of the filter “the synchronization input of which is the external synchronization input of the clock generator, the output of the first • delay element is connected to the clock input of the second shift register, the information input of which is connected to the output of the first AND element, the first OR element, characterized in that, in order to increase the noise immunity, a third shift register, a second adder, and a third threshold block are introduced into it , first and second counters, second delay element, RS-trigger, D-trigger *? · ger, third AND element, second, third and fourth OR elements and NOT element, the output of which is connected to the first input of the second OR element, whose output is connected to the D-input of the D-flip-flop, whose output is connected to the first input of the third AND element, whose output is connected to the first installation input of the first counter, the overflow output of which is connected to the input of the NOT element and the first input of the third OR element, whose output is connected to the counting first entry and the third inputs of the first and second elements AND, the second inputs of which are connected to the R-input of the RS-trigger and the counting input of the second counter, the overflow output of which is connected to the S-input of the RS-trigger, the output of which is connected to the second input of the third OR element, the second the input of the third AND element and the first input of the fourth OR element, the output of which is connected to the installation input of the second counter, the synchronization input of the D-trigger and the input of the first delay element, the output of which is connected to the clock input of the third shift register, information the input of which is connected to the output of the second AND element and is connected to the first input of the first OR element, the output of which is connected to the second input of the fourth OR element, the third input of the third AND element and the input of the second delay element, the output of which is connected 8161611 '' HS to the second input of the second OR element, the information outputs of the second and third shift registers are connected respectively to the first and second inputs of the second adder, the output of which is connected to the input of the third threshold block, the output of which is the information output of the filter, the output of the first element And is connected to the second input of the first element OR.