SU1120315A1 - Calculating device - Google Patents

Abstract

COMPUTATIONAL DEVICE, containing a pulse generator, two AND elements, two counters, two D triggers, an R5 trigger, a counting trigger, a switch, an OR-NOT element and an NAND element, the output of the pulse generator connected to the first input of the first AND element, the bit inputs of the first and second counters are connected to the inputs of the first and second operands, respectively, the output of the second element I is the output of the device difference, the information inputs of the first and second D triggers are connected to the device start input, the clock input of the first This D-trigger is connected to the output of the pulse generator, the output of the first B-trigger is connected to the second input of the first element I, the third input of which is connected to the upper section of the AND-NOT element, the output of the first element I connected to the counting input of the counting trigger and the first information input of the switch, the second information input of which is connected to the output of the counting trigger, the clock input of the second D-flip-flop, the counting inputs of the first and second counters and the first input of the second element And, the second input of which is connected to the inverse output R5-trigger The first control is controlled by the input of the switch, the second control input of which is connected to the output of the second D-flip-flop, and the third control input of the switch is connected to the forward output of the R5 trigger, the installation input of which is connected to the input of the initial installation of the device and the reset inputs the second D trigger, the counting trigger, the first and second counters, the overflow output of the first counter is connected to the first inputs of the AND-NOT and OR-NOT elements, the overflow output of the second counter is connected to the second inputs of the AND-NOT and {OR-NOT) elements. output element OR NOT - with input. SP house reset RS-flip-flop, switch output is the output of the device amount, which is different from. so that, in order to expand the field of application 2 by making it possible to calculate the square root of the sum of the squares of two numbers, the third and fourth D triggers, the third, fourth and fifth And elements and the ISh1 element are entered into it, and the first input of the third element And connected to the first input of the fifth element And and the output of the first element And, the second input of the third element And connected to the inverse output of the counting trigger, the third input of the third element And - the first input of the fourth element And, input, reset the fourth D-trigger and D -triggera second stroke, the output of the third AND element is connected to the first input of the OR gate, a second input coupled to an output of the fifth AND gate, a second input coupled to a direct output of the fourth

Description

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D-TpHrrepa, the third input of the fifth element H is connected to the clock inputs of the third and fourth j) triggers and to the direct output of the counting trigger, the fourth input of the fifth element I to the direct output of the R5 flip-flop, information input of the fourth D trigger with the third output of the third 3) trigger, the inverse output of which is connected to its information input, the second input of the fourth element I is connected to the inverse output of the fourth D flip-flop, the output of the fourth element And is connected to the reset input of the third D flip-flop, the output of the OR element connected to in The output of the square root of the sum of the squares of the two numbers of the device, the output e; 7th of the AND-NOT is the output of the end of the calculation of the device.

one

The invention relates to computing technology and can be used in measurement information systems as an information processing device.

A computing device is known that contains the unit of analysis of units and zeros, the block of equivalence, the triggers of the prohibition of the analysis of units and zeros, the group of elements AND, which form differences by inconsistency and equality, the group of elements OR, elements H OR, inverters and trigger 1.

However, this device is characterized by a large amount of equipment, low speed and limited functionality.

Closest to the present invention is a computing device comprising a pulse generator, two counters, two B-flip-flops, a switch, an RS-flip-flop, a counting flip-flop, two AND elements, an OR element, an EH element, and the NO-OR element .21 .

However, the known device is characterized by insufficient functionality that does not allow the square root of two numbers to be calculated simultaneously with the calculation of the sum and difference of two numbers.

The purpose of the invention is to expand the scope by enabling the square root of the sum of the squares of two numbers to be calculated simultaneously with the calculation of the difference and the sum of these numbers.

The goal is achieved by the fact that a computing device containing a pulse generator, two

And, two counters, two D-trigger, R5-trigger, countable trigger, switch, OR-NOT element and NAND element, the output of the PULSE generator is connected to the first input of the first AND element, the bit inputs of the first and second counters are connected to the inputs of the first and second operands, respectively, the output of the second element I is the output of the device difference, the information inputs of the first and second B-flip-flops are connected to the device start input, the clock input of the first D-trigger is connected to the output of the pulse generator, the output of the first J) trigger - with the second input of the first element I, the third input of which is connected to. the output element AND-NOT, the output of the first element And is connected to the counting input of the counting trigger and the first information input of the switch, the second information input of which is connected to the output of the counting trigger, clock input. the house of the second D-flip-flop, the counting inputs of the first and second counters and the first input of the second element -A, the second input of which is connected to the inverse output of the R5 trigger and the first control input of the switch, the second control input of which is connected to the output of the second D-trigger, and the third control input of the switch is connected to the direct output of the P5 flip-flop, the setup input of which is connected to the input of the initial setup of the device and the reset inputs of the second D flip-flop, counting flip-flop, first and second counters, overflow output first counter is connected to the first inputs of the elements NAND and

3.11

OR-NOT, the overflow output of the second counter is connected to the second inputs of the H-NOT and OR-NOT elements, the output of the OR-NOT element to the reset input R5 of the trigger, the switch output is the output of the device sum, additionally contains the third and fourth D-flip-flops , the third, fourth and fifth elements are AND and the OR element, the first input of the third element AND is connected to the first input of the fifth element AND and the output of the first element AND, the second input of the third element AND is connected to the inverse output of the counting trigger, the third input of the third element AND - with . the first input of the fourth element I, the reset input of the fourth D trigger and the output of the second D trigger; the output of the third element I is connected to the first input of the OR element, the second input of which is connected to the output of the fifth element I, the second input of which is connected to the direct output of the fourth 3) trigger, the third input of the fifth element I is connected to the clock inputs of the third and fourth J-flip-flops and with the direct output of the counting trigger, a quarter of the input of the fifth element And with the direct output of the R5-flip-flop, information input of the fourth D-trigger - direct the output of the third 3) trigger, the inverse output of which is connected to its information input, the second input of the fourth element I is connected to the inverse output of the fourth J) trigger, the output of the fourth element I is connected to the input from the third T) trigger trigger, with the square root output of the sum of the squares of the two numbers of the device, the output of the AND-NOT element is the output of the end of the device calculations.

The drawing shows the functional diagram of the computing device

The device contains an element And 1, element OR 2, element And 3, D-trigger 4 and 5, element And 6, switch 7, R5-trigger 8, D-trigger 9, element-10, counting trigger 11, counter 12, 13 pulse generator, element AND 14, element OR-NOT 15, D-flip-flop 16, counter 17, element-AND-NOT 18, input 19 of the initial installation, input 20 start the device, input 21 of the first number, input 22 of the second number output 23 square sum of squares, output 24 sums, output 25 differences and output 26 of the end of calculations

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The calculation of the square root of the sum of squares in the device is based on the use of an agglomerate of an approximate calculation (the algorithm gives a maximum relative calculation error of about 6%).

The device works as follows.

At the input 19 of the initial installation receives a pulse of the initial installation, which sets the RS-trigger 8 to 1, and the triggers 9, 11 and the counters 12, 17 in O, Logic O at the output of the D-trigger 9 sets the D-trigger 5 and through the element And 3 3) -trigger 4 in O. In the initial state, the D-trigger 16 records O, which prohibits the passage of counting pulses through element 14. At the inputs 21 and 22, the inverse values of the first and second numbers are received, which are written into the corresponding counters. 12 and 17. On the bus 20 mode potential logical 1 comes sig The operation, which is the leading edge of the counting pulses of the generator 13, is recorded in the D-flip-flop 16. The logic 1 signal at the output of the b-trigger 16 allows the counting pulses of the oscillator 13 to pass through the AND 14 element, from which the counting pulses go to the counting input of the counting trigger 11, On the negative front, where the frequency of the pulse of the counting pulses is divided by, two. The pulses from the output of the counting trigger 11 arrive at the counting inputs of counters 12 and 17 (which operate on a negative front), the contents of which for each pulse increase by one. On the first negative edge at the C input of the B-trigger 9, 1 is recorded in it, which goes to the second control input of the switch 7 and allows the counting pulses to pass through it from its first information input.

The logical unit from the output of the 15-trigger 9 also enters the reset inputs of G-triggers 4 and 5, which operate on the negative front, and allows the recording of information in these triggers from the D-inputs. The pulses arriving after setting the D-trigger 9 to one state from the output of the counting trigger 11 control the operation of the B-triggers 4 and 5 as follows: on the first pulse, the D-trigger 4 for .1 is written 1, and in D - the trigger 5, the second pulse in the D-trigg A is written O, and the D-trigger 5 1, the third pulse in the 1) trigge 5 is recorded O, and the D-trigger 4 remains in the zero state, as well as on the setup input the recording time is O. On the arrival of subsequent pulses, the operation of the B-triggers 4 and 5 is similar. At the output of the element And 6 (in the presence of 1 at the second, third and fourth input) the arrival of a counting impulse is formed, the duration of which is equal to the duration of the ctjieTHoro impulse. The number of C0B impulses at the output of the And 6 element is equal to 1/3 of the smaller number, and if the numbers are equal, 1/3 of one of the numbers. After one of the counters 12 or 17 overflows, at the output of the IPI-NE 15 element, an O is formed, which enters the reset input of the KJ trigger 8 and sets it to Q. The change in the state of the R5 trigger 8 switches the KdNMyTaTop 7 to half a day. It is a situation in which impulses from the output of a counting trigger fall on its output. The overflow of the next counter causes the end of output signal (output 26 of the end of the calculation) to prohibit the passage of counting pulses through element 14, at the output of the element | nta OR-NOT 18. If the numbers recorded in the counters 12 and 17 are equal to 1) 1 mi, the signals overflowing from the outputs of the meters 12 and 17 are set on the same counting pulse. In this case, a signal appears at the output of the NANDI element 18, prohibiting the passage of counting pulses through the element 14. 146 Thus, at the output of the element OR 2, pulses are formed, the number of which is equal to the square root of the sum of squares of two numbers, at the output of the switch 7, - the pulses, the number of which is equal to the sum of two numbers, and the output element And 10 pulses, the number of which is equal to the difference of two numbers. The computation time, regardless of the operation being performed, is determined from the ratios 2T (A + 1) + ir, with T CALCIs I 2T (B + 1X.; D5, with where A, B are the operand- and Tg modules). blocking, T is the repetition period of the counting pulses. The repetition period of the counting pulses is chosen from the following considerations where t is the duration of the counting pulse tn is the pause duration. The duration of the counting pulse is limited by the delay time of triggering Triggers 9 and 16, i.e. fcti The duration of the pause between pulses is limited by the delay time of the counters 12 and 17, the element, OR-NOT 15, the triggers 8. and 11, and the switch 7, d-e. Thus, the introduction of two 3) -triggers and three AND elements and an OR element allows the device to be expanded by obtaining the ability to extract the square root from the sum of the squares of two numbers at the same time as their sum and difference.

Claims (1)

A COMPUTER DEVICE containing a pulse generator, two AND elements, two counters, two D-flip-flops, R5-flip-flop, a counting flip-flop, a switch, an OR-NOT element and an AND-NOT element, the output of the pulse generator being connected to the first input of the first AND element, the bit inputs of the first and second counters are connected to the inputs of the first and second operands, respectively, the output of the second element And is the output of the device difference, the information inputs of the first and second D-triggers are connected to the device start input, the clock input of the first D is three the hegara is connected to the output of the pulse generator, the output of the first G-trigger is connected to the second input of the first AND element, the third input of which is connected to the output of the AND element, the output of the first And element is connected to the counting input of the counting trigger and the first information input of the switch, the second information input which is connected to the output of the counting trigger, the clock input of the second D-trigger, the counting inputs of the first and · second counters and the first input of the second element And, the second input of which is connected to the inverse output of the R5 trigger the control input of the switch, the second control input of which is connected to the output of the second D-flip-flop, and the third control input of the switch is connected to the direct output of the R5-flip-flop, the installation input of which is connected to the input of the initial installation of the device and the reset inputs of the second D-flip-flop, counting trigger, the first and the second counters, the overflow output of the first counter is connected to the first inputs of the AND-NOT and OR-NOT elements, the overflow output of the second counter is connected to the second inputs of the AND-NOT and OR-NOT elements, · the output of the OR-NOT element is to o. RS-trigger reset house, the output of the switch is the output of the sum of the device, distinguishing s. I mean, in order to expand the scope by obtaining the ability to calculate the square root of the sum of the squares of two numbers, the third and fourth D-triggers, the third, fourth and fifth elements AND and the OR element are introduced into it, and the first input of the third element AND is connected with the first input of the fifth element And and the output of the first element And, the second input of the third element And is connected to the inverse output of the counting trigger, the third input of the third element And - with the first input of the fourth element And, input, reset of the fourth D - trigger and output the second D-trigger, the output of the third AND element is connected to the first input of the OR element, the second input of which is connected to the output of the fifth element · AND, the second input of which is connected to the direct output of the fourth 51еот ^{, ю_} п§ ·> D-flip-flop, the third input of the fifth element AND is connected to the clock inputs ^; the third and fourth D-flip-flops and with direct output of the counting trigger, the fourth input of the fifth element AND - with the direct output of the R5-trigger, the information input of the fourth D-flip-flop with the direct-output of the third риг) -trigger, whose inverse output is connected to its information input, the second input of the fourth element AND is connected to the inverse output of the fourth D-trigger, the output of the fourth element is connected to the reset input of the third D-trigger, the output of the OR element is connected to the square root of the sum of the squares of the two numbers of the device, the course of the NAND is the output end of the device computing.