SU1652986A1 - Token selector in pattern recognition - Google Patents

Abstract

The invention relates to automation and computing technology and can be used to highlight features in the recognition of speech patterns. The purpose of the invention is to improve the accuracy of the device, achieved by introducing four counters, a pulse generator, the third, fourth, fifth and sixth elements OR, a third trigger, a decoder, which allows to increase the reliability of feature selection from pulse sequences when matching the pulse period in a bundle. 2 Il.

Description

The invention relates to automation and computing and can be used to highlight features when recognizing speech patterns.

The purpose of the invention is to improve the accuracy of the device.

Figure 1 shows the diagram of the device; in fig. 2 - timing diagrams for the operation of the device.

The device contains the first 1 trigger, the first 2 and the second 3 elements And, the second 4 trigger, the third 5 the fourth 6 and the fifth 7 elements And, the first 8 and second 9 elements OR, the first 10 and second 11 pulse shapers, pulse generator 12, the first 13, the second 14 and the third 15 pulse counters, the third 16, the fourth 17, the fifth 18 and the sixth 19 elements OR, the third 20 trigger the pulse distributor 21, consisting of a pulse counter 22 and a decoder 23. information input 24, input

initial reset 25 and exits 26 and 27.

The imaging unit 10 generates pulses on the leading edge of the input signal, and the imaging unit 11 - on the falling edge of the signal.

The device works as follows.

The pulse received at the input of the initial reset 25 (figa) through the element OR 17, is fed to the reset inputs of the second 4 trigger, pulse counters 15 and 22 and through the elements OR 8 and 9 to the reset inputs of the pulse counters 13 and 14, and through the element OR 18 to the reset input of the third 20 trigger. The outputs of the flip-flops 4, 20, the overflow outputs of the pulse counters 13-15, and the outputs of the pulse counter 22 are set to low voltage levels corresponding to a logic zero level (log.O).

(Ls

The input pulse sequence (Fig. 26) is fed to the counting input of the first 1 flip-flop. The latter, with the arrival of each input pulse, changes its state to the opposite and supplies the enabling signal alternately to the control inputs of the first (fig.2b) or second 14 (fig.2g pulse counters and second inputs of the first 2 or second 3 elements I. the inputs of which are input pulses.

Suppose that the first pulse of the input sequence is wils at the output of the first 2 element I (fig.2d), then the next impulse received at input 24 of the device will pass to the output of the second 3 element i (fig.2e) and switch the first 1 trigger to pass of the next pulse at the output of the first 2 element I. The output pulses of elements AND 2 and 3 alternately through the elements OR 9 and 8 are fed to the reset inputs of the pulse counters 13 and 14, the O levels are set at their outputs. If the control input (pulse counters 13 or 14 level log.1, then A pulsing counter counts the pulses of the oscillator 12, arriving at their clock inputs. The counts of the counters of pulses are 1315 K.

TO,

  L2 of the following

K, K,

selected the same conditions:

Where

h

L (,

to, to.

P / IIK (

less

the period of the pulses of the generator 12;

the maximum possible duration of the time interval between input pulses.

Since the input pulses from the outputs of the And 2 and 3 elements alternately discharge the pulse counters 14 and 13, the latter do not overflow. Therefore, the output of the element OR 16 level log.1 is not formed. At the same time, the input pulses from the outputs of the AND 2 and 3 elements through the OR 19 element arrive at the synchronizing clock of the pulse counter 22 of the pulse distributor 21. The latter changes its state with the arrival of each input pulse. Output counter code

ten

15

6529864

The pulses 22 are fed to the inputs of the decoder 23 of the pulse distributor 21. The pulses at the second and first outputs of the decoder 23 are formed respectively when the first and second pulses arrive at the synchronizing input of the pulse counter 22 with the enable signal at the control input of the decoder 23. Therefore, when the first pulse arrives at an input 24 of the device at the second output of the decoder 23 a pulse is formed (Fig. 2g). which arrives at the input of the trigger setup 20. At the output of the latter, a level is generated - log1 (fig.2i), which is fed to the second input of the fourth 6 element I and the first input of the fifth 7 element I. Since the first output of the decoder 23 the pulse is not generated, then at the output of the second 4 flip-flop the level of the log. O and at the output 27 of the device a pulse is also not generated. At the same time, the pulses of the generator 12 through the element And 7 arrive at the synchronizing input of the pulse counter 15. If during the counting of the pulse counter 15 a second input pulse arrives, then a pulse is formed at the first output of the decoder 23 (Fig. 2.3), which is fixed trigger 4 (Fig. 2k), and accordingly, at the output of the fourth 6th element, a voltage drop is formed.

25

thirty

35

40

45

50

55

nn, arriving at the input of the second 11 pulse generator. When the pulse counter 15 overflows, the output level of log.1 is formed at its output, which through the OR 18 element enters the reset input of the trigger 20. The last output (Fig. 2a) and, correspondingly, at the output of the AND 6 element, the rising edge of the signal, by which the driver 11 forms the output pulse (Fig.2l). The beginning of the first output pulse is fixed relative to the first input pulse of the packet and is equal to KЈ. Upon receipt of subsequent input pulses at the output of the decoder 23, no pulses are generated and, accordingly, there are no pulses at the output 27 of the device. The last pulse of the input sequence switches the trigger 1 and resets one of the counters, pulses 13 or 14. Since there are no subsequent input pulses, the output overflows one of

counters 13 drop log.

or 14 is formed 1. which through the third 16 element OR arrives at the second input of the third 5 element AND, the first input of which receives the rareschag; the signal from the output of the trigger 4. Pulse former 10 on the leading edge of the pulse from the code of the element 5 forms a pulse (Fig 2m ), arriving at the device output 26 and being the pulse of the end of the pack. The beginning of this pulse relative to the last pulse of the packet is fixed and equal to KЈ. At the same time, the impulse from the output of the element OR 16 through the elements OR 17 and 18 is applied to the reset of the flip-flops 4 and 20 and the pulse counters 13 15 and 22, and the levels of the log.O are set at their outputs.

When a noise (single pulse) arrives at the device input, the trigger 1 switches, one of the pulse counters 13 or 14 is reset, a pulse is generated at the output of the OR 19 element, and the second output of the decoder 23 is formed with the log 1 level, which is fixed by the trigger 20 (FIG. .2i). At the output of the trigger 20, a pulse of a duration equal to Cl is formed. Since there are no subsequent input pulses, the output of the trigger 4 is the level of the log. O and the pulse from the output of the trigger 20 does not pass to the input of the driver 11, and one of the pulse counters 13 or 14 overflows and at the output of the OR 16 element a reset pulse of the trigger 4 is generated and 20 and impulse counters 13 - 15 and 22.

Claims (1)

Invention Formula A device for feature selection in pattern recognition, containing the first trigger, the gate input of which is the information input of the device, the first and second elements AND, the first inputs of which are connected to the information input of the device, and the second inputs are connected to the direct and inverse outputs of the first trigger, two element OR. the second trigger, the direct output of which is connected to the first inputs of the third and fourth elements I. dpa of the pulse former, the fifth element AND, characterized by the fact that, in order to increase the accuracy of the device, four counters, a pulse generator, the third, fourth, fifth and sixth elements OR, the third trigger, the decoder, the output of the first element And is connected to the first inputs of the second and sixth elements OR, the output of the second element And is connected to the first M input of the first element OR and to the second input of the sixth element 5 OR, the control inputs of the first l The second counters are connected to the direct and inverse outputs of the first trigger, and the counting inputs are connected to the output of the pulse generator, the first input of the fifth element I is connected to the output of the pulse generator, the second inputs of the fourth and fifth elements And are connected to the direct output of the third trigger, the reset input of which is connected to the output of the fifth OR element. the first input of which is connected to the output of the third counter, the first input of the fourth element OR is the device reset input, 0 the output of the fourth element OR is connected to the second inputs of the first, second and fifth elements OR, to the inputs Resetting the third and fourth counters and to the installation input of the second trigger, the input of which is connected to the first output of the decoder, the second output of which is connected to the third input of the third trigger , the outputs of the third and fourth elements And are connected to the inputs of the first and second pulse formers, the outputs of which are the first and second outputs of the device, the output of the fifth element And is connected to 5 counting inputs of the third counter, the output of the third element OR is connected to the second inputs of the third element AND and the fourth element OR, the outputs of the first and second counters are connected to the inputs of the third element OR, the Reset inputs of the first and second counters are connected to the outputs of the first and second elements OR, the output of the fourth counter is connected to the information input of the decoder, the output of the sixth element OR is connected to the counting input of the fourth counter and to the control input of the decoder. five 0 qw to I