SU1190505A1 - Adaptive pulse duration discriminator - Google Patents

Abstract

ADAPTIVE PULSE SELECTOR WITH DURATION, containing serially connected clock generator, element And pulse counter, to the first group of terminals of which is connected a decoder, the output of which is connected to the second input of element And, sequentially connected pulse generator and delay element, element NOT, the output of which is connected with the input of the pulse counter reset circuit, and the input with the input bus, memory element, code comparison element, the first group of inputs of which is connected to the memory element inputs and analysis of & and connected to the second group of outputs of the pulse counter, the second group - with the outputs of the memory element, and the output - with the input of the pulse former, characterized in that, in order to expand the functionality by restoring the amplitude of the selectable pulses, the first connected analog key is inserted, an analog memory block and a second analog key, an OR element, a second and a third pulse shaper; the input of the first analog key is connected to the input bus and the control input is connected to the output code comparison terminal, the control input of the analog memory block is connected to the output of the OR element, the first and second inputs of which are connected respectively to the outputs of the second and third pulse drivers, the input O) of the second pulse driver, and the input of the third to the control input of the second analog switch and to the output of the delay element. Soo o ate o ate

Description

The invention relates to a pulse technique and can be used to select pulses by duration in a given range of durations while maintaining the amplitude of the pulses in discrete signal processing devices in radio engineering, telemechanics, and measuring equipment when transmitting signals through additive pulse noise.

The purpose of the invention is to expand the functionality by restoring the amplitude of the selectable pulses.

FIG. 1 shows a functional diagram of the proposed adaptive pulse selector for the duration; in fig. 2 - timing diagrams explaining the operation of the selector (a is the signal at the input of the selector; b is the signal at the output of the first pulse generator; c is the signal at the output of the delay device; d is the signal at the output of the decoder; d is the output signal of the third pulse generator; e is the output signal of the second pulse generator; l is the signal at the output of the analog memory device; h is the output signal of the selector).

The adaptive pulse selector contains a clock pulse generator 1, the output of which is connected through the AND 2 element to the counting input of the pulse counter 3, the reset circuit of which is connected to the output of the HE element 4, one output is connected to the inputs of the memory element 5 and the inputs of the code comparison element 6 , the output of the pulses connected via the driver 7 to the input of the delay element 8, while the other outputs of the pulse counter 3 are connected to the inputs of the decoder 9, and the input of the driver 7 of the pulses is connected to the control input of the first analog key 10, the output of which is connected via the analog memory block 11 to the input of the second analog key 12, and the control input of the analog memory block 11 is connected to the output of the OR element 13, the inputs of which are connected to the inputs of the second and third drivers 14 and 15 pulses , wherein the input of the element HE 4 is connected to the input bus 16, the output of the second analog switch 12 is connected with the output bus 17, and the control input of the memory element 5 is connected with a control 18.

Adaptive pulse selector in duration works as follows.

In the initial state (in the absence of input pulses), the output of element 4 does not have the potential of a logical "O", which sets the 3 pulse counter to the zero state and keeps it in this state until the input pulse arrives. Element And 2 open potential logical "1 from the output of the decoder 9 and the clock pulses of the generator 1 is fed to the counting input of the counter 3 pulses. However, they are not counted because the counter 3 pulses is blocked in the reset circuit. At the moment when a negative polarity impulse device (Fig. 2a) arrives at the input of the HE 4 element, a logical level of "1 appears, the blocking is released and the pulse counter 3 starts counting the pulses of the generator 1. Previously, before the input pulses, channel condition analysis. For this, the control input of the memory element 5 is given a signal "ANALYSIS from the control bus 18, on the leading edge of which the memory element 5" is cleared and a code proportional to the minimum lower selection threshold is written to it. At the end of the ANALYSIS signal, memory element 5 is locked and the selector is ready for operation. The following cases are possible.

There are no additive impulse noise in the channel. In this case, there is no need for “rigid selection of pulses in duration and the lower“ threshold can be set to a minimum. Let the duration of the input pulse with amplitude U satisfy the condition T (,, where t and T 1 are the upper and lower thresholds of the selection (Fig. 2a), respectively. In this case, when the input of the counter 3 (l - + - 1) clock pulses (n proportional to THI) the information inputs of the code comparison element 6, connected to the bits of the pulse counter 3, receive a code in its value greater than the code Td at the output () of the comparison element 6, a signal that will start the pulse shaper 7, forming a pulse of the required duration (Fig. 26). At the same time On the leading edge of the output signal of the code comparison element 6, an analog key 10 is opened and an input pulse arrives at the input of the analog memory block 11, the amplitude value of which is memorized (Fig. 2g).

The output impulse of the imager 7 through the delay element 8 with the delay time Tzzz Tb (Fig. 2c) is fed to the control input of the analog switch 12 and opens it. As a result, a voltage is applied to the output of the selector from block 11 of the analog memory and the process of generating the output signal begins. At the end of the pulse at the output of the delay element 8, the analog switch 12 is closed. Thus, at the output of the selector, an output pulse of the required duration is formed, the amplitude of which is equal to the amplitude AND of the input signal (Fig. 2h). At the same time, on the falling edge of the negative voltage drop of the output pulse of the delay element 8, the pulse shaper 15 generates a pulse (Fig. 2e), which through the OR 13 element enters the control input of the analog memory block 11 and zeroes it (Fig. 2g). At the moment of termination of the input pulse at the output of the HE 4 inverter, the potential of the logical

“O, the setting counter of 3 pulses to the zero state, and the selector is ready for processing the next pulse. Let the duration of the input pulse with amplitude t / 2 satisfy the condition (Fig. 2a). In this case, the operation of the selector is similar to that described until the operation of the decoder 9, which is set to the upper threshold TA. By the negative voltage drop at the output of the decoder 9 (Fig. 2d), the pulse shaper 14 generates a pulse (Fig. 2e), which through the OR 13 element enters the analog memory block 11 and zeroes it (Fig. 2g). At the same time, the logic level “O from the output of the decoder 9 enters the second input of the element II 2 and closes it and the pulses from the generator 1 to the input of the counter 3 pulses will not pass. The blocking element And 2 eliminates the likelihood of a false selector triggering when processing pulses whose duration is a multiple of T |. After time Tzad, a delayed pulse of the driver 7 is sent to the control input of the analog switch 12 (Fig. 2c). The key opens, however, the output pulse is not generated, since the voltage supplied to the key input from the analog memory block 11 is zero (Fig. 2h). Upon completion of processing the block of information pulses of the selector by a signal "ANALYSIS arriving at the memory element 5, is transferred to the channel state analysis mode.

In the channel, there is an additive impulse interference with a pulse duration of t = 1 (Fig. 2a). At the time of arrival of a noise pulse at the selector input, the pulse counter 3 starts counting the pulses of the generator 1 in time, i.e., measuring the pulse duration. A code proportional to the duration of the interference pulse is written to the memory element 5. At the end of the "ANALYSIS signal, memory element 5 is blocked, which prevents other codes from being written into it (for example, the information pulse duration code), and the previously recorded interference duration pulse code is used as the lower threshold r 2, the selector switches to input selection mode pulses. In this case, a complex signal containing impulses of interference, information impulses and information impulses, partially suppressed by interference, arrives at its input. If an interference pulse arrives at the input, then there will be no response to it at the output of the selector, since in this case the condition is fulfilled and the signal at the output () of the code comparison element 6 is absent (Fig. 2a). An information pulse arrives at the input, partially suppressed by a noise pulse with amplitude t / h. If at the same time the duration of the impulse balance satisfies the condition (tg-Tn:) Tn2tn: (Fig. 2a), then the output of the code comparison element 6 shows an output signal, and the output pulse of the analyzed amplitude which is equal to the amplitude of the non-depressed part

 input pulse (Fig. 2h). At the end of the processing of information pulses, the selector is again switched to ANALYSIS in the mode of analyzing the channel state, and the code of the threshold Tn2 in the memory element 5

Q is unlocked and the threshold code is set.

Tp

in the channel there is an additive impulse interference with the pulse duration Tlz (not shown in the time diagram). In this case, as in the previous one, as a result of measuring the duration of the interference pulse, memory threshold element 5 sets a threshold code against which the duration of the input pulses will be analyzed (Fig. 2a). Finally, if the interference pulses have a duration, then the threshold Tii4 is set (Fig. 2a), and the selector operates in a "hard selection" mode, in which their duration differences are used to separate information and interfering pulses. Thus, each time before processing information pulses, the value of the lower selection threshold is automatically set depending on the duration of the interference pulses.

The value of the upper threshold TU is fixed at the maximum pulse duration T2, which must be selected. If necessary, TB can also be made variable, similarly to the lower threshold, by inserting an additional memory device and comparison into the selector.

5 codes. The threshold Tni is set taking into account the maximum duration of the noise emissions operating in the communication channel in the absence of additive interference.

FIG. 2

Claims (1)

ADAPTIVE PULSE SELECTOR FOR DURATION, containing a series-connected clock pulse generator, an element And and a pulse counter, to the first group of outputs of which a decoder is connected, the output of which is connected to the second input of the element And, the pulse shaper and the delay element are connected in series, the element is NOT, the output of which is connected with the input of the reset circuit of the pulse counter, and the input with the input bus, a memory element, a code comparison element, the first group of inputs of which is connected to the inputs of the memory element and connected to the second group of outputs of the pulse counter, the second group with the outputs of the memory element, and the output with the input of the pulse shaper, characterized in that, in order to expand the functionality by restoring the amplitude of the selected pulses, the first analog key is connected in series, the analog block memory and the second analog key, the OR element, the second and third pulse shapers, while the input of the first analog key is connected to the input bus, and the control input to the output of the element for comparing codes, the control input of the analog memory block is connected to the output of the OR element, the first and second inputs of which are connected respectively to the outputs of the second and third pulse shapers, the input of the second pulse shaper connected to the output of the decoder, and the input of the third to the control input of the second analog key and to the output of the delay element. FIG. 1