SU790241A1 - Pulse duration selector - Google Patents

Description

(54) SELECTOR OF PULSES OF DURATION

A pulse selector of duration refers to a pulse technique and can be used in computing and measuring devices. A pulse selector is known in duration, comprising a generator, the output of which through a valve is connected to a non-reversible pulse counter, the output of which through a pulse shaper is connected to the first input of a coincidence element j | l. The disadvantage of this selector is the possibility of false triggering at input pulses that are multiples of the duration of selectable pulses. In addition, the pulse at the output of the selector is not equal in duration to the input selectable pulse C2}. The closest in technical essence is a pulse selector in terms of duration, containing a pulse generator, a match element, a pulse counter, a trigger, the output of which is connected to the input of the first match element, and the ORIGZ element. However, a known selector is the selection of pulses, the duration of which is longer than the selection threshold, i.e. One-sided selection, in addition, has low resolution and noise immunity. The purpose of the invention is to increase the reliability of selection and to obtain an output pulse equal in duration to the input pulse. This goal is achieved by the fact that in a pulse selector with duration, containing a pulse generator, an OR element, two AND elements, a trigger, the output of which is connected to the first input of the first element-AND, an M-bit shift register is entered, and the inputs of the OR element are connected to inverse outputs I through K th of the shift register, the forward outputs of which from (K + 1) th to (M – 1) th discharge and inverse output of the M th bit are connected to the inputs of the second element I, one of the inputs of which is connected to the output of the OR element, and the output to the setup input of the trigger Here, the clock input of the shift register is connected to the pulse generator, the information input is connected to the input bus and the input setting to zero the first register bit, and the output is connected to the second input of the first And element, the output is connected to the counting input. rigger and output tire.

The drawing shows a structural electrical circuit of the device.

Pulse selector for long duration contains generator 1 of pulses 2 and 3 AND, trigger 4, input 5, register 6 M-bit, performed, for example, on D-triggers, element 7 OR and output bus 8. The inputs of element 7 OR are connected to inverse outputs with 1, on the K-th level of register 6, defining the upper limit of selection. Direct outputs, from (K + 1) to (M-1) -th bit, determining the minimum duration of the selected pulse, and the inverse output of the M-th region and register b connect 1Y to the inputs of element 2 I, one of the inputs of which connected to the output of element 7 OR, the output of element 2 and connected to the installation input to 1 trigger 4, the direct output of which is connected to the first input of element 3 I. The clock input of register 6 is connected to the output of generator 1, the information input is connected to bus 5 and input set to zero 1 bit register register 6. The output of the register b is connected to the second input of the ementa 3 and the output of which soedine.n to trigger counting input bus 4 and 8.

The device works as follows.

Let us take the state of triggers, in which the direct (high) potential is 1% for direct output, and the state of triggers, on which the (high) potential, on the inverse output, zero, 0.

In the initial state, the generator 1 generates clock pulses having a follow-up period T, which continuously enters the clock input of the register. 6 i Element 2 And is closed by low direct output potentials from (K + 1) -th to (M-1) -th register bit b, and open with high potentials at the inputs connected to the output of element 7 OR and the inverse output of the mth register bit b. Element 3 And is closed on the first input by the low potential of the direct output of the trigger 4 and on the second input by the low potential of the output of the register 6.

The output rectangular positive impulse goes to the bus 5, then with the arrival of the next clock pulse in 1 bit de register b

With the coming of the next one

of the pulse, the unit will be recorded in T and P bits, etc. After the pulse has finished, the low input level of the T-th bit of the register b will return to the initial zero state. Thus, in register b: the code corresponding to the duration of the input pulse is written.

The clock pulses of the generator 1 will advance the recorded code according to the register 6. After (M-1) -th clock from the moment of arrival of the input pulse in the bits of the register b with (K + 1) -th to (m-lj-th, determining the minimum The unit pulse will be recorded and the part of register b from 1 to K (or at least one bit) will be in the zero state. At the same time, at the output of element 7 OR, at the direct outputs of bits c (K +1) -th of (M-1) -y and on the inverse output of the M-th bit of register b high potential in tc, as a result of which element 2I will open. Output signal element 2 and sets the trigger 4 to one, and element 3 is opened at the first input. And a high potential of the direct output of the trigger 4 opens. With the arrival of the next clock pulse, 1 is written to the Mth bit of the register b and at its output A high potential appears which, through the open element 3, arrives at the output of the device and forms the leading edge of the output pulse.

The code corresponding to the duration of the input pulse is shifted in the register by pulses of the clock frequency. In this case, the M-th register bit remains in a single state, as a result of which the output of element 3 is formed at the output of element 3 And. pulse, equal to the duration of vhbdnogo. After the M-th register register bit returns to the initial (zero) state, element 3 I is closed by a low level of its direct output. Element 3 output trigger 4 returns to its original state.

Thus, if the duration of the input pulse T is in the precursor (M-l-K),

affairs t tz

t, T (M-1), T is the period of clock pulses, M is the number of bits of register b, K is the number of bits of register 6 defining the upper selection limit D (), then the input pulse will pass to the output of the device.

If the duration of the input impulses is less than the time t or more than t, then the element 2 And remains closed at least one of the inputs and such pulses do not pass at the output of the selector.

If the device receives interference pulses, the duration of which is in the specified selection range, i.e. consisting, for example, of M-2 short impulses of interference coinciding with clock frequency pulses, then the first clock pulse in I de de register b will be fixed 1. However,

Since the information input of register 6 is connected to the input of a zero-setting I of the first, then after the end of the interference of the first input pulse, the first trigger of register b will return to the initial (zero) state. With the arrival of the second input pulse, the first frequency in register I of register b will again be fixed 1, but the register register b will still be in the initial (zero) state. After the termination of the second pulse of interference, the first trigger of register B will return to the initial state, hence, none of the pulses will be returned. will pass to the exit of the device.

Thus, the design features of this technical solution make it possible to increase the reliability of selection, pulses whose duration does not lie in the selectable range do not pass to the output of the selector, and also receive a pulse at the output whose duration is wound to the duration of the input selectable pulse.

Claims (3)

1. USSR author's certificate number 356770, cl. H.03K 5/18, 1971. 2. USSR author's certificate №536594, cl. H 03 K 5/18, 1975. 3. USSR author's certificate number 558394, cl. H 03 K 5/18, 1976.