SU1023646A1 - Threshold device - Google Patents

Description

The invention relates to a pulse technique and can be used as a pulse shaper on a mixture, signal c. noise.

Threshold devices are known, which contain a lower level threshold element, a threshold element, an upper level element, AND logic elements and logic elements OR D The disadvantage of such devices is low noise immunity.

The most obvious technical essence of this invention is a threshold device containing a threshold element of the lower level connected to the first input of an NAND logic element, and an input to the bus of input signals and the input of the threshold element of the upper level, the output of which is connected through the delay element to the second input. Logic element 2.

. However, in such devices, a false positive from interference occurs in the form of a sequence of accidental pulses in amplitude that exceed threshold thresholds.

The purpose of the invention is to improve the noise immunity of the device.

To achieve the goal, a threshold device containing a lower-level threshold element, an output connected to the first input of an AND-HB logic element, and an input to an input signal bus and an input of the upper-level threshold element whose output is connected via a delay element to the second input of the logical element I-HB, entered the logical element OR, the trigger, the first input of which is connected to the output of the logic element I-HB, the output - to the output bus, and the second input - to the output of the logical element OR, the first and second hots which It is equal to the first and second inputs of the NAND logic element, and a circuit of additional delay elements connected in series, connected to the output of the delay element, while the outputs of each additional delay element are connected respectively to the inputs of the AND AND HB OR logic elements.

FIG. 1 shows a functional scheme of the threshold device; in fig. 2 is a timing diagram of its operation. The device includes a threshold element 1 of the lower level and a threshold element 2 of the upper level, the inputs of which are combined and connected to the input bus of the device. The output of the threshold element 1 of the lower level is connected to the first input of the logical element I-HB 3 and the first input of the logic element OR 4. The output of the threshold element 2 of the upper level

connected to the input of series-connected delay elements 5, which can be performed, for example, on commercially available delay lines or according to the V) -shift shift register, the clock input of which receives the frequency from the pulse generator. The output of each delay element 5 is connected to the corresponding inputs of logic elements I-Hb 3 and OR 4. The output of logic element I-HB 3 is connected to the first, and the output of the logic element OR 4 is connected to the second inputs of trigger 6, the output of which is connected to the output bus devices

Threshold elements can be performed, for example, serially from prepared voltage comparators, the first input of which receives an input signal, and the second threshold voltage of the lower level C Y p n) or upper level (Uoope according to the purpose of the element).

The choice of the delay time on the delay element 5 and the total delay time are determined by the duration of the interference. For example, it is possible to evenly distribute the delay between VI sequentially connected delay elements 5. . .

Mr. - .vM gobel m,.

in this case, the delay on the delay element 5 is determined by the minimum duration of the interference (in accordance with the Kotelnikov

S BURDLEH VYJN

-y

ZOBA 1..

The total delay time of the serially connected delay elements 5 is determined by the maximum duration of the impulse output.

/ tnpiwei wK .. Moreover, the duration is gzzo (sum should always be less than the duration of the pulse of the useful signal.

Interference in the form of a sequence of random pulses, the duration and interval of which is less than the Total Delayed Time of the SUM O is greater than t, and the amplitude exceeds the difference in the threshold voltages and pores in and Unoph / are absent at the output of the threshold device.

The trigger b can be performed, for example, on the logical elements AND-HB according to the RS-flip-flop scheme.

The device works as follows.

In the initial state, in the absence of an input signal, the threshold elements 1 and 2 do not work. From the output of threshold element 2 of the upper level, through the delay elements 5 and from the output of threshold element 1 of the lower level Jia, all inputs of AND-NOT 3 and OR 4 logic elements arrive at levels O and set the output of the logical element OR 4 to level O, and the output of the logic element NAND 3 level 1, which set the level O at the output of the threshold device. When a threshold device arrives at the input in the form of a single positive pulse, which exceeds the lower and upper threshold levels, and whose duration does not exceed Tzsk, / threshold elements 1 and 2 are triggered. From the output of the lower threshold element 1 to the inputs of logic elements AND-NOT 3 and OR 4 and from the output of the Threshold Element 2 of the upper level to the input of the series-connected delay elements 5 are at the levels, 1. however, at all inputs of the logical elements AND-NOT 3 and OR 6 6 times one level 1 can not be connected, because the length of ejibHocTb positive interference is less than q SUA Therefore, at the outputs of the logical elements AND-HE 3 and OR 4. level 1 is set, and at the output of the threshold device, level O will remain. Thus, at the output of the noporof device, interference in the form of single positive pulses is excluded, in amplitude exceeding the lower and upper threshold levels, and in duration not exceeding aux, see Ud (see Fig. 2 ). When a device arrives at the input threshold of a noise in the form of a sequence of random positive pulses whose amplitude exceeds the lower and upper threshold levels, and the duration and interval of a trace smaller than 1–2 D, the threshold elements 1 and 2 are triggered, From the output of the threshold, 1Che element 2 of the upper level through the elements of delay. 5 and from the output of the threshold element 1 of the lower level to the inputs of the logic elements Y – HY 3. and OR 4 noise interference is coming. However, at the inputs of AND-NOT 3 and OR 4 logic elements, the IJ levels corresponding to their positive ults can not be present at the same time, since at any time interval of 1 Gs5 there will be at least one interval between pulses greater than Tjod E in which save the level O. Therefore, the outputs of the logical elements AND-NOT 3 and OR 4 will remain levels, and the output of the threshold device - level O, Thus, at the input of the threshold device exclude interference in the form of a sequence with {1 positive pulse owls, the amplitude of which leads to lower and upper threshold levels, and the duration and duration of the following interval is less Thzas SUM r but more (see Fig. 2 J.) When a threshold device arrives at an input signal that exceeds the lower and upper threshold levels, threshold elements 1 and 2 and through the exit time of the upper threshold element 2 through the delay elements 5 and from the output of the lower threshold element 1 all levels I and NO 3 and OR 4 arrive at level 1. Therefore, at the output of the logic element OR 4 will remain level 1, and the output of the logical element AND-NOT 3 will set the level that will form the output of the threshold device level 1. Thus, in the threshold device the formation of the leading edge of the output pulse occurs (see FIG. 2). When a threshold device arrives at the input Interference in the form of a single negative pulse, the magnitude of which exceeds the upper and lower threshold levels, the reverse operation of threshold elements 1 and 2 occurs. From the output of upper threshold element 2 through delay elements 5 and from the output of threshold element 1 lower Levels at the inputs of the logical elements AND-NOT 3 and OR 4 receive level 1. However, at the same time on dah logical elements AND-NOT 3 and OR 4 levels O can not be present, because the duration of the negative interference There is less tr adtvGA Therefore, the outputs of the logical elements AND-NOT 3, OR 4 and the output of the threshold device contain levels 1. Thus, the output of the threshold device eliminates interference in the form of a single negative pulse, the value of which exceeds the upper and lower threshold levels (see .2). When a threshold device receives noise as a sequence of random negative impulses that exceed the upper and lower threshold levels, and the duration and interval of the sequence is less than HzadC.VM ° greater than e, the reverse elements 1 and 2 are activated. From the output of the threshold element 2 of the upper level through the elements of the deduction 5 and from the output of the threshold element 1 of the lower level to the inputs of the logical elements AND-NOT 3 and OR 4 the levels O are received, corresponding to the corresponding negative impulse noise.

However, at all inputs of the logical elements AND-NOT 3 and OR 4, the levels O cannot be present at the same time, since on. Any time interval eHr3c with cvM will have at least one time interval between negative pulses, which will save level 1. Therefore, the outputs of the AND-NE 3 logic gates, OR 4 and the output device of the threshold device will have levels 1.

Thus, in the threshold device, interference in the form of a sequence of random negative pulses is eliminated, the magnitude of which s exceeds the upper and lower threshold ypoB-vS, and the duration and interval of the sequence are less than T5O (SUM / o more

Bad-J If a threshold device receives a signal, the value of which does not exceed the lower and upper threshold levels, the reverse action of the threshold elements 1 and 2 occurs and after the time of the SUM output of the threshold element 2

through the delay elements 5 and from the output of the threshold element 1 of the lower level all the inputs of the AND-HE 3 and OR 4 logic elements arrive at the O levels. Therefore, the output of the IS-3 logic element will remain at the level, and the output of the WL 4 logical element will set the level O, which will form at the output of the threshold device level O.

Thus, the rear edge of the output pulse is formed in the threshold device.

As a result, the proposed device eliminates false positives from interference in the form of single positive and negative pulses, the magnitude of which exceeds the upper and lower threshold levels, as in the known device, and also in the form of a sequence of random negative and positive pulses, duration and interval. which is less than T su, but more

Out

U

Claims (1)

(54) (57) A THRESHOLD device containing a threshold element of a lower level, connected to the first input of an AND-NOT logic element by an output, and an input to a bus of input signals and an input of a threshold upper level element, the output of which is connected through a delay element to the second input of a logical AND-NOT element, characterized in that, in order to increase noise immunity, an OR logic element is introduced into it, a trigger, the first input of which is connected to the output of the AND-NOT logical element, the output - to the output bus, and the second input - to the output of the logical OR element, the first and second input of which is connected to the first and second inputs of the AND gate, and the circuit of additional delay elements connected in series, connected to the output of the delay element, while the outputs of each additional delay element are connected respectively to the inputs of logic elements - | * Comrade NAND and OR. l / j