RU1829106C - Discriminator of zero beats - Google Patents

Abstract

Usage: impulse technology, discrete automation systems. The inventive discriminator of zero beats contains RS-triggers 1, 2, elements AND 3,4,7 and blocks 5 and b of the selection of the leading edge of the reference and input pulse sequences, each of which is made in the form of element And and additional elements And -NOT. The device achieves an extension of the frequency range of the pulse sequences. 4 ill.

Description

The invention relates to a pulse technique and can be used in discrete automation systems to logically discriminate between two alternating pulse sequences.

An object of the invention is to extend the frequency range of pulse sequences.

In FIG. 1 is a circuit diagram of a zero beat discriminator; figure 2 and 3 - time diagrams of his work; Fig. 4 is a circuit diagram of a pulse edge leading edge allocation unit.

The zero-beat discriminator contains: RS-Tpnrrep1. additional RS-trigger 2, the first AND-NOT 3 element, the second AND-NOT 4 element, block 5 for selecting the leading edge of the reference pulse sequence, the block for selecting 6 the leading edge of the input pulse sequence, and the third AND-NOT 7. element for selecting the front the front of the pulse sequence consists of an AND element

8, the first, second and third additional elements AND NOT 9, 10 and 11..

The device operates as follows,

Consider the case when fi h.

The inputs of the first and second shapers respectively receive pulse sequences fi and fz (figa and b). At the first outputs of blocks 5 and 6, short impulses of positive polarity appear corresponding to the leading edges of the input pulses (Figs. 2c and d). At the second outputs of the formers, the same negative polarity pulses are applied to the S- and R-inputs of the first RS-flip-flop 1. At the direct and inverse outputs of which signals are generated (Fig. 2g, h). Pulses from the first outputs of the first and second blocks 5 and 6, and the direct and inverse outputs of the first RS-trigger 1 are received respectively at the first and second inputs of the first and second elements NAND 3 and 4 at the outputs of which signals are generated (Fig.2i ,to). Moreover, at the output of the second AND-NOT 4 element, in this case, there are no pulses, and

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pulses from the output of the first element 21 / 1- NOT 3 switch the additional RS-- trigger 2 to the single state, which indicates the sign of the difference, i.e. fi h. Pulses of difference frequency from the output of the first AND-NOT 3 element are passed to the output of the third AND-NOT 7 element. Thus, a pulse sequence is generated at the first output of the device with a frequency f t-fa, and a unit level at the second output indicates such that fi - f2 0.

With a different ratio of the frequencies of the input pulse sequences, when iY f2, the pulses of the difference frequency appear at the first output and the second output sets the zero level, indicating the sign of the difference ft-

Consider the case of operation of the device with equal frequencies of the input pulse sequences. At the first and second outputs of blocks 5 and 6, short pulses appear corresponding to the leading edges of the input pulses and of the opposite polarity (Figs. 3a, b, c, d, e, e).

Under the influence of impulses ;; arriving at the S- and R-inputs (Fig. 3c), the RS-flip-flop 1 is switched and pulses appear on its direct and inverse outputs (Fig. 3c). However, they are delayed with respect to the pulses at the first outputs of blocks 5 and 6 for the time the trigger is switched, therefore, the inputs of the first and second elements are NOT received at different times and will not pass at their output (Fig. Z.k.) pulses and at the first output of the device, the additional RS-trigger 2 remains in the previous state (Fig. Zl.m).

Thus, when the frequencies of the input pulse sequences are equal, there are no pulses at the output of the discriminator.

SUMMARY OF THE INVENTION A zero beat discriminator comprising a series-connected front-edge selection unit of a reference pulse sequence and a first AND-HE element, series-connected front-edge allocation block of an input pulse sequence and a second AND-NOT element, RS-flip-flop, direct and inverse outputs which are connected to other inputs of the first and second elements AND NOT, respectively, as well as the third element AND NOT, whose inputs are connected to the outputs of the first and second elements. INE. It is due to the fact that, in order to expand the frequency range of pulse sequences, an additional RS-trigger is introduced into it, the S- and R-inputs of which are connected respectively to the outputs

the first and second AND-NOT elements, and each block of the leading edge selection of the pulse sequence is made in the form of an AND element and the first, second and third AND-NOT elements connected in series, the other inputs of the AND element and the second additional AND-NOT element being input the corresponding block of the selection of the leading edge of the pulse sequence, the other input of the first additional element AND is NOT connected to the output of the element AND, the other input of the third additional element is NOT connected to the output of the second For more NAND, and second outputs

The third additional AND elements are, respectively, the output and inverse output of the corresponding pulse front leading edge allocation unit, and the S and R inputs of the RS trigger are connected to the inverse outputs of the corresponding leading edge allocation blocking pulses.

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