SU1758848A1 - Random pulse stochastic converter - Google Patents

Abstract

Usage: in the pulse technique for converting the ratio of the average values of two alternating sequences of random pulses into a number. The stochastic random pulse converter contains 1 clock pulse generator, AND 2 element. Delay element 3, frequency divider 4, 5 pulse counter, register 7, controlled frequency divider, functional converter 9, reversible counter 10, input buses 11, 12. 1 il.

Description

The invention relates to a pulse technique and serves to convert the ratio of the average values of two alternating sequences of random pulses into a number.

The purpose of the invention is to improve the accuracy of the conversion.

The drawing shows a structural electrical circuit of a stochastic random pulse converter.

The stochastic converter of random pulses contains a generator of 1 clock pulses, an element 2, a delay element 3, first and second dividers 4 and 5 frequencies, a counter 6 pulses, a register 7, an adjustable frequency divider 8, a functional converter 9, a reversible counter 10, the first and second input bus 11 and 12.

The output of the generator 1 clock pulses connected to the second input element And 2 and the synchronization input of the counter 6 pulses. The first input element And 2 is connected to the first input bus 11. The output element And 2 through the first frequency divider 4 is connected to the synchronization input of the controlled frequency divider 8. The input of the delay element 3 is connected to the input of the second frequency divider 5, to the synchronization input and to the second input bus 12. The output of the delay element 3 is connected to the installation input of the pulse counter 6, the outputs of which are connected to the inputs of the register, the outputs of which are connected to the inputs of the controlled divider 8 frequencies. The output of the second frequency divider 5 is connected to the synchronization input of the functional converter 9, whose inputs are connected to the outputs of the reversible counter 10. The output of the controlled frequency divider 8 is connected to the first input of the reversible counter 10, the second input of which is connected to the output of the functional converter 9.

The stochastic transducer of random pulses works as follows.

Let the first input bus 11 receive a random sequence of positive pulses of Hz duration, and the second input bus 12 - negative pulses of duration n, where I with А 0,1,2,3 .... i.e. the input signals are random processes {pi}, satisfying the stationarity condition at a given averaging interval.

Let the negative impulse of duration T2 be the first to enter the device. In this case, blocking is removed from the pulse counter 6, which, during the pulse t2i, counts the pulses arriving at a frequency f0 to its synchronization input from the output of the generator 1 clock pulses. During time T2, the counter 6 registers f0 b pulses. The positive back edge of the pulse G21, the number from the output of the counter of 6 pulses, is entered into the register 7, after which the counter of 6 pulses is turned back by the delayed delay element 3 by a positive level and is blocked until the next TZ pulse arrives.

When the 1 st Hz positive pulse arrives at the first input of the element I 2, the pulses of frequency f 0 from the output of the 1 clock pulse generator appear at the output of the latter. As a result, a pulse sequence with frequency f0 / ki is formed at the output of divider 4 frequency over time Hz. where ki is the frequency division factor of the 4 frequency divider, which is fed to the synchronization input of the controlled frequency divider 8, the division factor of which is controlled by a binary number (proportional to T2} from the register 7 outputs. During the pulse Hz, the reversing counter 10 input will be output from controlled frequency divider 8 on average

... l. , ... pulses, where n and r2 kifoTiz kir2

average values of u and tg. At the moment when the pulse shch i is at the first input of the element And 2, the potential of logical O appears and the flow of pulses to the input of the frequency divider 4 stops.

Thus, when a series of pulses of Hz arrives at the first input bus 11 of the device, the pulse flow with the average frequency arrives at the summing input of the reversing counter 10

A, -ЈЈ-, kiT2

where fc const is the pulse frequency T, T2.

Under the action of pulses Tg, coming through a frequency divider 5 to the clock input of the functional converter 9, a pulse flow with an average frequency is formed at the output of the latter.

, k22m

where K2 is the frequency division factor of the divider 5 frequency; N (i) - the contents of the reversible counter 10; m is the number of its output bits.

The change in the content of the reversible counter 10 over time t is determined from the expression

(t) (Ai-A2) dt

Solving this equation with the initial condition N (0) No, we find that N (t)

Co-R- 1 -exp (-D-)) + M0ext (-4-)

Tg.-fL

m k2. 2m

where k0 2

constant naskl fe

the change in the inertia of the stochastic transducer of random pulses.

In steady state mode

N (co) ko

.EL

T2

Since it is determined only by the values of K2, m and fc (constants), the proposed device converts the ratio of average values of time intervals with constant inertness, independent of the parameters 1 and G2 of the input pulse streams.

Claims (1)

Invention Formula A stochastic random pulse converter containing serially connected first input bus, first frequency divider, second input bus, second frequency divider, series-connected reversing counter and functional converter, clock generator, the output of which is connected to the second input of the first And element, characterized in that . in order to improve the accuracy of the conversion, serially connected delay element, pulse counter, register and controlled frequency divider, the output of which is connected to the first input of the reversible counter, the second input of which is connected to the output of the functional the converter, whose synchronization input is connected to the output of the second frequency divider, whose input is connected to the register synchronization input and to the input of the delay element, the output of the clock pulse generator is connected to the synchronization input of the pulse counter, the output of the first frequency divider is connected to the synchronization input of the controlled frequency divider.