SU1275746A1 - Device for synchronizing pulses - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices for converting asynchronous pulse signals to signals synchronized in phase and phase with the synchronization signals. The purpose of the invention is the extension of the functionality achieved by forming shifted bursts of synchronizing series of pulses with simultaneous control of the number of output signals. For this, an additional clock bus 13, an initial installation bus 14, an additional output bus 12, an additional inverter 2, a third AND-HE element 5 and an AND 6 element are introduced into the device. In addition, the device contains an inverter 1, AND-HE elements 3 and 4 , D-triggers 7 I and 8, control bus 9, 10 clock pulse bus, output bus 11. (L) The number of pulses in the output series is controlled by varying the duration of the control signal, 3 nl.

Description

The invention relates to a pulse technique and can be used in automation and computing devices for converting asynchronous pulse signals into signals synchronized in duration and phase with the synchronization signals.

The purpose of the invention is the extension of functional capabilities by forming shifted bursts of synchronizing pulse series with simultaneous control of the number of output pulses with the duration of the control signal.

FIG. 1 shows the electrical functional scheme of the device ;; on e1) ig. 2 and 3 are time diagrams that show his work.

The device for synchronizing pulses contains Two inverters 1 and 2, three AND-NE elements 3-5, element 6, two triggers 7 and 8 B-type of the input of the first of which is connected to control bus 9, D-input with bus logical zero, my output is with the first input of the first IS-NE 3 element and with the D input of the second flip-flop 8. The second input of the IS-NE 3 element is connected via an inverter to the 10 clock pulse bus, which is connected to the first input of the second IS-NE 4 element, the Second input element AND - NOT 4 is connected to the direct output of the second trigger B and to the first input of the third element AND -NOT 5, output - with output bus 11 and with the first input of the element Ib, the second input of which is connected to the additional output bus 12 and the output of the third AND-NAND 5. Second input of the latter is connected to the additional bus 13 clock pulses and through an additional inverter 2 with the third input of the first element AND-HE 3, the output of which is connected to the S-input of the second trigger 8, the R inputs of the first 7 and second 8 triggers are connected to the initial state setting bus 14, and their C-inputs are connected to the RED element And 6.

The device works as follows.

In the initial state, the triggers 7 and 8 are in the zero state (FIG. 2g). A low potential from the direct output of tri-gera 7 closes the AND-HE 3 element (FIG.). Low

potential with a single exit trigger 8 closes. AND-HE elements 4 and 5 (Fig. 2 U, k), in which the high potential of the outputs passes through the element 6 on the C inputs of the triggers 7 and 8, have no effect on them. On bus 10, there are pulses of the clock frequency (Fig. 28), on bus 13 - additional clock frequency pulses (Fig. 2 b), at the outputs of elements 1 and 2 - pulses inverse to clock pulses (Fig. 2 3, e) the pulses of the first and second clock frequencies are ½ periods. The pulse duration is 1/4 period.

When a pulse of zero pulse (fig. 2 o.) Of zero polarity (control signal) arrives from bus 9 to trigger input (trigger signal), trigger 7 is set to one state and opens AND-NOT element 3 at the second input. At the time of the absence of clock pulses on the tires 10 and 13 ng1 output of element 3 appears: a low level, which, arriving at the S-code of trigger 8, sets it to one state. The unit level of the direct output of the trigger 8 permits the clock and additional clock pulses to pass through the EIA 4 and 5 elements on the buses 11 and 12 (Fig. 2c, k). If the control signal is received at the time of the pulse of the clock frequency, then the first pulse will be transmitted to the output bus 12 a pulse of additional clock frequency, and vice versa, if the control signal is received at the time of the pulse of the additional clock frequency, then the first pulse will be allocated to the output bus 12 clock frequency. In this case, the pulse, the additional, clock frequency, is first passed through the ETH 5 element to the bus 12.

Claims (1)

At the same time, the first output pulse of the bus 12 passes through the element 6 and enters the C inputs of the triggers 7 and 8. If the device operates in the single pulse frequency selection mode, the control signal after the trigger 7 is set to one is removed. Consequently, after the issuance of the first pulse of the AND 6 trigger 7 returns to the initial state, as a result, the low level 3 of the direct output of the trigger 7 blocks the AND-NOT element 3 and is set at the D input of the trigger 8. After 1/4 of the period after issuing the first impulse of the second clock frequency, the first impulse of the clock frequency from the bus 10 passes through the IS-NOT 4 element to the bus 11. When the first impulse of the bus 1 is output, output 6 of the element 6 produces a difference from a low level to a high level where the second trigger 8 goes back to ex. This state is blocked by the elements AND-HE 4 and 5. Therefore, in the single pulse mode on the output buses 11 and 12, one single pulse of the corresponding clock frequencies is allocated. The order of their value depends on the moment of arrival of the control signal. By changing the duration of the control signal, it is possible to control the number of pulses in the output series (Fig. 3). If there is a control signal on the bus (Fig. 3a), the trigger 7 is held in one state (Fig. 3g) and each You, divided by the output pulse at the C input, confirms the single state of the trigger 8 (FIG. 3). Only after the control signal is cleared and the pulse output is completed, the device returns to its initial state. The invention The device for synchronizing pulses, containing two trigger H l I ,, ds, t 1 G L- IIf .JL II I in J L JLJji i l  l nn uTT4JTTiJTTiJTTlj I III .. ..1II1 I 464 D-type, the direct output of the first of which is connected to the D-input of the second trigger and to the first input of the first NAND element, the second input of which through the inverter is connected to the clock pulse bus, which is connected to the first input of the second NAND element, the second input of which is connected to the direct output of the second trigger, the output to the output bus, control panel, characterized in that, in order to extend the functionality by forming shifted packets of synchronizing series of pulses with simultaneous control of the output impulses of control signal duration, an additional clock pulse bus, an initial setup bus, an additional output bus, an additional inverter, a third AND-NOT element and an AND element, whose first input is connected to the output of the second AND-NOT element, the second input of which is entered into it. connected to the output of the third element IS-NOT and with an additional output bus, output to the C-inputs of the first and second triggers, S-input of the first trigger connected to the control bus, D-input with zero bus, and the R-inputs of the first and second trigger moat coupled to bus initial setup, a direct output of the second of which is connected to a first input of the third AND-NO element, the second input of which is connected via a further inverter to the third input of the first AND-NO element and to the additional bus clock. srm.g f P n P brMniljbUJl-ilrvLi I I I I 1 I I I. G-1, 1 I 1 1 I / iiiimmlr r Uilriljui.