SU439911A1 - Pulse synchronization device - Google Patents

Description

(54) DEVICE FOR SYNCHRONIZATION OF PULSES

2, the output of which is connected to the third input of the circuit “AND 5, the second input of the circuit“ AND 6 n with the input of the circuit “NOT .3. The output of the circuit 3 is connected to the second input of the circuit “AND 7, the third input of which is connected to the single output of the trigger 8, and the output of the circuit“ AND 7 - to the zero input of the trigger / and the output bus 11 of the device.

The device works as follows.

An input asynchronous pulse (see Fig. 2, a) arriving at the device bus 9 sets the trigger 1 to the state "1. At the same time, from the unit output of the trigger / to the first input of the circuit “AND 5, the permissive signal is removed, and from the zero output to the first input of the circuit“ And 6 - the inhibit signal. For a period of time equal to the duration of the input pulse, the second input of the "P1 5" circuit is given a inhibitory signal from the output of the NOT 4 circuit. After this time has passed, the signal at the second input of the "And 5" circuit also becomes enabling. In the pauses between the synchronizing pulses arriving at the device bus 10 (see Fig. 2, b), the output of the circuit 2 does NOT form signals (see Fig. 2, c) arriving at the third input of the circuit "And 5 and the second input Circuit P 6. When the permissive signals are combined, the first, second, and third inputs of circuit 5 produce a pulse at the output of this circuit, which sets the trigger S to the state "1. From the single output of the trigger 8 to the third input of the “I 7” circuit, and the enabling signal arrives. At the output of circuit 7, a signal is generated that, at its remaining inputs, a synchronization signal from bus 10 and a synchronization signal after a double inversion from the output of the circuit NOT O (see Fig. 2, d). The next snubber pulse passes to the bus // device (see Fig. 2, e and the zero input of trigger 1. Due to a delay in the circuit "NOT 2 Sig. At its output (see Fig. 2, c) it remains resolving for a certain time interval Dt, when the next enable signal is indicated on the bus 10 of the device (see

FIG. 2, b). Since, besides the input clock signal. The second input of the circuit "AND 7" and the signal from the output of the circuit "NOT 3 (see Fig. 2, d), the resulting permissive signal acting on the first and second inputs of the circuit 7 (see Fig. 2, e}) does not overlap in time with the enabling signal generated at the output of the circuit "NOT 2 (see Fig. 2, 0). After setting the trigger I to the state

An “O” input to the circuit “AND 6” is supplied with an enable signal from the zero output of this flip-flop. The next permitting signal from the output of the circuit "NOT 2 passes in the pause between the synchronizing pulses through the circuit in to the zero input of the trigger 8 and sets it to the state" O. The circuit diagram returns to its original state.

Subject invention

20

A device for synchronizing pulses, containing an input trigger, a sync pulse bus, an asynchronous pulse bus, three AND diagrams and two NOT circuits, the bus

sync pulses connected to one of the inputs of the third circuit “And through two inverters connected in series to another input of the third circuit“ And, and one of the outputs of the input trigger is connected to one of the inputs

The first circuit "And, characterized in that, in order to increase reliability, a trigger and a circuit" are NOT introduced into it, the bus of asynchronous pulses is connected to the input of the input circuit "NOT, the output of which is connected to

the first input of the trigger and the second input of the first circuit “And, the output of which is connected to the first input of the input trigger, the output of which through the third circuit“ And is connected to the second input of the input trigger, the second output of the input trigger through the second circuit “And to the second input of the entered trigger , and the output of the first inverter is connected to the third input of the first circuit “And and the second input of the second circuit“ I.

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