SU606200A1 - Pulse synchronization device - Google Patents

Description

(54) DEVICE FOR SYNCHRONIZATION OF PULSES

The second input of which is connected to the second output of the trigger input, and the output is connected to the first input of the output trigger, the second input of which is connected to the output of the first element I, the output of the output trigger connected to the first input of the second element I, the second input of which is connected to the input of the second element NOT , the output of the third element And is connected to the third input of the input trigger, the third input of the second element And is connected to the second input of the output trigger, the third input of which is connected to the third input of the third and to the output of the second th element I.

The drawing shows a functional electrical circuit of a device for synchronizing pulses.

The device contains an input trigger 1, elements NOT 2, 3, elements AND 4-6, output trigger 7.: The device works as follows.

When the input asynchronous pulse arrives on the bus 8, the trigger 1 is set to the state "1. In this case, from its unit input to the second input of the And 4 element, the enabling signal arrives, and from the zero output to the first input of the And 5 element - prohibiting: signal. In the time interval equal to the duration of the input asynchronous pulse, the first input of the element And 4 is given a inhibitory signal from the element NOT 3. Until this time, the signal at the first input of the element And 4 becomes also enabling. In the pauses between the synchronizing pulses arriving at the device input 9, at the output of the element NOT 2, the permitting signals are generated, which arrive at the third input of the element 4 and the second input of the element 5. When the enabling signals coincide at the first, second and third inputs of the element 4 at its output, a pulse is formed, which sets the state of "I trigger 7 and keeps element 6 in the closed state." From the single output of this trigger, the first input of the element AND 6 receives an enable signal.

At the output of element And 6, a signal is formed when it appears at its second input-sync pulse from bus 9. The signal from element And 6 enters output 10 of the device, at zero input trigger 1, at the third input of element 5 and at the additional single trigger input 7. After trigger 1 is set to the state "O", the enable signal from the zero output of this trigger is supplied to the first input of the element 5. The next signal from the NOT 2 element goes in the pause between the sync pulses through the AND 5 element to the zero input of the trigger 7 and sets it to the “O” state. In addition, the same signal arrives at the additional zero input of trigger 1 and confirms its state.

If the delay of the signal on the element HE 2 leads to the fact that the signal at its output for a certain period of time D remains resolving. After the next sync pulse has already arrived on device 9, the outputs of the elements 4, 5 can form interference signals. Interference signal

on the output of the AND 4 element can be formed when the coincidence of the rise time of the leading edge of the sync pulse arriving on the bus 9 and the falling time of the falling edge of the input asynchronous pulse at the first input 5 of the And 4 element coincides.

If the interfering signal at the output of the AND 4 element leads to the transition of the trigger 7 into the “b” state, then the clock pulse arriving on the bus 9 passes to the output of the And 6 element and leads to the confirmation of the state of the “1 trigger 7.

This prevents the trigger 7 from returning to the state "O if the duration signal is insufficient for reliable holding in the state" 1 trigger 7. In addition, 5 the signal from AND 6 eliminates the formation of an interference signal at the output of the AND 5 element, which can formed if the delay time of the signal element NOT 2 exceeds the response time of the element AND 4, three 7, element 6 and trip-1. Thus, it is not allowed to prematurely set to "On the trigger 7, and therefore the formation of the output 10 is excluded interference devices instead of the wanted signal. If the time of decay of the sync pulse arriving on the device bar 9 and the time of the falling edge of the asynchronous signal at the first input of the AND 4 element at the output of this element coincide, an interference signal may appear. This signal can lead to premature installation in the state of "1 flip-flop 7 until the final fall of the trailing edge of the clock on the bus 9. This is possible if the delay time of a signal with an element of NOT 2 n element I 4 is significantly less than the droop of the trailing edge of the sync pulse on the bus 9 and the asynchronous signal at the first input of EtoTement I 4.

The formation of an interference signal at the output 10 of the device is eliminated by introducing a connection from the output of the element AND 4 to the third input of the element 6 because the signal at the output of the element 4 for the element b b is prohibitive. The considered situation takes place if the time delay of a signal by an element is substantially less than the time of a fall or rise of a signal at the element output, which is quite possible for elements with direct connections, for example, for integrated circuits.

The elimination of the effect of a transient on bus 8 after the falling edge of the input asynchronous 1 ×) pulse and, for example, due to the transition process in the communication line connected to bus 8, is provided by introducing an additional connection for the output of the And 5 element with an additional zero trigger input 1. The introduction of this link allows you to eliminate the influence of spurious pulses arriving on a single trigger input 1 after the moment the trailing edge of the input asynchronous pulse ends for a guaranteed period of time equal to about the period of clock pulses. Due to the fact that in the initial state, the additional zero input of the trigger 1

signals are received in the pause between the sync pulses; the duration of the input asynchronous pulses must exceed the duration of the sync pulse pause.

Thus, the introduction of additional links into the scheme makes it possible to increase its reliability at any combination of element switching times, including if the duration of the signal fronts exceeds the duration of the signal delays by the elements. In addition, this device extends the time interval during which the influence of transient processes after the falling edge of the input asynchronous pulse is eliminated.

In addition, the use of only one phase of the clock pulses to control the output element I 6 allows the upper frequency limit of the clock pulses to be increased by eliminating an additional element NOT from the clock circuit.

Claims (2)

1. USSR author's certificate No. 263670, H 03 K 5/13, 09.09.68. 2. USSR author's certificate No. 439911, H 03 K 5/13, 11.24.72.