SU790212A1 - Pulse synchronizing device - Google Patents

Description

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The invention relates to a pulse technique and can be used in discrete information processing systems for matching an asynchronous pulse signal with a clock frequency of an external device.

A device for synchronizing pulses is known, which contains three IS-NOT elements, two triggers and an inverter whose input is connected to the first input of the second AND-PE element, and the output is connected via the first IS-NOT element to the single input of the first trigger. The output of this trigger is The second element AND-NOT is connected to the single input of the second trigger, the first input of the additional element AND-NOT is connected to the output of the second trigger, the second input of the additional element AND-NOT is connected to the single input of the second trigger, and the output. and NAND - to the second inputs of the first element and the first trigger, the third input of the first element N – NO is connected to the second input of the second trigger 1.

However, the known device does not allow forming a pulse train simultaneously with a single pulse, which narrows the area of its application.

It is also known a device for synchronizing pulses, including 5. three triggers and an AND-NOT 2 element.

This device also does not allow simultaneous generation of a burst of pulses.

The purpose of the invention is the extension to the functionality of the computer system.

This goal is achieved by the fact that in the device for synchronization

15 pulses, containing three flip-flops and an NAND element, the first input of the first trigger connected to the first input of the NAND element, the second input of which is connected n to the output of the first

20 trigger, and the output of the element IS NOT connected to the first input of the second trigger, an inverter is introduced, the first. The third, the trigger is connected to the output of the first trigger, the second

25 whose input is connected to the output of the second trigger, the second input of which is connected to the input of the inverter, the output of which is connected to the third input of the NAND element and to the second

30 entrance of the third trigger.

FIG. Figure 1 shows the structural scheme of the proposed device for - temporary diagrams that clarify its operation. The device contains triggers 1, 2 and 3, element AND-HE 4, inverter 5, bus 6 asynchronous signal, bus 7 clock frequency, bus 8 single pulse, and also 9 bundles of pulses. Triggers 1-3 are built on two elements AND -NOT.

The device works as follows.

In the initial state, there is a low bus on bus b, and a high potential at the output of triggers 1-3. The bus 7 receives the clock pulses, which are inverted by the inverter 5 and transferred to the third input of the NAND 4 element and the first input of the trigger 3, High potential, received on the bus 6, allows the clock pause to pass through the IED 4. The resulting npir pause t Ktova frequency low potential at: output element AND-NOT 4 prepares the trigger, 2 to trigger at the time of the appearance at its second input of the pulse frequency. When the clock frequency pulse arrives at the bus 7, the trigger time 2 of the trigger arm 2 (the NAND element) triggers the output of this trigger to zero potential on the bus 8 and the second input of the trigger 1, which switches, and a low potential arrives at the second input of the element AND-NO 4, prohibit the passage of subsequent clock pulses. At the same time, the low potential arrives at the second input of trigger 3, the first input of which is at this time; low potential comes from the output of inverter 5, so the high potential is still present at the output of trigger 3. At the end of the clock synchronization pulse, a high potential is established at time t at the output of trigger 2. At the same time, the inverted pause of the clock frequency arrives at the first input of trigger 3. After 1 time of triggering trigger arm 3 (AND-NOT element), the output of this trigger establishes a zero potential received on bus 9.

When the clock pause ends, & at the output of the trigger 3 sets a high potential. While at the output of the trigger 1 there is a low potential at the output. trigger 3 synchronously with the pause of the clock frequency, a burst of pulses is formed. At the end of the asynchronous signal on the bus b, trigger 1 switches and a single potential is set at its output. Low

 potential arriving at its second input, trigger 3 is switched, and the synchronization device is reset.

Thus, in the presence of an asynchronous signal on the bus b of the device on bus 8, a single pulse is formed, which coincides in duration and phase with the first whole pulse of the clock frequency;

0 which, on the bus 9, a burst of pulses is formed, coinciding in duration and phase with a clock pause.

Claims (1)

Invention Formula A device for synchronizing pulses, containing three triggers and an NAND element, the first input the first trigger is connected to the first input of the NAND element, the second input of which is connected to the output of the first trigger, and the output of the NAND element is connected to the first input of the second trigger, which is different the fact that, in order to expand the functionality of the device, an inverter is inserted into it, with the first input of the third trigger connected to the output of the first trigger, the second input of which is connected to the output of the second trigger, the second input is cat. pogo connected to the input of the inverter, the output of which is connected to the third input element AND NOT with the second input of the third trigger. Sources of information taken into account in the examination I. USSR author's certificate 464070, cl. H 03 K 5/13, 1973. 2, USSR Author's Certificate 479236, cl. HW3 C 5/156, 1973.