SU746887A1 - Shaper of single pulses synchronized by clock frequency - Google Patents

Description

The invention relates to the field of automatics and computer technology and can be used, for example, as a starter device, to ensure the coordination of asynchronous trigger signals with a clock frequency of a sync signal generator. A device for forming single pulses is known, which contains three RS-flip-flops, AND elements and NOT ll. A disadvantage of the known device is complexity. Also known is a shaper of single pulses synchronized with a clock frequency, containing input and output triggers and three I elements, with the first inputs of the input trigger and the first element I connected to the input bus of the control signal, the second input of the first element I connecting to the single input of the input trigger , the output of the first element And is connected to the first inputs of the output trigger and the second element And, the second input of which is connected to the output of the output trigger, the output of the second element And is connected to the second input of A single trigger whose zero output through the third element I is connected to the second input of the output trigger, the third input of the first element I and the second input of the third element of I are connected to the input bus of the synchronizing clock frequency 2. The disadvantages of the known device are for its criticality to the duration and phase of the control signal relative to the synchronizing clock frequency (Sutr.) t receiving single pulses in the pauses between two clock signals with a duration equal to the duration of the pause timing clock. The aim of the invention is to increase the reliability of the formation of control pulses of any duration. The goal is achieved by the fact that in the formation of a single

746887 IMMB, synchronized with a clock frequency, containing input and output triggers and three elements AND, the first input of the input trigger is connected to one of the inputs of the first element AND, the other input of which is connected to ONE of the outputs B1 one-way 6 trigger, the output of the first element I is connected to the first vhbdom output trigger, the output of which is connected to the first input of the second element And, the output of which is the middle with the second input of the trigger, the second output of which is connected to the first input of the third element And, the second input of which th connected to the third input of the first AND gate, the output of the third AND apementa connected to; the second input of the output trigger, two taenne terminals are entered, the prG SfuM vshy shrvbgb 1sbyb1iga NOT connected to the control signal bus, and - to the bus from the first element I, the third input of which is not connected to the clock frequency bus through the second element and with the second input of the second element And FIG. Fig. 1 shows ({the driver circuit diagram; Fig. 2 is a timing diagram explaining its operation. The shaper of single pulses, synchronized with the clock frequency, contains the element HE 1, the trigger trigger 2, the element AND 3, the element 4, the elements AND 5 and 6, the output trigger 7, the element 8. NOT. The control signal bus 9 is connected via the NOT 1 element to the inverted input of the trigger input 2 and the first input of the IZ element, the second input of the AND 3 element is connected to a single output of the trigger input 2 bus 10 sync sync bars frequency is connected to the input element HE 4 and to the first input element I 5, the output element NO 4 is connected to the third input element I 3 and to the First input element I 6, the output Element I 3 is plugged to the inverted input trigger output 7, output of the element and the hrrrr hrrrrrrrrrrn the 1 st output: one output that is connected to the second input of the element 5, you are connected to the inverted zero input of the trigger 2 and through the element 8 to the output bus 11 single pulse. The shaper works as follows. In the initial state, the And 5 element is closed, and the triggers 2, 7 are in the zero state, and the clock clock frequency pulses are continuously input to the bus 1O. With the arrival of the control signal on bus 9, the input trigger 2 goes into one state, but at the output of the And 3 element, the high potential will be maintained as long as the control signal or clock frequency is active. As soon as the moment comes when the signals of the driver at the same time there are no these signals, the output of element 3 will have a low signal level, which will set the output trigger 7 into a single state and thus ensure that the clock frequency pulses pass through element 5 of shaper. The first impulse at the output of the AND 5 pulse sets the input trigger 2 to the zero state, but at the output of the AND 6 signal, there will be no signal as long as the clock pulse at the output of the pulse ensures that a single pulse passes. As soon as the generator fails: a sync pulse at the output of element K 6, the signal level is low, which sets output trigger 7 to the zero state and closes element 5 accordingly. Thus, a single impulse is received on output bus 11 , synchronized by the leading edge of the clock frequency pulse, with a duration equal to the duration of the pulse of the synchronizing clock frequency. In this way, the reliability of operation of the driver is increased due to the operation of the leading edge of the control signal and the formation of a single pulse synchronized with the leading and falling edges of the first integral sync pulse at the end of the control signal. Formula of the invention: Shaper of single pulses synchronized with a clock frequency, containing input and output triggers and three elements AND, with the first input

an input trigger is connected to one of the inputs of the first element AND, the other input of which is connected to one of the outputs of the input trigger. The output of the first element AND is connected to the first input of the output trigger whose output is connected to the first input of the second element AND whose output is connected to the second input of the input trigger, the second output of which is connected to the first input of the third element, And the second input of which is connected to the third input of the first element, And, the output of the third element, And connected to the second input of the output trigger, differing in order to increase the reliability of the formation of control pulses

of any duration, two elements are NOT entered into it, the input of the first element is NOT connected to the control signal bus, and the output is connected to one of the inputs of the first element I, the third input of which is not connected to the clock clock frequency through the second element and to the second the entrance of bopioro ment i

Sources of information taken into account in the examination

1. Authors. Certificate of the USSR № 515262, cl. H Q3 K 5/00, 09.O4.76.

2. USSR author's certificate J 514426, cl. H 03 K 5 / O1, 13.03.75.

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Claims (1)

Claim Shaper of single pulses synchronized by the clock frequency, containing input and output triggers and three AND elements, and the first input 5 746887 input trigger is connected to one of the inputs of the first element And, the other input of which is connected to one of the outputs of the input trigger, the output of the first element And is connected to the first input of the output trigger 5, the output of which is connected to the first input of the second element And, the output of which connected to the second input of the input trigger, the second output of which is connected to the first input 10 of the third element And, the second input of which is connected to the third input of the first element And, the output of the third element And is connected to the second input of the output trigger, 15 characterized in that, in order to increase the reliability of the formation of control pulses of any duration, two NOT elements are inserted into it, while the input of the first element is NOT connected to the bus of the control signal, and the output is to one of the inputs of the first element And, the third input of which through the second element is NOT connected to the clock clock bus and to the second input of the second element I.