SU790222A1 - Pulse signal delay device - Google Patents

Description

(54) DEVICE OF DELAYING A PULSE SIGNAL

The invention relates to a pulse technique and can be used in the construction of automatic devices. A device containing the first and second anchoring elements is known, the first input of the first anchoring element being connected to the output of the short side pulse former on the input signal and the output to one-shot, the first input of the second linking element is connected to the output of the short pulse pulse generator on the falling edge of the input signal, and the output - to the input of the output counting trigger, the second inputs of the elements The bindings are connected to the sync input of device ij. A disadvantage of this device is its complexity and consequence; This is low reliability. The purpose of the invention is to simplify the known device. To achieve this goal, a pulse signal delay device containing two short pulse drivers on the leading edge of the input signal, the outputs of which are connected to the inputs of the first OR element connected to the one-shot input, an output counting trigger, a D-trigger, an inverter, an And element, and a second the OR element, while the device input is connected to the information input of the D-flip-flop, the forward and inverse output of which is connected to the inputs of the short pulse formers on the leading edge of the input signal a, and the synchronizing input of the device is connected to the clock input of the D-flip-flop and through the inverter to the first input of the AND element, the second input of which is connected to the output of the OR element and the input of the output counting trigger, and the output to the first input of the second OR element, the second input of which is connected to the one-shot output. FIG. 1 is a functional diagram of the device in FIG. 2 shows diagrams explaining the operation of a pulse signal delay device. The device contains an input 1, a synchronizing input 2, a D-flip-flop 3, shapers 4 and 5 short pulses on the leading edge of the input signal, the element OR 6, the one-shot 7, the inverter 8, the element AND 9, the element OR 10, the counting trigger 11.

The device works as follows.

The input of the device 1 receives a sequence of pulses Gfig. 2ai, and on its clock input 2 - a sequence of stable pulses (Fig. 26). D-TriH, Germ 3 (Fig. 2c) binds the input signal (Fig. 2a) to the sequence pulses (Fig. 2, and the formers 4 and 5 short pulses on the leading edge of the input signal together with the OR 6 element assign the front and trailing edges of the input signal tied to synchronizing pulses (Fig. 2c, which trigger the vibrator 7) The duration of the output pulse of the one-shot 7 (t), which basically determines D-Bits-h-hold (tj), is chosen from the conditions

  0

where I-Min the duration of the input signal of the delay device is minimal; k 1, 2, 3 .., T is the repetition period of the synchronizing pulses.

In this case, the trailing edge of the output pulse of the one-shot 7 falls exactly on the middle of the interval between the two clock pulses fi.g. 2d, b) and the one-shot 7 is triggered by a subsequent pulse from the output of the Element OR 6 (FIG. 2 g, g

Prior to the appearance of the output single impulse of the one-vibrator 7 to the first, the input of the element And 9 is received by the inverted inverter 8 (physical. 2 a) pulses from the synchronizing input 2 (Fig. 26), and to the second input - logical O from the output of the element OR 10, the first and second inputs of which are logic O from the output of the one-shot .7, and the output of the element AND 9, respectively, and the trigger 11 is in the zero state. .

With the appearance of an output pulse. Single-vibrator 7, the element OR 10 sets the level corresponding to logical 1 at the second input of element AND 9, allowing the passage of pulses through element AND 9 from the output of inverter -8 to the second input of element OR 10 (Fig. 2d-3). With the end of the output pulse of the one-shot 7, the element AND 9 and the element OR 10 retain this state until the subsequent inverted clock pulse occurs, after

whereby the element AND 9, the element AND-LI 10 return to the initial state (Fig. 2d-3), and the counting trigger 11 switches to the single state (Fig. 2i).

Due to the fact that the one-shot is alternately triggered by pulses corresponding to the leading and trailing edges of the input signal tied to the sync pulses, the output signal of the counting trigger 11 triggered from the trailing edge of the output signal of the OR 10, element. repeats the input signal of the device, but is delayed in time.

If the instability of the trailing edge of the At T one-vibrator is one, the trailing edge of the output signal of the element OR is determined by a stable pulse from the device's sync input. Therefore, the device delay time

l l f

will be stable.

Thus, the proposed device, performed the same functions as the known ones, is simpler in design.

Formula. the invention

A delay device, a pulse signal, containing two short pulse impulses on the leading edge of the input signal, the outputs of which are connected to the inputs of the first OR element connected to the input of the one-oscillator, output trigger, characterized in that

0 devices, a D-flip-flop, an inverter element AND, the second OR element are entered into it, and the device input is connected to the information input of the D-flip-flop, the direct and inverse outputs of which are connected to the inputs

 drivers of short pulses on the leading edge of the input signal, and the synchronizing input of the device is connected to the clock input of the D-flip-flop and through an inverter with a pen0 vnm input of the And element, the second input of which is connected to the output of the second element OR and the input of the output counting trigger, and the output with the first the input of the second element OR,

5 the second input of which is connected to the output of the one-shot.

Sources of information accepted. Attention during the examination 1. USSR author's certificate

According to application number 264123b, cl. H 03 K 5/13 1978 (prototype).

d e

7K

Claims (1)

Formula. inventions' Delay device, pulse signal, containing two shapers of short pulses along the leading edge of the input signal, the outputs of which are connected to the inputs of the first OR element connected to the input of the one-shot, output counting trigger, characterized in that, in order to simplify the device, introduced a D-trigger, an inverter ^ element AND, a second OR element, while the input of the device is connected to the information input of the D-trigger, the direct and inverse outputs of which are connected to the inputs of the short pulse shapers on the leading edge of the input signal, and the synchronizing input of the device is connected to the clock input of the D-trigger and through the inverter to the first input of the AND element, the second input of which is connected to the output of the second OR element and the input of the output counting trigger, and the output to the first input of the second OR element , the second input of which is connected to the output of a single-shot.