SU658725A1 - Pulse synchronizing arrangement - Google Patents

Description

The invention relates more to the < 1 > pulse technique and can find n) and.enenie in control circuits of automatic devices synchronized by a clock frequency.

Pulse synchronization devices are known, containing two D-flip-flops and an AND I element.

Their disadvantage is the possibility of ao le: -1and short false pulses.

Of the known devices, the closest device to the invention is a pulse synchronizing device comprising an inverter, an output connected to the first input of the first match element, and an input from the clock pulse and the first input of the second match element, connected to the S-input of the output trigger, its output connected to the second input of the first element of the si-antenna, the output of which is connected to the exhaust bus (). M; 1ULSO 5 2.

A disadvantage of this device is that iirvrepn synchronized by its rsVJibcoB synchronization time coincides with clock pulses, as well as it is impossible (HocTi) to synchronize a burst with a pulse period of less than a clock pulse.

The purpose of the invention is to expand the functionality of the devices.

This is achieved by the fact that, in a pulse synchronization device containing an inverter, an output is connected to the first input of the first match element, and the input is connected to a clock bus and to the first input of the second match element, the output of which is connected to the S-input of the OUTPUT RS-trigger, your output connected to the second input of the first element of the match, the output of which is connected to the bus output pulses, introduced reversible pulse counter, the summing counting input of which is connected to the bus clock synchronized pulses itayuschy count input connected to the bus output pulses, and an output connected to the second input of the second overlaps and R-BXOdom output latch.

In the drawing, a functional diagram of a device for synchronizing pulses is given.

It contains a reversible counter I, elements 2 and 3, an inverter 4 and an output trigger 5.

In the initial state, the zero output of the reverse pulse counter 1 at. su, g (4g, signal out with a logical level of "Oh, cat | -] Y.1y, sets output trigger 5 to state" O and prohibits the passage of clock pulses through the first 2 and second 3 elements of the match.

When one or several synchronized pulses arrive at the zero output of the reversible pulse counter 1, a signal appears with a logical level of "1. This signal, in the absence of clock pulses, sets, via the coincidence element 2, output trigger 5 to the state "1. In this case, the passage of clock pulses through the coincidence element 3 to the device output is permitted.

The output pulses also go to the subtracting input of the reversible pulse counter 1, which switches along the trailing positive edge of the generated pulses.

When the number of pulses at the output of the device becomes equal to the number of synchronized ones, the signal at the output of the reversing counter 1 will again be set to a logic level "O, and the formation of the output pulses will stop.

The introduction of a new element - a reversible counter - significantly expands the functionality of the device. It is possible to synchronize the pulse bursts with a pulse repetition period less than the repetition period of the clock pulses, which cannot be realized by known devices.

Claims (2)

1. Gutnikov V.S. Integral electronics in measuring devices. L. Energie, 1974, p. 114 2. USSR author's certificate number 402143, cl. H OZK 5/13, 1973.