SU809483A1 - Phase comparator - Google Patents

Description

one

The invention relates to phase-measuring technology and can be used to build automatic synchronization devices for mobile electrical installations.

A phase comparator is known that contains a TpKfrep and three elements, NAND, the first inputs of the first and second elements NAND connected respectively to the first and second installation inputs of the trigger, the second inputs of these elements are connected respectively to the forward and inverse outputs of the trigger, and the outputs connected to the inputs of the third element AND NOT HE.

However, in the well-known phase comparator, when the pulse fronts of the compared frequencies coincide in time, the comparator may fail or double trip, i.e. its accuracy is low.

The purpose of the invention is to improve the accuracy, exclude failures or double alarms when the fronts of the compared frequencies coincide in time.

The goal is achieved by the fact that the phase comparator containing a trigger and three elements IS NOT, the first inputs of the first and second elements AND AND are NOT connected to the first and second installation inputs of the trigger, respectively, the second inputs of these elements and inverse inputs of the trigger, and the outputs are connected to the input of the third element AND –NE, a clock generator, an inverter, and two identical channels connected between the inputs of the phase comparator and the corresponding installation inputs igger, each channel is designed as two synchronous b-flip-flops and an element, whose first input is connected to the direct output of the first and D-input of the second synchronous D-flip-flops, the second input is connected to the inverse output of the second synchronous b flip-flop, and the third input is connected to the C - inputs of synchronous D-flip-flops and is the clock input of the channel, the output of the element I is the output, and the D input of the first synchronous t-trigger is the signal input of the channel, and the clock input of one of the channels is connected to

0 clock generator directly.

clock input of another channel through the nvertor.

The figure shows the structural electrical diagram of the phase comparator.

The phase comparator contains the trigger 1, the first 2, the second 3 and the third 4 elements AND-NOT, the clock generator 5, the inverter 6, as well as the first 7 and second 8 channels, made in the form of the first and second synchronous D-flip-flops 9 and 10 and the element And 11, as well as the source of controlled frequency 12 and the generator of the reference frequency 13.

Phase comparator works as follows.

The rectangular impulses of the source of the controlled frequency 12 and the clock generator 5 are received respectively at the D and C inputs of the first synchronous b-flip-flop 9, which generates pulses with a width corresponding to the pulses of the controlled frequency, but with fronts coinciding with the leading edges of the pulses of the clock generator 5. Formed by In this way, the pulses are delayed by the second synchronous L-trigger 10 for one clock cycle, equal to the period of the clock frequency. Element and 11 skips the clock pulse only at the time between the arrival of the -th pulse generated by the first synchronous b-trigger 9 and the pulse delayed by the second synchronous D-trigger 10 by one clock cycle.

As a result, at the beginning of each pulse of the controlled frequency, the first channel 7 forms a pulse that coincides in width and along the front with a forward clock pulse.

The second channel 8 works similarly. However, since one of its inputs receives clock pulses through the inverter 6, and the second receives pulses from the generator of the reference frequency 13, the second channel 8 forms at the beginning of each pulse of the reference frequency a pulse that coincides in width and nd fronts with inverse clock pulse.

Thus, in the event that the leading edges of the pulses of the standard and controlled frequencies coincide, the inputs of the trigger 1 from the outputs of the first 7 and second 8 channels receive pulses that do not coincide with time. From the output of the first channel 7, the pulse passes only into the interval between the leading and falling edges of the clock pulses, and from the output of the second channel 8 into the interval between the falling and leading edges of the clock pulse.

When the phases of two compared frequencies coincide, a state arises which is characterized by the fact that in the interval between the arrival at one trigger of two successive pulses of one compared frequency to another, two pulses of another compared frequency pass through its input. In this case, the first of the successive impulses is memorized by a trigger, thereby allowing passage through the corresponding AND-NOT element 2 or 3 of the second of the consecutive pulses that arrived at the same input. From the output of the corresponding circuit, the element IS-NOT 2 or 3, the pulse passing through it goes through the third element IS-NOT 4 to the output of the comparator, analyzing the coincidence of the phases of the compared frequencies.

The proposed connection of elements makes it possible to eliminate the possibility of the phase comparator not working or double triggering when the pulse fronts of the compared frequencies coincide in time, which improves the accuracy and reliability of operation.

Claims (1)

1. USSR author's certificate 484621, H 03 D 13/00, 1974. eleven eight . H 9VyhoZ