SU817979A1 - Multiphase inverter control device - Google Patents

Description

(54) DEVICE FOR MANAGING MULTI-PHASE

INVERTER

delay element and is the input to the driver.

FIG. 1 shows a diagram of the device; in fig. 2: - diagrams of his work.

The multiphase inverter device includes a synchronization pulse generator 1, a phase locked loop 2, a phase detector 3, a pulse width converter into voltage converter 4, a controlled oscillator 5 and a frequency divider 6, as well as a short frequency pulse generator 7, counter 8 pulses, shift register 9 and delay element 10. The shaper 7 short pulses of double frequency contains a delay element 11 and an element exclusive OR 12.

The device works as follows.

The pulses 3 from the output of the generator 1 of the synchronizing pulses of OTT arrive at one input of the phase detector 3, to another input of which pulses 14 are output from the output de; 1; 1 of the 6 frequency. On v; phase phase. Network. | (Pa J form (: impulse 15, duration;: osg KOTcpiiix paBiiH phase separation between synchronizing; impulses. 13 and output impulse; - m 14 del-gel 6 frequency At the same time, if impulses 13 The signal 14 is ahead in phase, the polarity of the output pulses 15 of the phase detector 3 is positive (Fig. 2), if they lag behind, it is negative. The constant voltage 16 is fed to the input equal oscillator 5, which in the stationary mode generates pulses 17, whose frequency is an integer times the output frequency of the inverter, a delayed signal 18 arrives at the control input of the shift register 9. the duration of the pulses 15 at the output of the phase detector 3 and the DC voltage 16 at the input of the controlled generator increases 5. The frequency of the generator increases and the phase of the output pulses 14 of the frequency divider 6 changes to that the frequencies of signals 13 and 14 will again be equal to each other. In this way, the control device, and hence the inverter as a whole, from another AC source is synchronized.

High-frequency pulses 17 from the output of the controlled generator 5 are fed to the counting input of the pulse counter 8, to the installation input of which pulses 19 are fed from the former 7 short pulses of double frequency. At the end of each half cycle of the synchronization voltage, these pulses set the counter 8 to the state "O. Impulses 20 s

the output of the counter goes to the clock input of the shift register 9, to the control input of which, through the delay element 10, clock pulses occur 13. At the outputs of the shift register 9, a symmetric (t-1) -phase sequence of control pulses 21 ... 25 is formed. As the first sequence of control pulses, synchronizing pulses 13 are used, therefore the resulting phase-sequence pulse sequence is in phase with the network.

The necessity of introducing a short frequency double frequency pulse generator 7 is due to the fact that in transients due to the inertia of phase 2 frequency locked loop, the frequency of the controlled oscillator 5 is not a multiple of the clock frequency 13. This causes the logical "O signal at the clock input of the shift register 9 appears after the change of the signal 13 at the control input of the register; and, consequently, the phase shift between the output pulses of the shift register 21 ... 25 and the synchronizing pulses 13 is violated, . E. Occurs unbalance control pulses constituents. WITH

5, using short double-frequency pulses 19, the phase shift between the control pulses is corrected, which increases their symmetry.

Real counters have a finite switching time, so if at the time the signal 13 changes, counter 9 will be in the state, then when the counter is reset to O pulses 19 from the short frequency pulse generator 7, the register 9 will switch which also violates the correct functioning of the shift register 9 and leads to an asymmetry of the control pulses. To eliminate this drawback, the arrival of the signal 13 at the control input of the shift register 9 is delayed by the element

0 10 delay at the time of reset of the counter 8 pulses.

Thus, the proposed device allows the in-phase operation of the inverter-C network.

Claims (2)

1. A device for controlling a multi-phase inverter, comprising a clock pulse shaper and a phase locked loop unit, containing a ringed phase detector, a controlled oscillator, and a frequency divider, characterized in that, in order to ensure the in-phase operation of the inverter with the network, it is additionally equipped with a driver short pulses of double frequency, pulse counter, delay element and shift register, control input which through the delay unit is connected to the clock pulse shaper, the clock input of the specified shift register is connected to the output of the last digit of the pulse counter, the counting input of which is connected to the output of the controlled oscillator, and the pulse counter setting input is connected to the output of the clock synchronizer pulses. 2. A device according to claim 1, characterized in that the shaper of short pulses The double frequency comprises a serially connected delay element and an exclusive OR element, the other input of which is combined with the output of the specified delay element and is the input of the driver. Sources of information taken into account in the examination 1. USSR author's certificate number 124519, cl. H 02 M 7/48, 1964. 2. US patent number 3803476, cl. 321-5 1978.