KR970005112Y1 - Phase locking device - Google Patents

Abstract

None.

Description

Phase synchronizer

1 is a block diagram of a phase synchronization device of the present invention.

2 is a waveform diagram of each part according to the driving of the phase synchronization device of the present invention.

FIG. 3 is a waveform diagram for explaining phase synchronization according to the driving of the phase synchronization device of the present invention.

* Explanation of symbols for main parts of the drawings

11: clock generating means 12: window pulse generating means

13: reset signal generating means 14: dispensing means

15 counting means 16 transistor

17: first inversion gate 18: second inversion gate

The present invention relates to a device for achieving phase synchronization, and more particularly to a phase synchronization device for synchronizing the phase of the output frequency of the equipment when two or more devices in parallel operation.

In general, a phase locked device (PLL) is a device used to synchronize the phase of the output frequency of each device when two or more devices are operated in parallel, and the two or more devices are each modified with the same frequency. Since the oscillation is performed using a generator, the output frequency is the same, but because the phases are different, the phase synchronization circuit should be used to match the phase of each equipment.

Conventional phase synchronization devices used to achieve synchronization of the devices running in parallel as described above were synchronized between the devices by continuously feeding and comparing the ratio ratio and the synchronization signal of the slave equipment. The method of synchronizing a device takes a long time to be synchronized, and the device is also complicated.

Accordingly, an object of the present invention is to provide a phase synchronization device that can be configured as a simple circuit in order to solve the conventional problems as described above, and can be synchronized between main and slave equipment during a clock of two cycles.

Phase synchronization device of the present invention for achieving the above object,

Clock generation means for generating a clock of a predetermined frequency; Window pulse generation means for generating a window pulse by inputting a clock generated from the clock generation means; Reset signal generating means for generating a reset signal by inputting a pulse generated from the window pulse generating means and a synchronization signal of a slave device; A divider means for dividing a clock signal input from the clock generator means and outputting the clock signal corresponding to the reset signal from the reset signal generator; And counting means for forming and outputting a clock signal input from the dividing means to form a synchronizing signal of the slave equipment synchronized with the reset signal from the reset signal generating means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of a phase synchronization device of the present invention, comprising: clock generating means (11) for generating a clock of a predetermined frequency; A window pulse generating means (12) for generating a window pulse by inputting a clock generated from the clock generating means (11); Reset signal generation means (13) for generating a reset signal by inputting a pulse generated from the window pulse generation means (12) and a synchronization signal of the slave equipment; A divider means (14) for dividing the clock signal inputted from the clock generator (11) and outputting the clock signal corresponding to the reset signal from the reset signal generator (13); And counting means 15 for outputting the clock signal input from the distributing means 14 to form and output a synchronous signal of the slave equipment synchronized with the reset signal from the reset signal generating means 13.

In addition, the phase synchronizing apparatus includes a transistor 16 for inputting clock pulses synchronously outputted from the counting means 15 as a base to form and output a signal synchronized with the collector and the emitter and an inverted synchronization signal, respectively; A clock output from the first inverting gate 17 and the counting means 15 for inverting the window pulse generated by the window pulse generating means 12 and supplying it to one input terminal of the clock generating means 11; And a second inversion gate 18 for inverting the pulse and inputting the pulse to the base of the transistor.

The reset signal generating means 13 is composed of negative logical means, and the counting means 15 is composed of hex counting means.

(A) to (c) of FIG. 2 are waveform diagrams of the respective parts according to the driving of the phase synchronizing apparatus of the present invention, and (a) is a vertical equipment input to one input terminal of the reset signal generating means (13). And (b) an inverted window formed by the window pulse generating means 12 and inverted by the first inverting gate 17 and input to the other input terminal of the reset signal generating means 13. (C) shows a reset signal formed by the reset signal generating means 13 corresponding to the two signals.

(A) to (c) of FIG. 3 are waveform diagrams for explaining phase synchronization according to the driving of the phase synchronization device of the present invention, (a) is a clock signal with a ratio ratio, and (b) is a slave device. Is a clock signal, and (C) shows a synchronization signal 33 phase-locked corresponding to the two clock signals.

It will be described in detail the driving method of the phase synchronization device of the present invention according to the above configuration.

The window pulse generating means 12 inputs a clock generated from the clock generating means 11 to form and output a window pulse. This window pulse is formed as an inverted window pulse as shown in FIG. 2 through the first inversion gate 17.

The negative logical means constituting the reset signal generating means 13 inputs the inverted window signal and the clock signal generated by the clock generating means 11 to two input terminals so that the two signals become " low " A momentary reset signal is formed and output.

The dispensing means 14 inputs a clock from the clock generating means 11 on the basis of the generated reset signal and divides and outputs the divided clock to a predetermined predetermined clock. In addition, the counting means 15 outputs a signal formed by the dispensing means 14 as a synchronization signal 33 of the slave equipment based on the generated reset signal. In the case of single operation, the reset signal is formed at the rising edge of the window pulse as shown in FIG. 2, but in the case of parallel operation, as shown in FIG. 3, the window pulse is used to form the synchronization signal of the slave equipment. The reset signal is formed at the falling edge of. That is, the reset signal is formed by being advanced by "t" seconds rather than the reset occurrence time in the single operation, which enables the synchronization signal to be formed only two times. Therefore, the time to be reduced is represented by the formula {(2T / 2) -t)}.

On the other hand, the clock output from the counting means 15 is inverted through the second inverting gate and outputted to the base of the transistor 16.

Accordingly, the opposite clocks are formed on the collector and the emitter of the transistor 16 and output. As described above, the clock formed in the collector of the transistor 16 formed by the operation is formed of a signal of which the period for t1 seconds indicated by the phase-synchronized clock signal of FIG. 3 is shortened.

The clock formed by the above method is input to the reset signal generating means 13 again, and the reset signal generating means 13 forms and outputs a corresponding reset signal. Accordingly, the dispensing means 14 and the counting means 15 form and output a new clock in the same manner as described above.

This forms and outputs a signal with a shorter period for " t2 " seconds indicated in the phase-synchronized clock signal of FIG. This is a clock that forms a down edge at the same time as the down edge of the ratio ratio clock signal. The next clock is formed and outputted as a phase-locked clock signal 33 synchronized with the ratio ratio clock signal.

Thus, the phase synchronization circuit of the present invention has the effect of synchronizing the phase between the ratio and the slave device during two clock cycles by using a circuit that is simpler than the time when the reset signal is generated.

Claims (3)

Clock generating means (11) for generating a clock of a predetermined frequency; A window pulse generating means (12) for generating a window pulse by inputting a clock generated from the clock generating means (11); Reset signal generation means (13) for generating a reset signal by inputting a pulse generated from the window pulse generation means (12) and a synchronization signal of the slave equipment; A divider means (14) for dividing the clock signal input from the clock generator (11) and outputting the clock signal corresponding to the reset signal from the reset signal generator (13); A phase synchronizing device (15) comprising a counting means (15) for outputting a clock signal input from said distributing means (14) to form and output a synchronizing signal of the slave equipment synchronized with the reset signal from said reset signal generating means (13). The transistor of claim 1, wherein the phase synchronization device comprises: a transistor for inputting clock pulses synchronously outputted from the counting means 15 as a base to form and output a signal synchronized with a collector and an emitter and an inverted synchronization signal, respectively; A phase synchronizing device further comprising 16). 2. The phase inversion device as set forth in claim 1, wherein said phase synchronization device inverts the window pulse generated by said window pulse generating means (12) and supplies it to one input terminal of said clock generating means (11). And; And a second inverting gate (18) for inverting the clock pulse output from said counting means (15) and inputting it to the base of said transistor.