JPH02149081A - Dot clock pulse generator - Google Patents

Abstract

PURPOSE:To generate a dot clock pulse coincident with the phase of a horizontal synchronising pulse (HSP) within 1/2 period of a clock pulse by generating a clock pulse having a period obtained by dividing an effective horizontal display period by the number of display dots in one line and using the HSP as a timing signal to latch the clock pulse. CONSTITUTION:The dot clock pulse generator is constituted of a clock pulse generating circuit 12 for generating a clock pulse having a period obtained by dividing the effective horizontal display period of a display device providing a screen for superimposing by the number of display dots in one line, a latch circuit 13 for latching the output clock pulse of the circuit 12 by using the rise of a HSP as a timing signal and an exclusive OR gate 14 for operating a practical exclusive OR between the latch output of the circuit 13 and the clock pulse and outputting a dot clock pulse. Consequently, the phase of the dot clock pulse can be allowed to coincide with the phase of the HSP within 1/2 period of the clock pulse at maximum.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a dot clock pulse that generates a dot clock pulse used for superimposition, etc. [Prior Art] Displaying two or more images on the same screen This is generally called superimposition. For example, when superimposing images such as characters and graphics onto the screen of a television receiver, a dot clock pulse synchronized with the horizontal synchronization signal of the television signal is required. . This is because if the phase of the dot clock pulse deviates from the horizontal synchronization signal, the insertion position of characters, figures, etc. during the effective horizontal display period within the L line also deviates, resulting in fluctuations in the characters, figures, etc. displayed on the screen. This is because it looks like an eyesore.

The dot clock pulse generator f shown in FIG. 3 generates dot clock pulses of a desired frequency by frequency-doubling the horizontal synchronization pulse separated from the video signal by the horizontal synchronization separation circuit 2 using the phase-locked loop circuit 3. It is. The horizontal synchronization pulse separated by the horizontal synchronization separation circuit 2 is passed through the phase comparator 4 in the phase locked loop circuit 3.
The phase is compared with the divided output of the output clock pulse sent through the frequency divider 5. And phase comparator 4
The phase comparison error obtained from is fed back to the voltage controlled oscillator 7 after the harmonic components in the low range are removed by the wave generator 6, and the voltage controlled oscillator 7 outputs an oscillation output with a frequency corresponding to the phase comparison error. It is sent out as a dot clock pulse to the superimpose device 8, and at the same time is also fed to the frequency divider 5 to form a feedback loop. Therefore, the phase-locked loop circuit 1 functions as a narrow band wave circuit whose center frequency is varied by the horizontal synchronization pulse.

[Problems to be Solved by the Invention] The above-mentioned conventional dot clock pulse generator 1 uses the phase-locked loop circuit 3, so that it is possible to obtain highly accurate dot clock pulses. The phase comparator 4, the low-pass filter 6, the voltage-controlled oscillator 7, and the frequency divider 5 are all composed of complicated circuits, and have the problem of being expensive.

[Means for Solving the Problems] The present invention solves the above problems, and includes a clock pulse generator that generates clock pulses having a period obtained by dividing the effective horizontal display period by the number of display dots in one line. A latch circuit that latches the output clock pulse of this clock pulse generation circuit with a horizontal synchronization pulse as a timing signal, and a dot clock that takes a substantial exclusive OR of the latch output of this latch circuit and the clock pulse. It consists of a gate circuit that outputs a pulse, and is characterized by a structure in which the output dot clock pulse of the gate circuit is made to match the phase of the horizontal synchronizing pulse within a maximum deviation of 1/2 cycle of the clock pulse. .

[Function] This invention improves the effective horizontal display period! A clock pulse with a period obtained by dividing by the number of display dots on a line is generated, and this clock pulse is latched into a latch circuit using the horizontal synchronization pulse as a timing signal, and this latch output and the clock pulse are essentially exclusive logic By achieving harmony,
A dot clock pulse is generated whose phase matches the horizontal synchronizing pulse with a shift within 1/2 period of the clock pulse.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1.2. FIG. 1 is a circuit diagram showing an embodiment of the dot clock pulse generator of the present invention, and FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG.

In FIG. 1, the dot clock pulse generator 11 divides the effective horizontal display period (52.5 μs) of the display device that provides the screen for superimposition by, for example, 168 as the number of display dots in the line. A clock pulse generation circuit 12 that generates a clock pulse with the obtained period (0,313 μs), and a latch circuit 13 that latches the output clock pulse of the clock pulse generation circuit 12 using the rising edge of the horizontal synchronization pulse as a timing signal.
and an exclusive OR gate circuit 14 which performs a substantial exclusive OR of the latch output of the latch circuit 13 and the clock pulse, and outputs a dot clock pulse.

Latch circuit! 3 is a circuit for determining the phase of the clock pulse at the rising edge of the horizontal synchronizing pulse, and in the embodiment, a D flip-flop circuit is used. Here, if the clock pulse is in positive phase at the rising edge of the horizontal synchronizing pulse, the Q output of the latch circuit 13 is at a low level, and conversely, if the clock pulse is in reverse phase at the rising edge of the horizontal synchronizing pulse, the latch circuit 13 The Q output of is at high level. On the other hand, the exclusive OR gate circuit 14 controls the passage of clock pulses using the Q output of the latch circuit 13 as a gate signal, and functions as an inverter or an OR gate depending on whether the gate signal is high or low.

By the way, as shown in the first half of the time axis in FIG. 2, if the polarity of the clock pulse is negative at the rising edge of the horizontal synchronizing pulse, that is, it is a positive phase clock pulse,
The exclusive OR gate circuit I4 receiving the low level gate signal from the latch circuit 13 functions as an OR gate for the clock pulse, and passes the positive phase clock pulse as it is as a dot clock pulse.

On the other hand, as shown in the second half of the time axis in FIG. 2, if the polarity of the clock pulse is positive at the rising edge of the horizontal synchronization pulse, that is, it is a reverse phase clock pulse,
An exclusive OR gate circuit that receives a high-level gate signal from the latch circuit 13 functions as an inverter for the clock pulse, inverts the polarity of the opposite phase dot clock signal, and then sends it out as a dot clock pulse.

As mentioned above, the dot clock pulse generator 11 is
Exclusive OR gate circuit 14 is latch circuit 1
By receiving the Q output of 3 and functioning as an OR gate or inverter, it is possible to always output positive phase clock pulses as dot clock pulses.
It is possible to match the phase with the horizontal synchronization pulse with a difference of /2 cycles.

[Effects of the Invention] As explained above, the present invention generates a clock pulse with a period obtained by dividing the effective horizontal display period by the number of display dots in one line, and uses this clock pulse as a horizontal synchronizing pulse with timing. Latch it into a latch circuit as a signal,
Since this latch output and the clock pulse are essentially exclusive ORed to form a dot clock pulse, at the rising edge of the horizontal synchronization pulse, the polarity of the clock pulse is negative, and the clock pulse is in positive phase. In the case of , if the polarity of the clock pulse is positive and the clock pulse is of reverse phase, the gate circuit that receives the high-level gate signal from the latch circuit functions as an inverter and inverts the polarity of the dot clock signal of the reverse phase. Therefore, it is possible to always generate a dot clock pulse whose phase matches the horizontal synchronization 7<rus within 1/2 period of the clock pulse. This provides excellent effects such as the ability to easily generate dot clock pulses required for imposition and the like.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the dot clock pulse generator of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. FIG. 2 is a circuit diagram showing an example of a generator. 11. Dot clock pulse generator. 12. Clock pulse generation circuit, 13° latch circuit, 14. , Exclusive OR gate circuit. Figure 1 Figure 2

Claims (1)

[Claims] A clock pulse generation circuit generates a clock pulse with a period obtained by dividing the effective horizontal display period by the number of display dots in one line, and the output clock pulse of this clock pulse generation circuit is latched using the horizontal synchronization pulse as a timing signal. It consists of a latch circuit that performs a substantial exclusive OR of the latch output of this latch circuit and the clock pulse, and outputs a dot clock pulse. A dot clock pulse generator configured to match the phase of a horizontal synchronizing pulse within a range of 1/2 period shift.