JPH03113975A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To generate a clock with a prescribed frequency in following to an input video signal by shifting the phase of a clock signal phase-locked to a synchronizing signal of the input video signal through the use of a burst signal of the input video signal. CONSTITUTION:When an output voltage of a phase comparator circuit 36 is V1, a PLL circuit 50 locks the phase so that the output voltage of a phase comparator circuit 38 is -V1. When a phase difference of the output clock of a PLL circuit 34 is phi with respect to a burst signal 32B, a phase difference of the output clock of a frequency divider circuit 48 is -phi with respect to the output clock of the PLL circuit 34, the phase of the burst signal 32B and the phase of the output clock of the frequency divider circuit 38 are in phase. Thus, a clock in following a video signal including jitter is obtained at an output terminal 46.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock generation circuit that generates a clock that follows jitter in a video signal that includes jitter.

[Prior Art] Conventionally, as a method for removing jitter from a video signal, a configuration using a digital time base collector is known. This samples the video signal using a clock that follows the jitter of the video signal, converts it into a digital signal, writes it into memory, reads it out using a stable fixed clock, and converts it back to an analog signal. This makes it possible to obtain a video signal that does not include jitter.

The circuit configuration shown in FIG. 2 is conventionally known as a circuit that generates a clock that follows the jitter of a video signal.

10 is an input terminal for a video signal including jitter. This video signal includes a horizontal synchronization signal and a burst signal, as shown in FIG. The synchronization separation circuit 12 separates a horizontal synchronization signal and a burst signal from the video signal at the input terminal 1o, and sends the separated horizontal synchronization signal 12A to the PLL circuit 14.
The separated burst signal 12B is supplied to the phase comparison circuit 16. PLL circuit 14 separates horizontal synchronization signal 12A
A phase comparison circuit 16 compares the phases of the output of the PLL circuit 14 and the burst signal 12B from the synchronization separation circuit 12. The level conversion circuit 18 adjusts the output level of the phase comparison circuit 16. The phase shift circuit 20 phase-shifts the output clock of the PLL circuit 14 according to the phase difference signal supplied from the phase comparison circuit 16 via the level conversion circuit 18. This provides a clock that is in phase with the burst signal 12B and has the same frequency. A frequency multiplier circuit 22 converts the output of the phase shift circuit 20 into a signal with N times the frequency.

This provides a sampling clock for A/D conversion when writing to the memory.

Merely matching the phase with the horizontal synchronizing signal does not provide sufficient horizontal synchronizing signal detection accuracy and causes a large error, so the error is usually removed by matching the phase with the burst signal.

[Problems to be Solved by the Invention] However, in the conventional example described above, the input/output characteristics of the phase shift circuit 20 and the phase comparator circuit 16 are different, so the level conversion circuit 18 is required to absorb the difference. Therefore, the clock output from the phase shift circuit 20 and
There is a phase error between it and the burst signal 12B that depends on the conversion accuracy of the level conversion circuit 18. In particular, if the phase shift circuit 20 and the phase comparator circuit 16 have non-linear characteristics, the circuit configuration of the level conversion circuit 18 will become very complicated and the conversion accuracy will deteriorate.

In the conventional example, the phase shift circuit 20 and the multiplier circuit 22
Another problem is that the circuit configuration is complicated.

Therefore, an object of the present invention is to provide a clock generation circuit that eliminates such problems.

[Means for Solving the Problems] A clock generation circuit according to the present invention is a circuit that generates a clock of a predetermined frequency that follows an input video signal, and which generates a clock according to a synchronization signal of the input video signal and a target clock. a first phase comparison means for phase comparing the synchronization signal of the input video signal and a burst signal of the input video signal; and a first and second phase comparison means for comparing the phases of the synchronization signal and the burst signal of the input video signal. , and an oscillating means that oscillates at a frequency corresponding to the output of the adding means.

[Operation] The first phase comparison means and the oscillation means constitute a PLL circuit. Therefore, when the output of the second phase comparison means is zero, the output of this PLL circuit becomes a clock signal whose phase is synchronized with the synchronization signal of the input video signal, but it depends on the output level of the second phase comparison means. is phase-shifted, and finally,
It becomes phase synchronized with the burst signal of the input video signal.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration block diagram of an embodiment of the present invention. 30 is a video signal input terminal; 32 is a synchronization separation circuit that separates the horizontal synchronization signal and burst signal of the video signal; 34
is the horizontal synchronization signal 3 separated by the synchronization separation circuit 32
2A, a PLL circuit generates a clock having a burst signal frequency; 36 is a burst signal 32B separated from the output of the PLL circuit 34 by the synchronization separation circuit 32;
A phase comparison circuit 38 compares the phase of the PLL circuit 3 with
This is a phase comparison circuit that compares the phases of the output clock of No. 4 and a clock obtained by dividing the target clock by N. The phase comparison circuits 36 and 38 are circuits having the same internal configuration and the same input/output characteristics.

40 is an adder that adds the outputs of the phase comparison circuits 36 and 38; 42 is a loop filter with sufficient gain in the low frequency range;
44 is a voltage controlled oscillator (VCO), 46 is a clock output terminal, and 48 is a frequency dividing circuit that divides the output clock of the VCO by N and supplies it to one input of the phase comparison circuit 38.

The phase comparator circuits 36 and 38 may have different circuit configurations as long as approximately the same human output characteristics can be obtained, and can be adjusted so that they are approximately the same even if the input/output characteristics are different. That's fine.

Next, the operation shown in FIG. 1 will be explained. Synchronous separation circuit 32, P
The operations of the LL circuit 34 and the phase comparator circuit 36 are the same as in the conventional example. phase comparison circuit 38, rube filter 42,
The loop consisting of the VCO 44 and the frequency dividing circuit 48 is a PLL
The circuit 50 is configured so that when the output of the adder 40 is zero, a target clock of a predetermined frequency is obtained at the output terminal 46 (that is, the output of the VCO 44).

Here, if the output voltage of the phase comparison circuit 36 is V,
In the PLL circuit 50, the phase is locked so that the output voltage of the phase comparison circuit 38 becomes 1. This means that when the phase comparison circuit 38 has the same characteristics as the phase comparison circuit 36, the phase difference between the two inputs of the phase comparison circuit 38 is
6 shows that the phase difference between the two inputs is the same in absolute value and only has a different sign. That is, when the phase difference between the output clock of the PLL circuit 34 and the burst signal 32B is φ, the phase difference between the output clock of the frequency dividing circuit 48 and the output clock of the PLL circuit 34 is −φ.

That is, the burst signal 32B and the output clock of the frequency dividing circuit 48 have the same phase.

In this way, a clock that follows the video signal including jitter is obtained at the output terminal 46.

In this embodiment, the phase is locked to the burst signal frequency, but the phase may be locked to the horizontal synchronization signal.

Effects of the Invention] As can be easily understood from the above description, according to the present invention, a clock signal that follows a video signal including jitter can be obtained with a very simple configuration. In addition, fewer adjustment elements are required during circuit manufacturing, and high accuracy can be easily achieved.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention, FIG. 2 is a configuration block diagram of a conventional example, and FIG. 3 is a waveform diagram of a video signal. 30: Video signal input terminal 34: PLL circuit 36
．． 38: Phase comparison circuit 40: Adder 42: Loop
Filter 44: Voltage controlled oscillator 46: Clock output terminal 48: Frequency divider circuit

Claims (1)

[Claims] A circuit that generates a clock of a predetermined frequency that follows an input video signal, the first phase comparison means for comparing the phases of a synchronization signal of the input video signal and a clock corresponding to a target clock; a second phase comparison means for comparing the phases of the synchronization signal and the burst signal of the input video signal;
A clock generation circuit comprising: an addition means for adding the outputs of the first and second phase comparison means; and an oscillation means for oscillating at a frequency according to the output of the addition means.