JPH0530379A - Clock signal generating device - Google Patents

Abstract

PURPOSE:To generate a clock signal synchronously with a horizontal synchronizing signal by using an AFC having a VCO making accurate oscillation and locked to the horizontal synchronizing signal so as to lock a PLL thereby outputting a clock signal synchronously with the horizontal synchronizing signal. CONSTITUTION:The AFC comprising a VCO 7 making accurate oscillation, a phase comparator 3 and a filter 5 is locked to a horizontal synchronizing signal. A PLL comprising a phase comparator 9, a filter 11, a VCO 13 and a frequency divider 15 is locked by a pulse outputted from the AFC and a clock signal synchronously with the horizontal synchronizing signal is generated and outputted from the VCO 13. Thus, no adjustment for free-run of the PLL is required and the effect of disturbance due to the horizontal synchronizing signal before and after the vertical synchronizing signal or due to noise is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generator suitable for generating a clock signal necessary for a memory controller, a DSP and the like.

[0002]

2. Description of the Related Art In a device such as a memory controller or a DSP having a digital section which operates by a clock signal, a basic clock signal is an integral multiple of a horizontal frequency and locked to a horizontal synchronizing signal.

That is, as understood from FIG. 2, the horizontal sync signal is separated from the composite video signal input to the sync separation circuit 10 and is input to the phase comparator 20.

On the other hand, the clock signal is oscillated by the VCO 50, frequency-divided by the frequency divider 40 to the horizontal frequency, and input to the phase comparator 20.

If there is a phase difference between the horizontal synchronizing signal and the divided clock signal, the error component is input to the filter 30 and a potential in the correcting direction is given from the filter 30 to the VCO 50. Locked to horizontal sync signal.

The clock signal is input to a device 60 such as a memory controller or DSP.

[0007]

However, in the conventional circuit configuration, when the input signal (horizontal synchronizing signal) disappears,
Since the VCO 50 (oscillator) oscillates at the free-run frequency, it is necessary to adjust the oscillation frequency at that time to the horizontal frequency.

Further, since the horizontal synchronizing signal is affected by the equalizing pulse in the vertical synchronizing portion, the error output of the phase comparator 20 is disturbed, resulting in a problem that the generated clock signal is disturbed.

It is an object of the present invention to provide a clock signal generation device which does not require adjustment to adjust free run and is less affected by disturbance before and after vertical synchronization.

[0010]

A clock signal generator according to the present invention is a VCO 7 using a ceramic oscillator.
AFC circuits 3, 5 and 7 that lock to the horizontal sync signal with
PLL circuits 9, 11, 13, 15 for generating a basic clock signal of the device 60 including at least a memory controller
And the frequency of the PLL circuits 9, 11, 13, 15 is locked by the pulse signals locked by the AFC circuits 3, 5, 7, and a clock signal synchronized with the horizontal synchronizing signal is generated. And

[0011]

In the clock signal generator according to the present invention, the AF
The frequency of the PLL circuit is locked by the pulse signal locked by the C circuit, whereby a clock signal synchronized with the horizontal synchronizing signal is generated.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a clock signal generator according to the present invention will be described below with reference to the drawings.

In FIG. 1, the horizontal sync signal is separated from the composite video signal input to the sync separation circuit 1 and is input to the phase comparator 3.

The oscillator of the VCO 7 is a ceramic oscillator, which oscillates accurately at an integral multiple of the horizontal frequency,
The output signal of the VCO 7 is input to the phase comparator 3.

Then, the phases of the horizontal synchronizing signal and the output signal of the VCO 7 are compared by the phase comparator 3, and if there is a phase error, the oscillation frequency of the VCO 7 is changed via the filter 5, and the phase comparator 3 and the filter are changed. 5, and VCO
The oscillation frequency of the VCO 7 is locked to the horizontal synchronizing signal by the AFC circuit composed of 7.

On the other hand, the output of the VCO 7 is also input to the phase comparator 9, and the phase comparator 9 and the filter 1
1, the VCO 13, and the frequency divider 15 constitute a PLL circuit.

The VCO 13 is a CR oscillator with a built-in IC, and its output is frequency-divided by the frequency divider 15 and input to the phase comparator 9.

Therefore, the phase comparator 9 compares the phase of the pulse from the AFC circuit with the output pulse of the frequency divider 15, and the oscillation frequency of the VCO 13 corresponds to the output of the filter 11 from the AFC circuit. Locked to the pulse of.

Since the pulse from the AFC circuit is locked to the horizontal cycle signal, the oscillation frequency of the VCO 13 is also locked to the horizontal synchronizing signal.

In this case, when the input of the composite video signal disappears, the loop of the AFC circuit oscillates at the free-run frequency of the VCO 7, but since the VCO 7 oscillates at the frequency determined by the ceramic oscillator, there are variations. There are few values close to the horizontal frequency, and no adjustment is required to match the free run.

Further, since the pulse is always input from the AFC circuit to the PLL circuit, the VCO 13 does not oscillate in free run, and the state locked by the input pulse is maintained.

The output signal of the VCO 13 is used as a basic clock signal required for the device 60 such as a memory controller or DSP.

As described above, in this embodiment, V
Since the CO7 always oscillates accurately and the pulse from the AFC circuit is always input to the PLL circuit, the VCO 13 does not oscillate in free run.

Therefore, the free-run adjustment is not required, the resonance sharpness of the ceramic oscillator is high, the frequency pull-in range is narrowed, and the AFC loop is passed. The influence of the disturbance is reduced.

[0025]

As can be understood from the above description, in the clock signal generating device according to the present invention, the frequency of the PLL circuit is locked by the pulse signal locked by the AFC circuit, and thus the frequency is synchronized with the horizontal synchronizing signal. A clock signal is generated.

That is, since the PLL circuit is always supplied with the synchronizing pulse signal from the AFC circuit and has no free-run state, adjustments such as adjusting the free-run are unnecessary.

Further, since the oscillation of the AFC circuit is made by the ceramic oscillator, the sharpness of resonance is high.

In addition, the generated clock signal is AFC
Since it is synchronized with the circuit, it also has an effect that there is little influence of disturbance before and after vertical synchronization and synchronization disturbance due to noise.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a preferred embodiment of a clock signal generation device according to the present invention.

FIG. 2 is a circuit configuration diagram of a conventional example.

[Explanation of symbols]

 1 Sync Separation Circuit 3,9 Phase Comparator 5,11 Filter 7,13 VCO 15 Frequency Divider

Claims (1)

Claim: What is claimed is: 1. An AFC circuit that locks to a horizontal synchronizing signal by a VCO using a ceramic oscillator, and a PLL circuit that generates a basic clock signal of a device including at least a memory controller. A clock signal generation device, wherein the frequency of the PLL circuit is locked by the pulse signal locked by the AFC circuit, and a clock signal synchronized with the horizontal synchronizing signal is generated.