JPH07123292A - Phase synchronization circuit - Google Patents

Abstract

PURPOSE:To obtain a phase synchronization circuit in which the circuit scale is reduced by adopting the phase synchronization circuit without a frequency divider without frequency division ratio setting depending on an input of a synchronizing signal. CONSTITUTION:A phase comparator circuit 4 compares a synchronizing signal input (a) from an input terminal 1 with a comparison signal (b) from a delay circuit 3 for the phase to provide an output of a phase comparison signal (c). An LPF 5 converts the outputs of the signals c,c' into a DC voltage and it is given to a voltage controlled oscillator 6 and an oscillating output of the voltage controlled oscillator 6 is given to a latch circuit 2, which latches the input synchronizing signal (a) and the latched signal is given to the phase comparator 4 as a comparison signal b' again. The phase difference between the input synchronizing signal (a) and the comparison signal is equivalent to a delay of the delay circuit 3 by varying the frequency from the voltage controlled oscillator 6 so as to reduce the phase difference from the input synchronizing signal (a). As a result, the voltage controlled oscillator 6 generates a clock signal whose phase is synchronously with that of the input synchronizing signal (a).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit used in video equipment and the like.

[0002]

2. Description of the Related Art In a conventional phase locked loop circuit, as shown in FIG. 3, a sync signal input is input to a phase comparison circuit 4, a frequency divider 10 divides the phase by the phase comparison circuit 4, and the pulse signal is input. And phase comparison result is output, and the output is LP
Converted to DC voltage by F5 and voltage controlled oscillator (VCO) 6
To control the oscillation frequency of the voltage-controlled oscillator 6, output the oscillation output of the voltage-controlled oscillator 6 via the output terminal 7, and input the same to the frequency divider 10 to form a loop for synchronization. The oscillation output phase-synchronized with the signal input can be output from the output terminal 7.

[0003]

However, in the conventional phase locked loop circuit, the circuit scale of the frequency divider 10 becomes large, and the frequency division ratio of the frequency divider 10 is changed according to the frequency of the input synchronizing signal. I had to change. An object of the present invention is to eliminate the frequency divider in the phase locked loop circuit and save the trouble of setting the frequency division ratio according to the input of the synchronizing signal to reduce the circuit scale.

[0004]

A phase locked loop circuit of the present invention comprises a latch circuit for latching and outputting an input sync signal,
A signal obtained by delaying the output for a predetermined time is input as a comparison signal, and a phase comparison circuit that compares the phase with the input synchronization signal, and a voltage controlled oscillator that controls the oscillation frequency based on the output from the same phase comparison circuit, And a circuit for inputting an output from the same voltage controlled oscillator as a latch signal of the latch circuit.

[0005]

According to the present invention having the above-mentioned structure, the input synchronizing signal is latched by the latch circuit, the signal delayed for a predetermined period is inputted to the phase comparing circuit as the comparison signal, and the phase comparing circuit compares the phase with the input synchronizing signal. , A loop is configured to control the oscillation frequency of the voltage controlled oscillator based on the phase comparison result, and to input the oscillation output of the voltage controlled oscillator as the latch signal of the latch circuit. It is possible to output a phase-locked oscillation output from the voltage controlled oscillator.

[0006]

1 is a block diagram showing an embodiment of a phase locked loop circuit of the present invention. In the figure, the same parts as those shown in FIG. 3 are designated by the same symbols. A synchronizing signal a separated and extracted from the video signal is input to the input terminal 1, and the input synchronizing signal a is branched through the input terminal 1 so that one is input to the latch circuit 2 and the other is input to the phase comparison circuit. I am typing in 4. The latch circuit 2 latches the input synchronizing signal a by the latch signal input from the voltage controlled oscillator 6, delays it by one synchronizing period, and inputs it to the delay circuit 3.
The delay circuit 3 delays the signal for a predetermined period and inputs it to the phase comparison circuit 4 as a comparison signal b.

The phase comparison circuit 4 compares the phase of the input synchronizing signal a from the input terminal 1 with the comparison signal b from the delay circuit 3 to output a phase comparison result c, and the LPF 5 converts the output into a DC voltage. Then, the oscillation frequency of the voltage controlled oscillator 6 is controlled, the oscillation output of the voltage controlled oscillator 6 is output via the output terminal 7, and the same is input as the latch signal of the latch circuit 2. The loop is configured in this way.

FIG. 2 is a waveform diagram showing the waveform of each part of FIG. 1. An embodiment will be described below with reference to FIG. In the phase comparison circuit 4, the L-level period T1 of the input synchronization signal a
, The phase delay period T2 of the comparison signal b is detected, and the comparison result c is obtained as the period T.
A waveform in which the portion corresponding to the phase delay period T2 in 1 becomes H level and the other portion becomes L level is output. In the portion of the comparison result c other than the period T1, the impedance of the phase comparison circuit 4 changes, so that the H level portion is output at the lowered level.

The comparison result c is converted into a DC voltage by the LPF 5 and input to the voltage controlled oscillator 6, the oscillation frequency of the voltage controlled oscillator 6 is changed, and the oscillation output of the voltage controlled oscillator 6 is used as the latch signal of the latch circuit 2 again. The input synchronizing signal a is latched by the same latch circuit 2 and input to the phase comparing circuit 4 as the comparison signal b ′ via the delay circuit 3. The voltage controlled oscillator 6 is arranged so that the phase difference with the input synchronization signal a is reduced.
Of the comparison signal b '.
Has a smaller phase difference with respect to the input synchronizing signal a, and becomes the phase delay period T3.

The phase comparison circuit 4 compares the phases of the input synchronizing signal a and the comparison signal b ', detects the phase delay period T3 of the comparison signal b', and outputs the comparison result c'as the phase delay period T3 within the period T1. A waveform is output in which the portion corresponding to is at H level and the other portion is at L level. Comparison result c'again
Is input to the voltage-controlled oscillator 6 via the LPF 5 and the oscillation frequency of the voltage-controlled oscillator 6 is changed to reduce the phase difference between the input synchronization signal a and the oscillation frequency of the voltage-controlled oscillator 6. By setting the phase difference between the signal a and the comparison signal to be only the amount delayed by the delay circuit 3, it becomes possible to generate a clock signal whose phase is synchronized with the input synchronization signal a in the voltage controlled oscillator 6. .

Therefore, unlike the conventional example, it is possible to provide a simple phase-locked circuit in which the frequency divider is eliminated, and since the frequency divider is eliminated, the frequency division ratio is changed according to the input of the synchronizing signal. The time and effort can be saved and the circuit scale can be reduced. In order to prevent the oscillation frequency of the voltage controlled oscillator 6 from locking at a frequency different from the input synchronization signal, it is desirable to use a voltage controlled oscillator 6 having a narrow variable range of the oscillation frequency.

[0012]

As described above, according to the present invention,
Since the circuit configuration can be performed by omitting the frequency divider in the phase synchronization circuit, it is possible to save the trouble of setting such that the frequency division ratio is changed according to the input of the synchronization signal, and to provide the phase synchronization circuit having a small circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a phase locked loop circuit of the present invention.

FIG. 2 is a waveform diagram showing a waveform of each part of FIG.

FIG. 3 is a block diagram of a phase locked loop circuit showing a conventional example.

[Explanation of symbols]

 1 Input Terminal 2 Latch Circuit 3 Delay Circuit 4 Phase Comparison Circuit 5 LPF 6 Voltage Controlled Oscillator 7 Output Terminal 10 Frequency Divider

Claims (1)

[Claims] 1. A latch circuit for latching and outputting an input synchronization signal, a phase comparison circuit for inputting a signal obtained by delaying the output as a comparison signal as a comparison signal, and performing phase comparison with the input synchronization signal, and a same phase A phase-locked circuit comprising a voltage-controlled oscillator that controls an oscillation frequency based on an output from a comparison circuit, and a circuit that inputs an output from the voltage-controlled oscillator as a latch signal of the latch circuit.