JPH01106522A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To attain a stable operation at the steady-state by providing a phase comparator section sending each control signal sequentially in the steady-state, a charge pump section operating an analog switch in response to each control signal and generating a control voltage of a voltage controlled oscillator and a delay means giving a prescribed delay to one of the control signals. CONSTITUTION:The phase comparator circuit 121 in the steady-state is operated in a way that each control signal is sent sequentially in response to lead/lag of a phase of an output signal of a voltage controlled oscillator 151 and an input signal and a charge pump section 125 keeps the control voltage at that point of time. Since the operation of the analog switch of the charge pump section 125 has an operation delay to each control signal, at least one control signal has a delay to make the output voltage stable against each control signal sent sequentially. Thus, the status of unstable output voltage due to simultaneous turn-on is avoided.

Description

[Detailed Description of the Invention] [Summary] Regarding phase-locked circuits (PLLs) used in local oscillators (phase-locked oscillators) or demodulation circuits, the control voltage of voltage-controlled oscillators can be controlled without deteriorating phase noise characteristics. The purpose is to enable stable operation in steady state with a phase locked circuit that can be adjusted within a predetermined range.The phase comparator and this output control voltage are input through a loop filter, and the oscillation frequency is controlled accordingly. In a phase synchronized circuit, the output signal of the voltage controlled oscillator is fed back and compared with the input signal in a phase comparator. A phase comparator section is configured to send out control signals according to the lead and lag of the voltage control oscillator, and send out each control signal one after the other in steady state. The device includes a charge pump section that generates a control voltage, and a delay means that provides a predetermined delay to at least one of each control signal.

[Industrial application field]

The present invention provides a local oscillator (
The present invention relates to phase-locked loops (PLLs) used in phase-locked oscillators (phase-locked oscillators) or demodulation circuits.

In particular, in a configuration in which a phase comparator for controlling a wideband voltage controlled oscillator (VCO) includes a charge pump circuit using an analog switch to directly control the control voltage of the voltage controlled oscillator, steady state (phase The present invention relates to a phase-locked circuit having a configuration in which operation is stable in a synchronous lock state.

[Conventional technology]

A phase-locked circuit (PLL) that synchronizes the output signal with the input signal
) uses a phase comparator to compare the phase of the reference signal or input carrier signal and the output signal of the voltage controlled oscillator (VCO), and uses the output as the control voltage of the voltage controlled oscillator (VCO) via a loop filter. It consists of a feedback loop. In a voltage controlled oscillator (VCO), frequency control of an output signal is performed in a direction that reduces a frequency difference and a phase difference between an input signal and an output signal in accordance with this control voltage.

This kind of phase-locked circuit (PLL) can obtain an output signal that is synchronized with the phase of the input signal, so it is possible to reproduce the frequency and phase information contained in the input signal, and it is also useful for demodulating circuits for frequency modulated waves and for carrier waves. It is used in playback circuits, etc.

It is also used as a phase synchronized oscillator that obtains a highly stable oscillation frequency by using a signal extracted from a crystal oscillator with high frequency stability and spectral purity as a reference signal for phase comparison with the output signal.

In addition, in a phase-locked oscillator, a frequency multiplier or frequency divider is configured by dividing or multiplying the output signal of a voltage controlled oscillator (VCO) (extracting the m-th harmonic component) and feeding it back to a phase comparator. be done. .

FIG. 5 is a block diagram showing the configuration of a phase-locked oscillator using a frequency divider.

In the figure, a reference signal (frequency f,) obtained from a crystal oscillator (including a frequency divider) is input to a first input terminal of a phase comparator (PC) 520.

The output of the phase comparator 520 is passed through a loop filter (low pass filter LPF) 531 to a voltage controlled oscillator (VC
O) 551. The output signal (frequency r,) of the voltage controlled oscillator 551 is sent to the output terminal 553 and input to the frequency divider (frequency division ratio N) 555, and the frequency divided signal (frequency f, /N) is used for phase comparison. to the second input terminal of device 520.

With this configuration, the output signal (f,) is the reference signal (
fl), and is controlled to a frequency (Nf, ) that is N times that of the reference signal.

By the way, the voltage controlled oscillator (VCO) used here
551 has a wide band characteristic in which the oscillation frequency f0 varies according to the frequency division ratio N. As shown in FIG.
o(r,,~f,,) is controlled, and the control voltage is VB
The oscillation operation is configured to stop when the value becomes 0 or less.

Now, in the configuration shown in FIG. 5, if the control voltage of the voltage controlled oscillator 551 falls into the oscillation stop region (below VBO), the output signal (ro) disappears and the frequency divider
5 will also disappear, and the frequency divider 555 will operate due to noise. Generally, when a frequency divider operates due to noise, the output signal frequency of the frequency divider becomes high, and the phase comparator 520 performs the same operation as when the oscillation frequency 10 is high, so the oscillation frequency f0 is lowered. Such signals are sent out continuously. That is, the voltage controlled oscillator 5
The control voltage of 51 becomes even lower, permanently VB, ~VB
You will no longer be able to return to the 1st officer range of 2.

Therefore, when using a voltage controlled oscillator (VCO) whose oscillation operation is stopped by the control voltage VB,
It is necessary to limit the range of control voltage.

On the other hand, a digital phase comparator, which is commonly used as a phase comparator, uses the output signal (fo
Alternatively, the phase of the frequency-divided signal f, /N) and the reference signal (f, ) is compared, and the output becomes a high level (for example, 5V) or a low level (for example, OV) depending on the phase difference. .

FIG. 7(a) is a block diagram showing the basic configuration of a digital phase comparator.

FIG. 7(b) is a time chart explaining the operating principle of the digital phase comparator. Note that this time chart is for explaining the operating principle, and is different from the actual operation of the phase comparator.

In FIG. 7, the reference signal (f, ) and the output signal (fo) of the voltage controlled oscillator (VCO) are transmitted to the phase comparator circuit 72.
1, and the control signal φP or control signal φR is sent from the phase comparator circuit 721 to the charge pump circuit 723 depending on the phase state of the output signal with respect to the reference signal. At the output terminal D0 of the charge pump circuit 723, a high level (H) or low level (L) voltage is generated according to the control signals φP and φR, respectively, and the voltage is high impedance at other times indicated by the - dotted chain line. This is the configuration.

Note that the loop filter (Fig. 5, 531) repeats charging or discharging depending on the voltage level and pulse width of the output terminal D0 of the charge pump circuit, and the voltage controlled oscillator (
The control voltage of the VCO) is adjusted. That is, the output end D
When the voltage level of 0 is high level (H), the control voltage of the voltage controlled oscillator increases and the oscillation frequency f0 increases, and when it is low level (L), the control voltage decreases and the oscillation frequency f0 decreases.

A wideband voltage controlled oscillator (V
CO), when such a digital phase comparator is used, as shown in FIG. It is necessary to convert the output of 820 into a control voltage (VB, ~vB,) of voltage controlled oscillator 851. In addition, reference number 821 is a phase comparison circuit,
Reference number 823 is a charge pump circuit, reference number 855
is a frequency divider.

However, a voltage controlled oscillator (VCO) with high modulation sensitivity used in a wideband phase-locked oscillator is easily modulated by noise from an added limiter circuit 841 or a voltage adder circuit 843 using an operational amplifier, etc. There was a problem in that the phase noise characteristics of the

Therefore, by using an analog switch in the charge pump circuit of the phase comparator and adjusting its bias voltage, the output voltage of the phase comparator becomes the control voltage VB, ~VB2 of the voltage controlled oscillator, and these circuits A configuration is adopted that eliminates the need for

FIG. 9 is a block diagram showing the configuration of a phase synchronized oscillator using analog switches in the charge pump circuit of the phase comparator.

In the figure, a charge pump circuit 825 of a phase comparator 820' is composed of analog switches S, . . . S2 using field effect transistors (FETs), to which bias voltages VB, . . . VB2 are applied.

Therefore, when the control signal φP is output from the phase comparator circuit 821, the output terminal D of the charge pump circuit 825
0, and when the control signal φR is output, the control voltage VB appears at the output terminal D0 of the charge pump circuit 825. These control voltages are input to the voltage controlled oscillator 851 via the loop filter 831, and its oscillation frequency 10 is controlled.

[Problem that the invention seeks to solve]

However, in the charge pump circuit 825 using such an analog switch SI+32, the operation of the phase locked loop (PLL) becomes unstable due to the delay time of rising or falling of the analog switches S, S, etc. was there.

This state will be explained below.

FIG. 1θ is a time chart illustrating the operation of the phase comparator in a steady state (phase synchronization lock state).

During normal operation, the phase comparator circuit 821 outputs the control signal φP and the control signal φR one after the other. Therefore, after a predetermined start-up delay, the analog switches S+ and Sz are turned "on" after a time τ1, and also after a time τ,
, respectively, and each becomes "off". That is, time τ1
A bias voltage VB is applied to the output terminal D0 of the charge pump circuit 825.

appears, and at time τ, the bias voltage VB appears.

However, both analog switches S and Sz are turned on.
During the time τ2, the output terminal voltage of the charge pump circuit 825 is not determined (experimentally, approximately VB+). The cause of this is the pulse width of the control signals φP and φR (approximately 20 to 5
One example of this is that the fall delay time (approximately 50 to 200 ns) of the analog switch is longer than that of the analog switch (about 50 to 200 ns).

When the output of the charge pump circuit 825, that is, the control voltage of the voltage controlled oscillator (VCO) becomes unstable, the loop filter, the voltage controlled oscillator (VCO)
The operation of the phase locked loop (PLL) including

The present invention solves these conventional problems,
Voltage controlled oscillator (V
An object of the present invention is to provide a phase-locked circuit that can stabilize the operation during steady state in a phase-locked circuit that can adjust the control voltage of CO) within a predetermined range.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, a phase comparator 120 performs a phase comparison between an input signal at one input terminal and a signal at the other input terminal.

In the voltage controlled oscillator 151, a control voltage outputted from a phase comparator is inputted via a loop filter 131, and the oscillation frequency is controlled accordingly.

The phase locked circuit includes a phase comparator 120, a loop filter 131, and a voltage controlled oscillator 151, and has a configuration in which an output signal of the voltage controlled oscillator 151 is fed back and input to the phase comparator 120.

The phase comparator 121 of the phase comparator 120 constituting the phase locked circuit of the present invention is a voltage controlled oscillator 1 that responds to an input signal.
The charge pump unit 125 sends control signals according to the phase lead or lag of the output signal of the output signal 51, and sends out each control signal one after the other during steady state, and the charge pump section 125 operates the analog switch according to each control signal. The delay means 127 is configured to generate a control voltage that controls the reduction of the phase difference between the input signal and the output signal or the maintenance of a steady state.
This configuration provides a predetermined delay to at least one of No. 3.

It is preferable that the delay means 127 is configured to give a delay to one of the control signals that are sent out one after the other during normal operation to a range in which the analog switches that operate in response to the control signals operate one after the other. .

[For production]

The operation of the phase comparator circuit 121 during steady state is such that each control signal corresponding to the phase lead/lag of the input signal and the output signal of the voltage controlled oscillator 151 is sent out one after the other, and the charge pump section 1
25 operates to maintain the control voltage at that point in time, but since the analog switch of the charge pump section 125 has a delay in operation with respect to each control signal, the output voltage in response to each control signal sent out in succession A delay is applied to at least one control signal for stability.

In other words, by giving a delay to one of the control signals that are sent out one after the other during steady state, to the range in which the analog switches that operate in response to the signal operate one after the other,
This prevents the output voltage from becoming unstable due to being turned on at the same time.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the phase-locked circuit (phase-locked oscillator) of the present invention.

In the figure, the first input terminal of the phase comparator 220 has
The output signal of the crystal oscillator 211 is transmitted to the frequency divider (frequency division ratio M) 21
3 as a reference signal (frequency f,).

The output of the phase comparator 220 is passed through a loop filter (low pass filter LPF) 231 to a voltage controlled oscillator (V
CO) 251 voltage control terminal. The output signal (frequency f,) of the voltage controlled oscillator 251 is output from the output terminal 25.
3 and a variable frequency divider (frequency division ratio N) 255, and the frequency-divided signal (frequency f, 7N) is sent to the second input terminal of the phase comparator 220.

The configuration of the phase comparator 220 is to input a reference signal ("r") and a frequency-divided signal (f, /N), perform a phase comparison, and output a control signal φP or φR according to the frequency difference and phase difference. Phase comparison circuit 221 and its control signals φP, φ
The analog switches (FETs) S, , S, are controlled according to R, and the control voltage V of the voltage controlled oscillator 251 is applied to the output terminal D0.
A charge pump circuit 22 configured to output B, , VB2
5, and one of the control signals φP and φR (in FIG. 2, φ
A feature is that a delay circuit (τ) 227 is inserted to provide a delay to P). Note that the delay circuit 227 can be easily constructed using a known circuit technique using a combination of a capacitor and an inductor or a resistor.

FIG. 3 is a time chart illustrating the normal operation of the embodiment of the present invention.

In the figure, control signal φP is delayed through delay circuit 227 and becomes φP'.

In a steady state where the reference signal (r7) and the frequency-divided signal (f, /N) are synchronized, the control signals φP and φR are output from the phase comparator circuit 221 one after the other, but the delay circuit 227 Since the delay amount τ is given to the control signal φP,
Analog switches St, S of charge pump circuit 225
t can be avoided from turning on at the same time. Therefore, the control voltages VB+, V
Bz is output, and the voltage controlled oscillator 251 operates to maintain this steady state.

Here, the delay amount τ of the delay circuit 227 is the value obtained by subtracting the rising delay amount of the analog switch S2 from the falling delay amount of the analog switch S1, as shown in FIG. Considering the overlap tolerance range, the output end of the charge pump circuit 225 is also assumed to be the delay amount τ shown by the broken line. The control voltage appearing in the control voltage will not become unstable. In other words, the delay amount τ is approximately τ,
If it is within the range of <τ, there will be no particular problem in the operation of the voltage controlled oscillator (operation of the phase-locked circuit).

Note that in a normal phase lag state, the control operation of the voltage controlled oscillator (VCO) according to φP will be delayed according to the delay amount τ, (or τb), but the loop filter 231 and the voltage controlled oscillator There is no substantial problem in the operation of 251.

Furthermore, in this embodiment, a configuration is shown in which a predetermined delay is given to the control signal φP for the phase comparator circuit 221, which outputs the control signal φP following the control signal φR during normal operation. Depending on the operation of the phase comparator circuit 221 that outputs the signals φR one after the other, any control signal may be delayed.

FIG. 4 is a diagram showing another example of the configuration of the charge pump circuit.

Reference numbers and symbols are equivalent to those shown in FIG.

As shown here, even in a configuration using transistors TR, TR2, if the on-off time of the transistor cannot be ignored, the configuration in which one of the control signals φP or φR is delayed by the method of the present invention is effective. be.

〔Effect of the invention〕

As described above, the charge pump section using the analog switch allows the control voltage of the voltage controlled oscillator (VCO) to be adjusted within a predetermined range without deteriorating the phase noise characteristics.

Furthermore, according to the present invention, the control voltage of the voltage controlled oscillator is stabilized by adding a delay to one of the control signals for the operation delay of the analog switch, so that stable operation is achieved both during phase synchronization pull-in and during steady state. A possible phase-locked loop (PLL) is constructed and is extremely useful in practice.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing the configuration of an embodiment of the phase-locked circuit (phase-locked oscillator) of the present invention, and Fig. 3 shows the steady state operation of the embodiment of the present invention. 4 is a diagram showing another configuration example of the charge pump circuit, FIG. 5 is a block diagram showing the configuration of a phase synchronized oscillator using a frequency divider, and FIG. ), Figure 7 is a diagram showing the basic configuration and operating principle of a digital phase comparator, Figure 8 is a block diagram showing the configuration of a conventional phase synchronized oscillator (1), and Figure 9 is a diagram showing the phase FIG. 10 is a block diagram showing the configuration of a phase synchronized oscillator (2) using an analog switch in the charge pump circuit of the comparator. FIG. 10 is a time chart illustrating the operation of the phase comparator in a steady state. In the figure, 120 is a phase comparator, 121 is a phase comparison section, 125 is a charge pump section, 127 is a delay means, 131 is a loop filter, 151 is a voltage controlled oscillator, 211 is a crystal oscillator, 213 is a frequency divider (frequency divider) 220 is a phase comparator, 221 is a phase comparison circuit, 225 is a charge pump circuit, 227 is a delay circuit, 231 is a loop filter (LPF), 251 is a voltage controlled oscillator (VCO), 255 is a variable frequency divider (dividing ratio N), 520 is a phase comparator (PC), 531 is a loop filter (LPF), 551 is a voltage controlled oscillator (VCO), 553 is an output terminal, 555 is a frequency divider (dividing ratio N). be.

Claims (2)

[Claims] (1) A phase comparator (120) that performs a phase comparison between the input signal of one input terminal and the signal of the other input terminal, and a control voltage outputted from this phase comparator (120) is connected to a loop filter (131). ) and a voltage controlled oscillator (151) whose oscillation frequency is controlled accordingly, and the output signal of the voltage controlled oscillator (151) is fed back to the other phase comparator (120). In the phase synchronized circuit configured to send out signals to an input terminal, the phase comparator (120) sends out control signals according to the phase lead/lag of the output signal with respect to the input signal, and in a steady state, each control signal is sent out. A phase comparator (121
) and operate the analog switch according to each control signal,
a charge pump section (125) that generates the control voltage that controls reducing the phase difference between the input signal and the output signal or maintaining a steady state; and a delay means (127) that provides a predetermined delay to at least one of the control signals. A phase-locked circuit characterized by comprising: (2) The delay means (127) is configured to give one of the control signals that are sent out one after another during normal operation a delay within a range in which analog switches that operate in accordance with the control signals operate one after the other. A phase-locked circuit according to claim (1).