JP2921260B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase
Locked Loop) For a frequency synthesizer,
In particular, the present invention relates to a frequency synthesizer that requires quick response for frequency switching. The present invention is used for channel switching of a mobile wireless communication system.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional frequency synthesizer includes a voltage-controlled oscillator 3 capable of outputting a desired frequency signal 2 by a control voltage 1;
And a frequency divider number data signal 5 and a frequency divider number data activation signal 6 generated by the control unit 4, and a variable frequency divider 7 for dividing the frequency signal 2 and outputting the divided frequency signal 2; The reference oscillator 9 to be output and the comparison signal 1 output from the variable frequency divider 7
3, a phase comparator 16 that outputs a pulse signal 15 for charging / discharging the control voltage 1 according to the phase difference so that the phase difference between the two signals coincides with each other. And a low-pass filter 19 for integrating the output 18 of the charge pump circuit 17 and supplying the control voltage 1 to the voltage controlled oscillator 3 for a predetermined time from time t _1. When the output frequency is switched from f ₀ to f ₁ within the time t
_{1 or} earlier to keep sending the dividing number data 5 corresponding to f _1,
Had done channel switching by at time t ₁ sends the frequency division number data activating signal 6.

[0003]

In such a conventional frequency synthesizer, the phase comparator used in the PLL circuit has a remarkable sensitivity when the phase difference between the input reference frequency signal and the comparison signal is small. It often has a dead zone that is low. Therefore, when the switching width of the frequency is narrow, the initial phase difference in the phase comparator occurs only slightly, and the sensitivity of the phase comparator significantly decreases with respect to this phase difference, so that the detection of the phase difference is delayed. There is a disadvantage that the initial response of the switching becomes slow and the switching time becomes extremely long. FIGS. 5 and 6 show the response when the switching width is wide and the response when the switching width is narrow, respectively.

An object of the present invention is to provide a frequency synthesizer which eliminates such a drawback and has means for performing switching in a short time even when the switching width of the output frequency is narrow.

[0005]

SUMMARY OF THE INVENTION The present invention provides a voltage controlled oscillator capable of supplying a control voltage of a predetermined value to a frequency signal of a desired frequency and outputting the frequency signal, and a voltage control oscillator corresponding to the desired frequency to be switched. A control unit for generating a frequency division number data signal having a value and a frequency division number data activation signal for activating the frequency division number data signal; and a frequency signal supplied is activated by the frequency division number data activation signal. A variable frequency divider that divides the frequency according to the divided frequency data signal to generate a comparison signal, a reference oscillator that generates a reference frequency signal,
A frequency synthesizer comprising: a phase comparator that generates a pulse signal; a charge pump circuit that performs charging and discharging with the pulse signal; and a low-pass filter that provides a control voltage obtained by integrating a signal output from the charge pump circuit to the voltage-controlled oscillator. A gate pulse generating circuit for generating a gate pulse signal having a predetermined width in accordance with a frequency division number data activating signal, and a reference frequency signal from the reference oscillator being opened and closed in accordance with the gate pulse signal to generate a reference gate signal The phase comparator includes means for comparing the phase of the comparison signal with the phase of the reference gate signal and continuing to generate the pulse signal until the two phases match. It is characterized by.

[0006]

[Function] When setting the frequency of the frequency synthesizer,
A gate pulse signal is generated from the gate pulse generation circuit using the frequency division number activation signal, the gate circuit is controlled by the gate pulse signal to stop the reference frequency signal for a predetermined time, and thereafter, a switching operation is performed. Thus, even if the switching width of the output frequency is narrow, the switching can be performed in a short time excluding the influence of the sensitivity drop due to the dead zone of the phase comparator.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. In this embodiment, as shown in FIG. 1, a voltage control oscillator 3 capable of supplying a predetermined value of a control voltage 1 to switch to a frequency signal 2 of a desired frequency and outputting the frequency signal 2 and a desired frequency to be switched A control unit 4 for generating a frequency division number data signal 5 having a value corresponding to the above, a frequency division number data activation signal 6 for activating the frequency division number data signal 5, and a frequency division number A variable frequency divider 7 for generating a comparison signal 13 by dividing the frequency in accordance with a frequency division number data signal 5 activated by a data activation signal 6, a reference oscillator 9 for generating a reference frequency signal 8, and a pulse signal Fifteen
, A charge pump circuit 17 for charging and discharging with the pulse signal 15, and a control voltage 1 obtained by integrating a signal 18 output from the charge pump circuit 17.
And a low-pass filter 19 that supplies the voltage-controlled oscillator 3 to the voltage-controlled oscillator 3. 11 and a gate circuit 12 that opens and closes the reference frequency signal 8 from the reference oscillator 9 according to the gate pulse signal 10 to generate a reference gate signal 14. The phase comparator 16 determines the phase of the comparison signal 13 Means for comparing the phase of the gate signal 14 and continuing the generation of the pulse signal 15 over a period until the two phases match.

Next, the operation of this embodiment will be described. FIG.
In this embodiment, a PLL frequency synthesizer is formed by the voltage-controlled oscillator 3, the variable frequency divider 7, the phase comparator 16, the charge pump circuit 17, and the low-pass filter 19, and the control unit 4 generates the PLL frequency synthesizer. The output frequency is switched by making the frequency division number data signal 5 valid by the frequency division number data activation signal 6. As described above, the frequency switching operation is started by the frequency division number data activating signal 6, and this frequency division number data activating signal 6 is also input to the gate pulse generation circuit 11, and has a predetermined width as shown in FIG. Is converted to the gate pulse signal 10. A reference frequency signal 8 as an output of the reference oscillator 9 passes through a gate circuit 12 which is opened and closed by a gate pulse signal 10, and is input to a phase comparator 16 as a reference gate signal 14. While the gate of the gate circuit 12 is closed, the reference gate signal 14 appears to the phase comparator 16 to have a complete phase lag with respect to the comparison signal 13. Therefore, the charge pump circuit 17 performs a charging operation, and the frequency signal 2 immediately responds in the direction of increasing the frequency. After the gate of the reference frequency signal 8 is opened, the operation returns to the normal switching operation. At this time, the output frequency is sufficiently high, and the frequency switching width does not become narrow, and the influence of the dead zone of the phase comparator is suppressed. Can be removed. Figure 3 shows an example of an output response to the gate pulse signal 10 (t ₁ time ~t ₂ is closed gate).

[0009]

As described above, according to the present invention, when setting the frequency, a gate is applied to the reference frequency signal for a predetermined time to forcibly increase the initial phase difference at the time of frequency switching. Since the comparator is used while avoiding the dead zone, there is an effect that the switching can be completed within a short time regardless of the frequency switching width.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a time chart showing signal waveforms of respective parts in FIG. 1;

FIG. 3 is a waveform chart showing an output response in the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a waveform diagram showing an output response in a conventional example (when the switching width is wide).

FIG. 6 is a waveform diagram showing an output response in a conventional example (when the switching width is narrow).

[Explanation of symbols]

 Reference Signs List 3 voltage controlled oscillator 4 control unit 7 variable frequency divider 9 reference oscillator 11 gate pulse generation circuit 12 gate circuit 16 phase comparator 17 charge pump circuit 19 low-pass filter

Claims (1)

(57) [Claims] 1. A voltage controlled oscillator capable of providing a control voltage of a predetermined value to switch to a frequency signal of a desired frequency and outputting the frequency signal, and a frequency division number data signal having a value corresponding to the desired frequency to be switched And a control unit for generating a frequency division number data activation signal for activating the frequency division number data signal, and a given frequency signal according to the frequency division number data signal activated by the frequency division number data activation signal. A variable frequency divider that generates a comparison signal by dividing the frequency, a reference oscillator that generates a reference frequency signal, a phase comparator that generates a pulse signal, a charge pump circuit that performs charging and discharging with a pulse signal, the integrated control voltage output signal of the pump circuit in a frequency synthesizer that includes a low pass filter to provide to the voltage controlled oscillator, the frequency division to the variable frequency divider A gate pulse generating circuit for generating a gate pulse signal of a predetermined width in response to the frequency division number data activation signal when a number activation signal is applied; and closing the gate in response to the gate pulse signal to generate the reference pulse
The reference frequency signal from the shaker is used as the reference gate signal with a phase delay.
A gate circuit to be provided to the phase comparator, wherein the phase comparator compares the phase of the comparison signal with the phase of the reference gate signal and generates a pulse signal over a period until the two phases match. A frequency synthesizer comprising means for continuing.