JP2663537B2 - Frequency synthesizer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a frequency synthesizer used for a high-frequency multi-channel radio, and more particularly to a PLL-type frequency synthesizer characterized by high-speed phase pull-in. It is.

2. Description of the Related Art A frequency synthesizer is an important component of a multi-channel radio, and realization of high-speed frequency pull-in characteristics and further reduction in power consumption of a mobile radio are important issues. A digital phase initialization circuit shown in CS85-21 of the IEICE Communication System Study Group is one of the methods considered for high-speed frequency pull-in characteristics and low power consumption. Hereinafter, a conventional digital type phase initialization circuit will be described with reference to FIG.

In FIG. 6, reference numeral 1 denotes a reference oscillator, the output of which is frequency-divided by a reference frequency divider 2 and input to a phase comparator 3 as a reference signal. 4 is a voltage controlled oscillator (hereinafter referred to as VCO)
Then, the output is frequency-divided by the variable frequency divider 5 and input to the phase comparator 3. The output of the phase comparator 3 is the reference frequency divider 2,
The phase difference component of the output of the variable frequency divider 5 is input to the control terminal of the VCO 4 through the charge pump 6 and the low-pass filter 7 to control the phase difference. By this operation, a stable output synchronized with the reference signal can be obtained from the VCO 4. By changing the frequency division ratio of the variable frequency divider 5, the output frequency of the VCO 4 can be changed, which is used for a multi-channel radio.

In order to reduce the power consumption of the wireless device, it is conceivable to turn off the power when it is not needed, which is generally called an intermittent operation. When the frequency synthesizer described above is operated intermittently, it is necessary to stabilize the frequency in a short time due to the consistency of the system and the effect of the intermittent operation. The following means have been considered to realize these. That is, the control voltage for outputting the required frequency when the power is turned off in the intermittent operation is held by the low-pass filter 7. At this time, it is conceivable that the retained charge fluctuates depending on the state of the charge pump 6. Therefore, the loop switch 8 is inserted between the charge pump 6 and the low-pass filter 7, and the loop switch 8 is opened when the power is turned off. Further, when the power is turned on, a phase difference signal may be generated at the output of the phase comparator 3 because the phase is different even though the frequency is the same, which causes a frequency fluctuation, and it takes time to stabilize the frequency. As a countermeasure against this, a method has been considered in which the reference frequency divider 2 is initialized with the output of the variable frequency divider 5 and the variable frequency divider 5 and the reference frequency divider 2 are in the same phase to form a loop. Reference numeral 9 denotes a control circuit for performing these controls.

Problems to be Solved by the Invention However, in this method, a sufficient in-phase state cannot be obtained, so that there is a problem that it takes a long time to pull in the phase.

SUMMARY OF THE INVENTION The present invention solves the above problems of the prior art, and aims at improving high-speed phase pull-in.

Means for Solving the Problems The present invention relates to a multi-channel radio, wherein a first oscillator for outputting a reference frequency, a first frequency divider for dividing the output of the first oscillator, and an output for a target frequency are provided. A second oscillator that performs variable frequency division on the output of the second oscillator, a phase comparator that compares the phases of the outputs of the first and second frequency dividers, A charge pump that converts an output of the comparator; and an integrator that integrates an output of the charge pump and controls the second oscillator, wherein a charge pump is provided between the first oscillator and the first frequency divider. The first provided in
A second gate circuit provided between the second oscillator and the second frequency divider or in the second frequency divider;
A third gate circuit provided between the charge pump and the integrator connected to the output of the phase comparator, and an output of the first or second frequency divider serving as a clock signal and a reset signal; A fourth input which receives an output of a shift register of 3 bits or more that receives a frequency synthesizer intermittent control signal and a signal indicating a phase advance of the output of the phase comparator.
And a control circuit comprising a fifth gate circuit for inputting an output of the shift register and a signal indicating a phase delay of the output of the phase comparator, wherein the fourth and fifth gate circuits are provided. Are based on the phase comparison of the phase comparator, and the first and second
And the control circuit controls the third gate circuit by a loop control signal that is shorter than the rise of the frequency synthesizer intermittent control signal by a fixed time.

Operation In the present invention, a sufficient in-phase state is created in the intermittent operation mode by the above-described configuration, and the phase is pulled in at a high speed.

FIG. 1 is a configuration diagram of a frequency synthesizer according to an embodiment of the present invention. In FIG. 1, 1 is a reference oscillator,
2 is a reference frequency divider having the output of the reference oscillator 1 as an input, and 4 is
VCO, 5 is a variable frequency divider that receives the output of VCO 4 as input, 3 is a phase comparator that receives the outputs of reference frequency divider 2 and variable frequency divider 5, and 6 is the output of phase comparator 3. , A low-pass filter receiving the output of the charge pump 6 as an input, 8 a loop switch for switching between the charge pump 6 and the low-pass filter 7, 10 and 11 reference oscillators 1 and 2 A gate circuit placed between the VCO 4 and the variable frequency divider 5, the intermittent control signal and the output of the reference frequency divider 2 or the variable frequency divider 5 and the output of the phase comparator 3 as inputs Loop switch 8 and gate circuit 10,1
This is a control circuit that controls 1.

The operation of the above configuration will be described below.
Normal frequency synthesizer operation is the same as in the prior art. In the intermittent operation, gate circuits 10 and 11 for controlling the input of the reference frequency divider 2 and the variable frequency divider 5 by the control circuit 9 which receives the output of the phase comparator 3 and the intermittent control signal as inputs.
Is controlled by the time corresponding to the phase error, and the two inputs of the phase comparator 3 are brought into the in-phase state. Further, the control circuit 9 generates a loop control signal shorter than the rise of the intermittent control signal by a fixed time. The loop switch 8 is directly controlled by the loop control signal. With these operations, the phase is adjusted at the beginning of the intermittent control, a short pull-in time is required, and then the mode of the ordinary frequency synthesizer is set.

FIG. 2 is a configuration diagram of the control circuit 9 in one embodiment of the present invention. In FIG. 2, reference numeral 12 denotes a 3-bit shift register which receives the output of the reference frequency divider 2 or the variable frequency divider 5 as a clock input and receives an intermittent control signal as a reset input.
Is a gate circuit that receives the output of the shift register 12 and the output of the phase comparator 106 as inputs.

The operation of the above configuration will be described below.
The output of the reference frequency divider 2 or the variable frequency divider 5 (the output of the reference frequency divider 2 in this embodiment) is input to the 3-bit shift register 12 as a clock signal.
An intermittent control signal is input as a reset signal. The shift register 12 outputs a loop control signal that is delayed by three periods from the intermittent control signal while the reference frequency divider outputs three pulses in response to the rise of the intermittent control signal. The switch circuit 8 is directly controlled by the loop control signal. That is, the technical significance of the loop control signal is not to close the loop that was opened immediately after the intermittent control signal was turned on, but to set the phase for the period of three cycles of the reference frequency divider output after the intermittent control signal was turned on. Perform phase matching to adjust advance and delay,
Then, by closing the loop with the loop control signal,
It is to realize high-speed frequency acquisition. Also,
A signal representing the phase advance of the phase comparator output is input to the gate circuit 13, and a signal representing the phase delay of the phase comparator output is input to the gate circuit 14. Further, the output of the gate circuit 13 is input to the gate circuit 11, and the output of the gate circuit 14 is input to the gate circuit 10.
To enter. This allows VCO4 if the phase is advanced
Is stopped, and when the phase is delayed, the input of the reference oscillator 1 is stopped to enable phase matching.

3 and 4 are time chart examples showing the temporal relationship of signals in one embodiment of the present invention. FIG. 3 shows a case where the phase is advanced, and FIG. 4 shows a case where the phase is delayed. As shown in the time charts of FIGS. 3 and 4, the gated time is the time of three cycles from the rise of the intermittent control signal to the output of three pulses by the reference frequency divider.
As shown in the figure, when the phase is advanced, the loop control signal and the phase advance signal are gated by the gate 13, and when the phase is delayed, the loop control signal and the phase delay signal are gated by the gate 14 as shown in FIG. I do. In both cases of phase advance and phase delay, the phase adjustment by the gate circuits 13 and 14 is as follows.
It is performed only during the period of three cycles of the reference frequency divider output from the rise of the intermittent control signal to the rise of the loop control signal, and then the loop is closed by the loop control signal. With these operations, the phase is adjusted at the beginning of the intermittent control, a short pull-in time is required, and then the mode of the ordinary frequency synthesizer is set.

FIG. 5 is a configuration diagram of a setting data input section for a main part frequency synthesizer in one embodiment of the present invention. In FIG. 5, 15 is an N-bit shift register, 16 is an N-bit data latch, 17 is a 1-bit data latch, 18 is a gate circuit, and 19, 20, and 21 are clock, data, and strobe input terminals, respectively. is there.

The operation of the above configuration will be described below.
The signal from the data input terminal 20 is input to the N-bit shift register 15 by the signal from the clock input terminal 19,
The data protruding from the N-bit shift register 15 is 1
Input to the bit data latch 17. The signal from the strobe input terminal 21 and the output signal of the 1-bit data latch 17 are controlled by the gate circuit 18, and the N-bit data latch
By inputting to the load terminal 16, the output of the N-bit shift register 15 is input to the N-bit data latch 16. With such an operation structure, a strobe signal having a time difference is synthesized, so that a frequency synthesizer that is resistant to noise can be configured.

As described above, according to the present embodiment, the reference oscillator 1 and the reference frequency divider 2
Gate circuit between VCO4 and variable frequency divider 5
By providing the shift registers 12 and the gate circuits 13 and 14 as the control circuit 9, high-speed phase pull-in can be realized during intermittent operation. Further, a 1-bit data latch 17 and a gate circuit 18 are provided in the data input section, and by combining strobe signals, a frequency synthesizer resistant to noise can be provided at the time of data input.

Effect of the Invention As described above, according to the present invention, a sufficient in-phase state can be created at the time of intermittent operation, and the phase can be pulled in at a high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frequency synthesizer according to an embodiment of the present invention, FIG. 2 is a block diagram of a control circuit which is an essential part of the frequency synthesizer, FIG. 3 is a time chart showing an example of signal phase advance, FIG. FIG. 4 is a time chart showing an example of a phase delay of a signal, FIG. 5 is a block diagram of a data input section which is a main part of the same, and FIG. 6 is a block diagram of a conventional intermittent operation type frequency synthesizer. 1 ... reference oscillator, 2 ... frequency divider, 3 ... phase comparator,
4 voltage-controlled oscillator, 5 frequency divider (variable frequency divider), 6 charge pump, 7 loop filter (low-pass filter, integrator), 8 loop switch, 9 …… Control circuit, 10, 11, 13, 14 …… Gate circuit, 12
... shift register, 15 ... N-bit shift register,
16 ... N-bit data latch, 17 ... 1-bit data latch, 18 ... Gate circuit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-248022 (JP, A) JP-A-62-243423 (JP, A) JP-A-59-133377 (JP, A) 139138 (JP, U)

Claims (2)

(57) [Claims] A first oscillator for outputting a reference frequency; a first frequency divider for dividing an output of the first oscillator; a second oscillator for outputting a target frequency; A second frequency divider for variably dividing the output of the oscillator, a phase comparator for comparing the phases of the outputs of the first and second frequency dividers, and a charge pump for converting the output of the phase comparator; A first gate circuit provided between the first oscillator and a first frequency divider, comprising: an integrator that integrates an output of the charge pump to control the second oscillator; A second gate circuit provided between the second oscillator and the second frequency divider or in the second frequency divider; a second gate circuit connected to an output of the phase comparator; A third gate circuit provided between the first and second frequency dividers serving as a clock signal; A fourth gate circuit for inputting an output of a 3-bit or more shift register which receives a force and a frequency synthesizer intermittent control signal serving as a reset signal, and a signal indicating a phase advance of the phase comparator output; A control circuit comprising a fifth gate circuit for inputting an output of the register and a signal indicating a phase delay of the output of the phase comparator, wherein the fourth and fifth gate circuits are provided with a control circuit of the phase comparator. Based on the phase comparison, the first and second gate circuits are controlled for a time period during which the phase error signal lasts, and the control circuit uses a loop control signal that is shorter than the rising edge of the frequency synthesizer intermittent control signal by a fixed time. A frequency synthesizer for controlling the third gate circuit. 2. A frequency division number setting circuit comprising a shift register and a data latch, wherein a 1-bit data latch output of the shift register or a 1-bit data latch output placed before or after the shift register and a data strobe signal are provided. 2. The frequency synthesizer according to claim 1, wherein said data latch is controlled by a logical product.