JP3250151B2 - Jitter suppression circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator and, more particularly, to a jitter suppressing circuit for suppressing jitter (temporal phase fluctuation) of a clock signal.

[0002]

2. Description of the Related Art Conventionally, as a means for suppressing jitter of a clock signal, an analog phase-periodic loop (PLL) or a digital PLL has been used. Recently, in terms of stability, reliability, ease of LSI (Large Scale Integrated Circuit), etc.,
Generally, a digital PLL is widely used below 30 MHz.

FIG. 4 shows a basic circuit block of a conventional digital PLL. This digital PLL circuit has an input signal 2
9, a binary quantization phase comparator 30, a loop filter 31, a fixed oscillator 35, and a pulse adding / removing circuit 34
And an R frequency divider 33. The fixed oscillator 35, the pulse adding / removing circuit 34, and the R divider 33 are digital V
A CO (voltage controlled oscillator) 32 is configured.

In this digital PLL circuit, the input signal 29 and the output of the R frequency divider 33 are compared in phase by a binary quantization phase comparator 30. That is, as a result of the above-described phase comparison, the binary quantization phase comparator 30 outputs a binary signal such as 0 when the phase is advanced and 1 when the phase is delayed. The result of the quantization is the loop filter 3
1 to the pulse adding / removing circuit 34.

The pulse adding / removing circuit 34 uses a signal output from the loop filter 31 to generate a fixed oscillator 35
This is a circuit for adding / removing a clock pulse output from. Next, the clock signal output from the pulse adding / removing circuit 34 is frequency-divided by the R frequency divider 33 into R signals.
The signal is input to the above-described binary quantization phase comparator 30 and compared with the phase of the input signal 29.

[0006]

However, in the above-mentioned conventional digital PLL circuit, the pulse adding / removing circuit 34 is used.
In some cases, quantization jitter occurs depending on the frequency or time of adding or removing pulses. In order to suppress the quantization jitter, it is necessary to increase the oscillation frequency of the fixed oscillator 35.
Although effective in suppressing high frequency jitter components contained in the input signal 29, there is a problem that the PLL follows low frequency jitter components.

Accordingly, an object of the present invention is to suppress jitter even when the phase fluctuation (jitter) width included in an input signal is larger than a normal value and fluctuates at random, and it is also possible to suppress low frequency jitter. Another object of the present invention is to provide a jitter suppression circuit.

[0008]

In order to solve the above-mentioned problems, a jitter suppressing circuit according to the present invention employs the following characteristic configuration.

(1) Input signal and output signal from frequency divider
A phase comparator for comparing the phase and outputs a phase difference signal, before
Low-pass filtering of the output signal from the phase comparator
To perform digital conversion of the LPF to be output and the output of the LPF side
An A / D converter and a predetermined number of digital signals from the A / D converter;
Signal based on the most frequent digital values of the
An arithmetic unit for outputting a digital signal which is either the arithmetic unit
D / A conversion to convert digital output of these to analog signal
, An output signal from the LPF side, and the D / A converter
A switch for selectively outputting the output signal from the scan
Of the frequency corresponding to one output signal selected by the switch.
VCO for outputting a clock and frequency division of the output of the VCO
The power divider, and after the power is turned on , the switch
Switch selects the output signal from the LPF side,
After establishment, select the output signal from the D / A converter.
Jitter suppression circuit .

(2) between the input signal and the output signal from the frequency divider
A phase comparator for comparing the phase and outputs a phase difference signal, before
Low-pass filtering of the output signal from the phase comparator
To perform digital conversion of the LPF to be output and the output of the LPF side
An A / D converter and a predetermined number of digital signals from the A / D converter;
Signal based on the most frequent digital values of the
An arithmetic unit for outputting a digital signal which is either the arithmetic unit
D / A conversion to convert digital output of these to analog signal
, An output signal from the LPF side, and the D / A converter
A switch for selectively outputting the output signal from the scan
Of the frequency corresponding to one output signal selected by the switch.
VCO for outputting a clock and frequency division of the output of the VCO
And a frequency divider that obtains the phase obtained by the phase comparator.
When the phase error is equal to or more than a predetermined value, the switch
The output signal from the LPF is selected and synchronization is established.
Jitter for later selecting the output signal from the D / A converter
Suppression circuit.

(3) The arithmetic unit is configured to determine a predetermined relative frequency.
The average value of a plurality of digital signals having the above
Output the digital signal obtained based on the averaged value.
(1) or the jitter suppressing circuit according to (2) .

(4) In the arithmetic unit, the digital data obtained this time is
Value deviates from the digital value obtained last time by a predetermined value or more.
When the digital value obtained this time is a predetermined coefficient
(1) or using the digital obtained by multiplying
(2) The jitter suppression circuit .

(5) between the input signal and the output signal from the frequency divider
A first signal obtained by low-pass filtering the phase difference signal
And a digital signal obtained by digitally converting the first signal
A predetermined number of these digital signals have a high relative frequency.
Digital signals obtained based on digital values are converted to analog
Selectively select one of the converted second signals
Provide a switch to output, and select the one selected by this switch.
Output a clock with a frequency corresponding to the
A PLL circuit configured to divide the frequency by the frequency divider;
After the power is turned on, the switch outputs the first signal.
Select the second signal after synchronization is established.
Data suppression circuit .

(6) between the input signal and the output signal from the frequency divider
A first signal obtained by low-pass filtering the phase difference signal
And a digital signal obtained by digitally converting the first signal
A predetermined number of these digital signals have a high relative frequency.
Digital signals obtained based on digital values are converted to analog
Selectively select one of the converted second signals
Provide a switch to output, and select the one selected by this switch.
Output a clock with a frequency corresponding to the
A PLL circuit configured to divide the frequency by the frequency divider;
The phase error obtained by the phase comparator is equal to or greater than a predetermined value
Sometimes, the switch selects the first signal,
Jitter suppression circuit for selecting a second signal after synchronization is established
Road .

[0015]

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a jitter suppression circuit according to the present invention will be described below in detail with reference to the accompanying drawings, particularly, FIG.

FIG. 1 is a block diagram showing a preferred embodiment of a jitter suppression circuit according to the present invention. This jitter suppression circuit has an input terminal 1 and a control terminal 2 to which an input signal and a control signal are applied, respectively. A CPU (central processing unit) 7 is connected to an input terminal 1 via a phase comparator 3, a low-pass filter 4, and an A / D (analog / digital) converter 6.
Is connected.

The output of the CPU 7 is input to one input terminal 11 of an analog switch 9 via a D / A (digital / analog) converter 8, and the output of the low-pass filter 4 is input to the analog switch 9 via a delay circuit 5. It is input to the other input terminal 10. The output of the analog switch 9 is connected to the output terminal 14 via the VCO 12, and outputs an output clock signal. The output of the VCO 12 is
The N-divided output signal 18 is also input to the N divider 13 and fed back to the phase comparator 3.

The control signal from the control terminal 2 is applied to the CPU 7, and the period detection signal 15 from the phase comparator 3 is
Input to U7. The CPU 7 outputs a switching signal 16 of the analog switch 9 and a frequency division number setting signal 17 to the N frequency divider 13.
Occurs.

Next, the operation of the jitter suppression circuit of FIG. 1 will be described. In this jitter suppression circuit, the analog switch 9 is connected to the output terminal 10 of the delay circuit 5 after the power is turned on.
As a result, this jitter suppression circuit operates as an analog PLL circuit. When the PLL enters a synchronous state as an analog PLL circuit, the analog switch 9 is switched to the output terminal 11 of the D / A converter 8 to operate as a digital PLL circuit. However, the switching of the analog switch 9 is performed after a predetermined calculation process required by the CPU 7.

The delay circuit 5 includes an A / D converter 6,
It is provided for adjusting the phase (time) with the digital processing time by the CPU 7 and the D / A converter 8. In other words, the main purpose of the delay circuit 5 is to compensate for the propagation delay of the A / D converter 6 and the D / A converter 8. However, the delay circuit 5 includes the low-pass filter 4 and the VCO 12
It also has a buffer function between them.

First, the analog P of the jitter suppression circuit shown in FIG.
The operation of the LL circuit will be described. An input signal including a jitter component is input to an input signal terminal 1. This input signal and the output signal 18 from the N frequency divider 13 are separated by the phase comparator 3
And compare the phases. The phase error between both signals is smoothed by the low-pass filter 4 and converted into a voltage. This correction voltage is supplied to the output terminal 14 of the VCO 12 via the delay circuit 5.
Generates an output clock signal corresponding to this voltage. As described above, the N frequency divider 13 divides the output clock signal by N and inputs the frequency divided signal to the phase comparator 3 as the N frequency divided signal 18.

After the cycle of the analog PLL circuit is established, the output voltage of the low-pass filter 4 is taken in by the A / D converter 6, converted into a corresponding digital value, and taken into the CPU 7 at the timing of the input signal. This captured value becomes a phase error.

When a predetermined number of digital values, which are the phase errors, become t in the CPU 7, the CPU 7 performs arithmetic processing by a method of creating a histogram (see FIG. 2) described later, and outputs the result to D. / A converter 8. This D / A converter 8 outputs a voltage approximating the output voltage of the low-pass filter 4. After that, CPU7
Sends a switching signal 16 to the analog switch 9, switches the analog switch 9 to the output terminal 11 of the D / A converter 8, and outputs the output voltage of the D / A converter 8 to the VCO 12.
To enter. As a result, a digital PLL circuit is obtained, and a stable output clock signal is obtained from the output terminal 14.

Next, referring to the histogram of FIG.
The operation process of the PU 7 will be described. First, the digital value of the A / D converter 6, which is the phase error, is acquired at the timing of the input signal according to the procedure described above. At this time, an area in which digital values are stored in advance is divided by an appropriate value (class width). Distribute the captured digital values to the appropriate class. The number of data (frequency) in each class is counted.

When the total number of data fetched in this way reaches t, the total number of data already fetched (t)
Of each class (relative frequency) is calculated for each class, the average of the region where the relative frequency is equal to or greater than a predetermined value is calculated, and the value is output from the D / A converter 8.

When outputting the average value to the D / A converter 8, a section (confidence section) in which the relative frequency of the class including the average value output to the D / A converter 8 can be 95% reliable is calculated from the following equation. f ± 1.96√ {f (1-f) / t} where f is the relative frequency and t is the total number of data.

Thereafter, each time the number of digital values taken into the CPU 7 becomes t in total, the relative frequency is obtained by the same procedure, and the relative frequency of the class having the highest relative frequency is determined by the reliability calculated in the previous processing. If it is a section, the average value calculated in the previous processing is held as it is. That is, the CPU 7 keeps outputting the previous average value to the D / A converter 8. If it is out of the confidence interval, the average value of the region where the relative frequency is equal to or more than the specified value is obtained again and compared with the average value calculated in the previous process. If the new average value is within a certain range from the previous average value, the value is output to the D / A converter 8. if,
If it is outside the predetermined range, the correction is made by a predetermined coefficient (for example, ２) and output to the D / A converter 8. Also, the calculated average value is stored for the next processing.

Next, an application example in which the jitter suppression circuit of the present invention shown in FIG. 1 is applied to image signal processing will be described with reference to FIG. In the block diagram of this application example, the same reference numerals are used for the constituent elements corresponding to the jitter suppression circuit of FIG. 1 for convenience.

In the application example to the image signal processing shown in FIG. 3, the phase comparator 3, the low-pass filter 4, the delay circuit 5,
A / D converter 6, CPU 7, D / A converter 8,
The following elements are included in addition to the analog switch 9, the VCO 12, and the N frequency divider 13. That is, an M frequency divider 21, a W frequency divider 22, and a flip-flop (F / F) 23.

The input terminal 19 of the phase comparator 3 has an input H
The S signal is input. The input VS signal is input from the input terminal 20 to the F / F 23. Also, the control terminal 2 has
The control signal is input and input to the CPU 7 together with the input HS signal and the input VS signal. An output clock signal I is output from an output terminal 25 of the VCO 12, and an output clock signal II is output from an output terminal 26 of the M frequency divider 21. Also, W
An output HS signal and an output VS signal are output from output terminals 27 and 28 of the frequency divider 22 and the F / F 23, respectively. This circuit has a function of generating a high-frequency clock signal and reproducing the horizontal / vertical synchronization signal based on the input HS signal and the input VS signal, that is, the input horizontal synchronization signal and the input vertical synchronization signal.

In this circuit, the timing at which the result of the arithmetic processing performed by the CPU 7 is output to the D / A converter 8 is processed flexibly at the following timing. (1) Output at the timing of the input VS signal. (2) Output at the timing of the input VS signal ± (input HS signal × t). (3) Output at random timing.

Further, it can be understood that this circuit can be realized simply and inexpensively, since most of the analog section can be made into one IC or LSI (integrated circuit). Further, the jitter suppression circuit of this application example is configured and operates in the same manner as in FIG. 1, and therefore, detailed description is omitted here.

The configuration and operation of the preferred embodiment and application of the jitter suppression circuit of the present invention have been described in detail. But,
It will be understood that various modifications can be made without departing from the spirit of the invention. For example, in the above description,
The analog switch is an analog PLL only when the power is turned on.
It operated to operate as a circuit. But out of sync,
That is, when the phase error becomes sufficiently large, the analog PLL
It is preferable to switch the analog switch so that
Further, since the analog PLL circuit rises more quickly than the digital PLL circuit, the voltage to the VCO obtained by the analog PLL after the power is turned on is transferred to the digital PLL circuit by the A / D converter 6 so that the digital PLL circuit is turned on.
The circuit can be started up quickly.

[0035]

As will be understood from the above description, according to the jitter suppressing circuit of the present invention, both the analog PLL circuit and the digital PLL circuit are provided. Start up, then digital PL
High reliability and high stability of jitter suppression can be obtained as an L circuit. Further, the correction timing in the case of the digital PLL circuit can flexibly correspond to various timings. Further, the circuit configuration has a practically remarkable effect that it can be realized relatively small and inexpensively using an IC or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram of a preferred embodiment of a jitter suppression circuit according to the present invention.

FIG. 2 is an explanatory diagram of an arithmetic processing process of a CPU of the jitter suppression circuit in FIG. 1;

FIG. 3 is a block diagram of an image signal processing circuit to which the jitter suppression circuit in FIG. 1 is applied.

FIG. 4 is a block diagram of a conventional digital PLL circuit.

[Explanation of symbols]

 Reference Signs List 3 phase comparator 4 low-pass filter 5 delay circuit 6 A / D converter 7 CPU 8 D / A converter 9 switch 12 VCO 13 frequency divider

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-61-265934 (JP, A) JP-A-9-214327 (JP, A) JP-A-2-213223 (JP, A) JP-A 2000-31816 (JP, A) Japanese Utility Model Hei 5-78039 (JP, U) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H03L ^7/ 06-7/22

Claims (6)

(57) [Claims] (1)The phase of the input signal and the output signal from the divider
A phase comparator for comparing and outputting a phase difference signal; Low-pass filtering the output signal from the phase comparator.
LPF to A / D converter for digitally converting the output of the LPF
When, Of a predetermined number of digital signals from the A / D converter,
Digital derived based on relatively frequent digital values
An arithmetic unit for outputting a signal, Converting the digital output from the arithmetic unit into an analog signal
D / A converter, The output signal from the LPF side and the output signal from the D / A converter
A switch for selectively outputting an output signal, A circuit corresponding to one output signal selected by the switch
A VCO that outputs a wave number clock, The frequency divider for dividing the output of the VCO, After the power is turned on, the switch is turned on from the LPF side.
Output signal, and after the synchronization is established, the D / A conversion
The output signal from the converter Characterized by jitter
Suppression circuit. (2)The phase of the input signal and the output signal from the divider
A phase comparator for comparing and outputting a phase difference signal; Low-pass filtering the output signal from the phase comparator.
LPF to A / D converter for digitally converting the output of the LPF
When, Of a predetermined number of digital signals from the A / D converter,
Digital derived based on relatively frequent digital values
An arithmetic unit for outputting a signal, Converting the digital output from the arithmetic unit into an analog signal
D / A converter, The output signal from the LPF side and the output signal from the D / A converter
A switch for selectively outputting an output signal, A circuit corresponding to one output signal selected by the switch
A VCO that outputs a wave number clock, The frequency divider for dividing the output of the VCO, The phase error obtained by the phase comparator is equal to or greater than a predetermined value
In some cases, the switch controls the output signal from the LPF side.
From the D / A converter after synchronization is established
The output signal of Jitter suppression circuit characterized by the following:
Road. 3. The arithmetic unit according to claim 1, wherein the relative frequency is not less than a predetermined relative frequency.
Average of multiple digital signals
Outputting a digital signal obtained based on the average value
The jitter suppression circuit according to claim 1, wherein: 4. The arithmetic unit according to claim 1, wherein the digital value obtained this time is
Is more than a predetermined value from the digital value obtained last time
Multiplying the digital value obtained this time by a predetermined coefficient
Claims characterized by using digital obtained by
3. The jitter suppression circuit according to 1 or 2 . 5. A phase difference between an input signal and an output signal from a frequency divider.
A first signal obtained by low-pass filtering the signal;
A predetermined number of digital signals obtained by digitally converting the first signal are received.
Out of these digital signals
Digital signal obtained based on the value was converted to analog
Selectively outputting either one of the second signal and the second signal
Switch, and select one output selected by this switch.
Output a clock having a frequency corresponding to the input signal, and
A PLL circuit configured to divide by a
After raising, the switch selects the first signal,
Selecting the second signal after synchronization is established;
Jitter suppression circuit. 6. A phase difference between an input signal and an output signal from a frequency divider.
A first signal obtained by low-pass filtering the signal;
A predetermined number of digital signals obtained by digitally converting the first signal are received.
Out of these digital signals
Digital signal obtained based on the value was converted to analog
Selectively outputting either one of the second signal and the second signal
Switch, and select one output selected by this switch.
Output a clock having a frequency corresponding to the input signal, and
A PLL circuit configured to divide the phase by a
When the phase error obtained by the comparator is greater than or equal to a predetermined value
The switch selects the first signal and the synchronization is
Selecting a second signal after the establishment.
Data suppression circuit .