JP2827967B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit including a microcomputer and a PLL.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit having a built-in microcomputer and PLL circuit is disclosed in, for example, Transistor Technology, February, 1994, February 301.
As described on page (Literature 1), the same clock has been supplied from the clock generation circuit to the microcomputer and the phase comparator of the PLL.

Referring to FIG. 3 which shows a conventional semiconductor integrated circuit described in Document 1 as a block, this conventional semiconductor integrated circuit includes a clock CK for driving the entire semiconductor integrated circuit.
, A timing generator 3 for generating a required clock CM of the microcomputer 10 in response to the supply of the clock CK, and a plurality of PLL reference frequencies RF in response to the supply of the clock CK And a plurality of reference frequencies R
A multiplexer 5 for selecting one selection reference frequency FS from F, an amplifier 6 for amplifying an externally supplied VCO signal and outputting an amplified VCO signal VA, and dividing the amplified VCO signal VA by a predetermined dividing ratio. A programmable counter 7 for outputting a frequency-divided signal VD, a phase comparator 8 for comparing the phases of the reference frequency FS and the frequency-divided signal VD to generate a phase difference signal PC, and responding to the supply of the phase difference signal PC. A charge pump circuit 9 for converting the error signal DC and a microcomputer 10 are provided.

Next, the operation of the conventional semiconductor integrated circuit will be described with reference to FIG. 3. First, the clock generation circuit 1 supplies the same clock CK to the timing generator 3 and the reference frequency generation circuit 4 respectively. I do. The reference frequency generation circuit 4 generates a plurality of reference frequencies RF synchronized with the clock CK in response to the supply of the clock CK, and supplies the plurality of reference frequencies RF to the multiplexer 5. The multiplexer 5 selects one of the reference frequencies RF as the selected reference frequency FS and supplies it to one input of the phase comparator 8. On the other hand, the amplifier 6 is a VCO supplied from outside this IC.
The signal VO is amplified and the amplified VCO signal VA is supplied to the program counter 7. The program counter 7 divides the signal VA supplied at a division ratio set by external control (not shown) to generate a divided signal VD, and supplies the divided signal VD to another input of the phase comparator 8. I do. The phase comparator 8 compares the phases of these signals FS and VD, generates a phase difference signal PC which is a difference signal, and supplies it to the charge pump circuit 9. The charge pump circuit 9 converts the signal into a corresponding error signal DC in response to the supply of the phase difference signal PC, and outputs it as a VCO control signal outside the IC.

In this conventional semiconductor integrated circuit, the phase comparison point of the phase comparator 8 when the PLL is locked is a level change point of the selection reference frequency FS. This selection reference frequency F
The S level change point always overlaps the clock CK level change point. Since the clock CK is also supplied to the timing generator 3 for the microcomputer 10, the clock CK also overlaps with the level change point of the clock CM of the microcomputer 10.

[0006] As is well known, in a PLL, the ability to detect the phase difference signal PC is one factor that determines the gain of the PLL. When the microcomputer 10 operates at the timing of this phase comparison, noise naturally occurs in the power supply or the reference voltage line. Then,
The phase difference signal PC contains a noise component, which is taken over by the error voltage CD, and finally has a problem that the lock frequency of the VCO contains a noise component.

FIG. 4 is a time chart showing a timing relationship between the selection reference frequency FS of the input of the phase comparator 8 when the PLL is locked, the frequency-divided signal VD, and the output phase difference signal PC. In FIG. 4 (A) showing the state without the phase error, the phase error tφ1 at the time of locking is very narrow. For example, the time is about 100 ps. On the other hand, in the case (B) showing a state with noise, the reference frequency FS
Assuming that a noise having a time width tn, for example, 50 ps occurs when the level changes, the width of the phase difference signal PC is tφ1 + tn
Thus, in this case, it is 150 ps, which includes an error of 50%. When the VCO frequency is low, the error caused by this noise has little effect because the period is long. However, when the VCO frequency is high, the period becomes short because the period becomes short. It may be impossible to lock the lock.

For example, if the VCO input frequency is 130 MHz,
Assuming that the permissible time of the influence of noise when the period is 7.69 ns is set to 50 ps as described above, that is, up to 0.65% of the VCO frequency period, a VCO frequency higher than this value is used unless the noise generation time of the microcomputer is shortened. It was impossible. Since the noise generation time of the microcomputer is inversely proportional to the processing speed, the reduction is the same as the improvement of the processing speed. For this implementation, the individual transistors must be increased, and the circuit area increases. .

[0009]

In the above-mentioned conventional semiconductor integrated circuit, the timing of the phase comparison of the PLL and the operation timing of the microcomputer coincide with each other.
Noise caused by microcomputer operation interferes with the phase difference signal, increases the width of the phase difference signal at the time of PLL lock, lowers the phase difference detection sensitivity, and increases the phase error. was there.

Further, there is a disadvantage that the upper limit of the operating frequency of the PLL is greatly restricted by the interference of the noise.

An object of the present invention is to provide a semiconductor integrated circuit capable of performing a PLL operation normally even during a microcomputer operation.

[0012]

A semiconductor integrated circuit according to the present invention is formed on a same semiconductor substrate and has a first timing at the same timing.
And a clock generating circuit for generating a second clock signal, a microcomputer operating in response to the supply of the first clock signal, and a reference frequency signal of a PLL circuit in response to the supply of the second clock signal A reference frequency signal generation circuit for generating a reference frequency signal, and a phase comparison circuit for comparing the phase of the reference frequency signal and the controlled frequency signal to generate a phase difference signal for controlling the generation source of the controlled frequency signal In the integrated circuit, the first and second
And a clock delay circuit for delaying one of the clock signals for a predetermined time.

[0013]

FIG. 1 is a block diagram of a first embodiment of the present invention, in which components common to those of FIG. The semiconductor integrated circuit according to the present embodiment has a clock generation circuit 1 common to the conventional one.
, A timing generator 3, a reference frequency generating circuit 4, a multiplexer 5, an amplifier 6, a programmable counter 7, a phase comparator 8, a charge pump circuit 9, and a microcomputer 10; A phase delay circuit 2 is provided which generates a delay clock CP after a predetermined time delay and supplies it to a timing generator 3.

The phase delay circuit 2 includes an analog or digital delay circuit 21 such as a known delay line.

Next, the operation of this embodiment will be described with reference to FIG. 1. The clock generation circuit 1 supplies the same clock CK to the phase delay circuit 2 and the reference frequency generation circuit 4, respectively. Hereinafter, the operations from the reference frequency generation circuit 4 to the charge pump circuit 9 are common to those of the related art, and thus the description thereof will be omitted.

On the other hand, the phase delay circuit 2 delays the clock CK for a predetermined time, for example, 50 ns, and
And supplies this clock CP to the timing generator 3. The timing generator 3 uses the clock C
In response to the supply of P, a clock CM for the microcomputer 10 is generated and supplied to the microcomputer 10.

According to the configuration of this embodiment, the level change point of the reference frequency FS, ie, the phase difference detection point of the phase difference signal PC, and the operating point of the microcomputer 10 do not always overlap. For example, if the clock CK is 9 MHz, the cycle is 111 ns. If the delay value of the phase delay circuit 2 is 50 nsec as described above, the microcomputer 10 always operates with a delay of 50 ns with respect to the phase difference detection point. Is always delayed by 50 ns. Therefore, occurrence of an error due to the interference of the noise can be effectively suppressed.

According to the present invention, the time difference between the operation change point of the microcomputer and the phase difference detection point of the PLL is V
If the noise width generated by the microcomputer is 50 ps, which is a half cycle of the CO input frequency, 20
The VCO input frequency can be increased to just before GHz.

FIG. 2 is a block diagram showing the configuration of a phase delay circuit 2A which characterizes the second embodiment of the present invention. Referring to FIG.
The difference from the first embodiment is that inverters I1 and I2 connected in series are provided instead of the delay circuit 21. The operation is the same as in the first embodiment.

The embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various modifications can be made. For example, instead of inserting the phase delay circuit on the clock generation side of the microcomputer, it is of course applicable that the phase delay circuit is inserted on the PLL reference signal generation side without departing from the gist of the present invention.

[0021]

As described above, the semiconductor integrated circuit of the present invention includes the clock delay circuit for delaying one of the clock signal for the microcomputer and the clock signal for the PLL for a predetermined time. Since the operation change point of the microcomputer deviates from the detection point, interference of noise caused by the operation of the microcomputer with the PLL operation is suppressed, and the characteristics of the PLL can be maintained as in the non-operation of the microcomputer. There is.

Further, since the above-mentioned noise interference can be removed,
This has the effect that the constraint on the upper limit of the operating frequency of the PLL is greatly eased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a block diagram showing a phase delay circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of a conventional semiconductor integrated circuit.

FIG. 4 is a time chart showing an example of an operation in a conventional semiconductor integrated circuit.

[Explanation of symbols]

 Reference Signs List 1 clock generation circuit 2, 2A phase delay circuit 3 timing generator 4 reference frequency generation circuit 5 multiplexer 6 amplifier 7 programmable counter 8 phase comparator 9 charge pump circuit 10 microcomputer

Claims (4)

(57) [Claims] A clock generation circuit formed on the same semiconductor substrate to generate first and second clock signals at the same timing; a microcomputer operating in response to the supply of the first clock signal; A reference frequency signal generating circuit for generating a reference frequency signal of a PLL circuit in response to the supply of a second clock signal; and a source for generating the controlled frequency signal by comparing a phase between the reference frequency signal and the controlled frequency signal A phase comparison circuit for generating a phase difference signal for control according to (1), further comprising: a clock delay circuit for delaying one of the first and second clock signals for a predetermined time. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein said clock delay circuit includes said time delay line. 3. The semiconductor integrated circuit according to claim 1, wherein said clock delay circuit includes at least one inverter circuit connected in series so as to obtain said time delay. 4. The semiconductor integrated circuit according to claim 1, wherein said clock delay circuit delays said first clock signal by said time and supplies said first clock signal to said microcomputer.