JP2806661B2 - Double loop type PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital transmission, and more particularly to a double loop type PLL circuit.

[0002]

2. Description of the Related Art A conventional double-loop PLL circuit includes, for example, an input disconnection detection circuit 101 for monitoring the input state of an input clock and an N-division circuit for dividing the input clock by N as shown in FIG. Circuit 102 and VCXO oscillation circuit 11
MN dividing circuit 1 for dividing the output of 0 by M · N (M is an integer)
11, a pulse output from the MN frequency dividing circuit 111 and N
A first phase comparison circuit 103 and a second phase comparison circuit 10 for comparing the phases of the pulses output from the frequency dividing circuit 102
4 and a first low-pass filter 105 and a second low-pass filter 1 for smoothing the outputs of the first phase comparison circuit 103 and the second phase comparison circuit 104, respectively.
06 and a coupling circuit 107 that couples the outputs of the first low-pass filter 105 and the second low-pass filter 106
And the output of the coupling circuit 107 and the reference voltage generation circuit 10
8 which is selected by the output of the input disconnection detection circuit 101, and a VCXO oscillation circuit 110 which changes the oscillation frequency by the output of the switch circuit 109.
And

In the conventional example shown in FIG. 4, when the input clock is not interrupted, a pulse obtained by dividing the input clock by N and VC
The phase of the pulse obtained by dividing the output of the XO oscillation circuit 110 by M · N is compared, and based on the result, the oscillation frequency of the VCXO oscillation circuit 110 is controlled (M is an integer, and the frequency to be compared is set to be the same) When the input clock is cut off, the output of the reference voltage generating circuit
The transmission frequency of the XO oscillation circuit 110 is controlled. And
Switch circuit 1 performed at clock loss and clock recovery
The switching operation of 09 is performed immediately.

[0004]

On the other hand, in this conventional double loop type PLL circuit, the input clock is cut off and the VC
While the input of the XO oscillation circuit 110 is being supplied from the reference voltage generation circuit 108, the output of the coupling circuit 107 is at the power supply voltage level or the ground level. For this reason,
The clock is restored again from the input clock disconnection state, and VCX
When the input of the O-oscillation circuit 110 is switched to be supplied from the output of the coupling circuit 107, if the switching speed is high, the output level of the VCXO oscillation circuit 110 is not restored because the output level of the coupling circuit 107 is not restored to a steady state. The inconvenience that the frequency jumps has occurred.

[0005]

An object of the present invention is to improve the disadvantages of the prior art, and in particular, to improve the VC generated when the input clock is restored.
It is an object of the present invention to provide a double-loop PLL circuit which effectively eliminates a jump phenomenon of an oscillation frequency of an XO oscillation circuit, thereby effectively suppressing occurrence of a communication failure.
With that purpose.

[0006]

According to the present invention, a VCXO oscillating circuit for changing a transmission frequency as required is provided.
An MN divider for dividing the output of the CXO oscillation circuit by MN, an N divider for dividing an externally input clock by N, and an output pulse of each of the N divider and the MN divider. A phase difference smoothing output circuit of two systems connected in parallel for comparing the phase and then smoothing the output, a coupling circuit for coupling the outputs of the respective phase difference smoothing output circuits, and a reference provided separately from the output of the coupling circuit A switch circuit for selecting one of the outputs of the voltage generation circuit and regulating the operation of the VCXO oscillation circuit; and an input disconnection detection circuit for controlling the selection operation of the switch circuit in accordance with the input state of a clock input from the outside. And a double loop type PLL circuit having the following. Then, a configuration is adopted in which a delay circuit is provided between the above-described switch circuit and the input disconnection detection circuit. This aims to achieve the above-mentioned object.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. The embodiment shown in FIGS. 1 to 3 has a VCXO oscillating circuit 10 that changes the oscillation frequency as required, and outputs the output of the VCXO oscillating circuit M · N
After comparing the phases of the output pulses of the MN divider circuit 11, the N divider circuit 2 for dividing the clock inputted from the outside by N, and the output pulses of the N divider circuit 2 and the MN divider circuit 11, Two phase difference smoothing output circuits 30 and 40 connected in parallel for smoothing the output, and each phase difference smoothing output circuit 3
A switch for selecting one of a coupling circuit 7 for coupling the outputs 0 and 40 and an output of a reference voltage generating circuit 8 provided separately from the output of the coupling circuit 7 and regulating the operation of the VCXO oscillation circuit 10. The circuit includes a circuit 9 and an input disconnection detection circuit 1 that controls a selection operation of the switch circuit 9 according to an input state of a clock input from the outside. Further, a delay circuit 12 is provided between the switch circuit 9 and the input disconnection detection circuit 1. The delay circuit 12 has a limited delay function that operates effectively when the output of the switch circuit 9 is switched from the output side of the reference voltage generation circuit 8 to the coupling circuit 7 side. One embodiment of the circuit configuration of the delay circuit 12 is shown in FIG. In FIG. 2, shift register 20
1 delays the output of the input disconnection detection circuit 1 for a fixed time.
The shift clock of the shift register 201 is VCXO
A frequency-divided output of the oscillation circuit 10 or a clock of another system is used.

FIG. 3 shows waveforms at various parts in FIG. 2. The output A of the input disconnection detecting circuit 1 is delayed by the shift register 201 like the output B. Output A and output B are AND circuit 2
The logical product is obtained by 02 and becomes an output C (if the logic of the output A is opposite, the AND circuit 202 becomes an OR circuit). The delay circuit 12 is configured to generate a delay only when the output of the switch circuit 9 is switched from the reference voltage generation circuit 8 to the coupling circuit 7.

As described above, since the switching is performed after a delay time until the output level of the coupling circuit 7 recovers to the steady state, the clock is recovered again from the input clock cutoff state and the input of the VCXO oscillation circuit 10 is changed. Coupling circuit 7
Can be prevented from jumping the output frequency of the VCXO oscillation circuit 10 when switching from the output of the VCXO oscillation circuit.

[0010]

As described above, according to the present invention, it is possible to prevent the oscillation frequency of the VCXO oscillation circuit from jumping when the input clock is restored, and to further reduce the output clock of the double loop type PLL circuit to the data system. When used in the above processing, it is possible to provide an unprecedented superior double-loop PLL circuit capable of performing good communication without causing a communication failure such as a data error when the input clock is cut off for a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a detailed block diagram showing a detailed example of a delay circuit in the block diagram of FIG. 1;

FIG. 3 is a timing chart showing the operation of each unit in FIG.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input disconnection detection circuit 2 N dividing circuit 3 first phase comparison circuit 4 second phase comparison circuit 5 first low-pass filter 6 second low-pass filter 7 coupling circuit 8 reference voltage generation circuit 9 switch circuit 10 VCXO oscillation Circuit 11 MN frequency divider

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-48-34407 (JP, A) JP-A-59-4330 (JP, A) JP-A-3-143022 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H03L 7/00-7/14

Claims (2)

(57) [Claims] 1. A V for changing a transmission frequency as required.
The CXO oscillation circuit and the output of this VCXO oscillation circuit
An MN dividing circuit for dividing N, an N dividing circuit for dividing an externally input clock by N, this N dividing circuit and the M
Two phase difference smoothing output circuits connected in parallel for comparing the phase of each output pulse of the N frequency dividing circuit and then smoothing the output; a coupling circuit for coupling the output of each phase difference smoothing output circuit; And the output of a reference voltage generating circuit provided separately from the output of the VCX.
A double-loop PLL circuit comprising: a switch circuit that regulates the operation of the O oscillation circuit; and an input disconnection detection circuit that controls a selection operation of the switch circuit according to an input state of a clock input from outside. A double loop PLL circuit comprising a delay circuit between a switch circuit and an input disconnection detection circuit. 2. The delay circuit according to claim 1, wherein the delay circuit has a limited delay function that operates effectively when switching the output of the switch circuit from the output side of the reference voltage generation circuit to the coupling circuit side. Double loop type PL according to 1.
L circuit.