JP3368971B2 - Frequency synchronization device and clock signal regeneration device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a phase locked loop (PL).
The present invention relates to an L) type frequency synchronizing device and a clock reproducing device using the same, and more particularly to a clock reproducing device for reproducing a clock signal from a non-return zero (NRZ) data signal.

[0002]

2. Description of the Related Art In recent years, in data communication utilizing optical communication or the like, data is often transmitted in a non-return-zero (NRZ) system in order to improve data transmission efficiency. In order to reproduce the data signal transmitted by the NRZ method on the receiving side, the receiving side needs a clock signal that is synchronized with the change of the data signal. Therefore, a clock signal reproducing device for reproducing a clock signal from the received data signal is provided on the receiving side, and the data signal is reproduced according to the reproduced clock signal.

An example of a conventional clock signal reproducing device is shown in FIG.
16 and FIG. The clock signal reproducing device of FIG.
A clock signal is reproduced by using a filter having a high Q value. (1) shows a circuit configuration and (2) shows a time chart of the operation. As shown in the figure, the clock signal regenerator of (1) of FIG. 15 delays the data signal by the T / 2 delay line 151 and the T / 2 delay line 151 that delay the data signal by a half cycle of the clock signal which is known in advance. An EXOR gate 152 that takes an exclusive OR of the original data signal and the original data signal, a filter 153 that passes only a signal having a high Q value near the frequency of the clock signal, and an amplifier 154 that amplifies its output, The phase adjustment unit 155 that changes the phase of the clock signal output from the amplifier 154 is included.
The operation of this clock signal reproducing device will be described with reference to FIG.

It is assumed that the data signal and the basic clock signal included in the data signal are as illustrated. Since the data signal delayed by the T / 2 delay line 151 becomes a signal as shown at the node a, a signal obtained by removing a part of the clock signal as shown is obtained as the output of the EXOR gate 152. Since the filter 153 has a high Q value, when such a signal is input, it outputs an oscillation signal having the frequency of the clock signal. However, since the phase of this signal does not match the phase of the original clock signal, the phase adjusting unit 155
Change the phase so that it matches the phase of the original clock signal.
The adjustment of the delay amount in the phase adjusting unit 155 is usually performed by changing the wiring length.

Although the clock signal reproducing apparatus of FIG. 15 has a simple structure, it is possible to reproduce a signal in a very narrow frequency range within the pass frequency of the filter 153, and a filter is used for clock signals having different frequencies. It needs to be changed, and there is a problem that the usable frequency is fixed.
In addition, the delay amount of the phase adjusting unit 155 needs to be determined for each device, and the wiring length needs to be adjusted in the manufacturing process, which complicates the manufacturing process and makes it difficult to form an IC. .

In data communication, it is required that a clock signal in a wider frequency range can be reproduced, and the clock signal reproducing device of FIG. 15 cannot meet the demand. Therefore, a clock signal reproducing device using a PLL circuit shown in FIG. 16 has been proposed. In the clock signal reproducing device of FIG. 16, reference numeral 161 is a voltage controlled oscillator (VCO), 163 is a low-pass filter, 164
Is a phase frequency comparator (PFD), 165 is a PFD charge pump, 166 is a phase comparator (PD), and 167 is P.
D charge pump, 168 is a 1/2 frequency divider, and 169 is a phase error detector (lock detector). In this clock signal reproducing device, the VCO 161, the low-pass filter 163, the PFD 164, and the PFD charge pump 165 constitute a first loop, and the VCO 161
The low-pass filter 163, the PD 166, and the PD charge pump 167 form a second loop. The first loop compares the phases of the reference clock signal fr and the clock signal output from the VCO 161 with the PFD 164 and compares the PFD charge pump 165 and the low-pass filter 16 with each other.
3 is a loop for synchronizing the clock signal output from the VCO 161 with the reference clock signal fr to make the frequencies match by feeding back to the VCO 161 via 3. The second loop compares the phase of the signal obtained by dividing the clock signal output from the VCO 161 with the ½ frequency divider 168 and the phase of the data signal with the PD 166, and through the PD charge pump 167 and the low-pass filter 163. VCO1
This is a loop for synchronizing the clock signal output from the VCO 161 with the basic clock signal of the data signal by feeding back to 61.

After making the second loop inoperative, the clock signal output from the VCO 161 is sufficiently synchronized with the reference clock signal fr in the first loop. When the frequency of the clock signal and the frequency of the reference clock signal fr substantially match each other, the PFD 164 is put into the non-operating state and the PD 166 is put into the operating state, so that the first loop is brought into the non-operating state.
The second loop is switched to the operating state and the clock signal output from the VCO 161 is synchronized with the data signal. As a result, the clock signal required for data reproduction is reproduced. If the frequency or phase of the data signal changes, the VCO 161
When the clock signal and the data signal output from the device are no longer synchronized, the lock detector 169 detects this and switches the second loop to the non-operating state and the first loop to the operating state, and again the frequency of the clock signal is used as a reference. Clock signal fr
Then, the first loop is switched to the second loop to synchronize with the data signal.

When the clock signal is reproduced from the NRZ data signal by the PLL circuit, it is necessary to match both the frequency and the phase, but it is difficult to directly match the both. Therefore, as in the device of FIG. In the loop, the frequency of the reproduced clock signal is first drawn to the frequency of the reference clock signal fr and then to the second loop so that the phase of the reproduced clock signal matches the phase of the data signal.

[0009]

However, as is apparent from the above description, in the clock signal reproducing apparatus of FIG. 16, the lock detector switches the PFD and PD between the operating state and the non-operating state, Although the first loop and the second loop are switched, there is a problem that it takes time from being switched to the second loop to being pulled in because of the phase offset between the PFD and the PD.
In addition, because it is no longer synchronized with the data signal,
Even when the loop is switched to the above-mentioned loop, it takes time until the phase overshoot occurs and it is pulled to the frequency of the reference clock signal fr. That is, when the synchronization with the data signal is lost, it takes time to synchronize again. If there is such a problem, it takes time until the data can be received, and the communication efficiency decreases.

The present invention has been made in view of the above problems, and is to improve the responsiveness in a clock signal reproducing device for reproducing a clock signal from a data signal and the frequency of the clock signal used in such a device. It is an object of the present invention to realize a frequency synchronizer for synchronizing in advance with the frequency of the reference clock signal.

[0011]

FIG. 1 is a principle block diagram of a frequency synchronizer of the present invention, (1) shows a basic configuration,
(2) shows the feedback characteristic in this device.
In Figure 1, reference numeral 1 is a voltage controlled oscillator capable of changing the oscillation <br/> frequency according to the voltage applied, 2 oscillation signal output of the voltage controlled oscillator 1 and the first reference signal fr Is a low-pass filter that removes high frequency components from the output signal of the reference phase detection means 2. The oscillation signal output from the voltage controlled oscillator 1 is synchronized with the first reference signal fr by feeding back the output of the low pass filter 3 to the voltage controlled oscillator 1. The feedback system of this frequency synchronizer uses the first reference signal fr and the voltage control.
The oscillation signals output from the oscillator 1 are compared, and the comparison result is the voltage.
A first feedback system input to the controlled oscillator;
The reference signal fr and the oscillation signal output from the voltage controlled oscillator 1 are
The comparison is performed, and the comparison result is input to the voltage controlled oscillator.
2 feedback system, and the first feedback
And the second feedback system have substantially the same gain.
Having and feedback direction is opposite
It is characterized by This frequency synchronizer's feedback
When the phase error is zero due to the above configuration,
Oscillation of the voltage controlled oscillator 1 within a predetermined phase error range including
Do not change the frequency. Furthermore, in other ranges, voltage
The oscillation frequency of the controlled oscillator 1 is the frequency of the first reference signal fr.
To have a characteristic that works in the direction of matching with.

[0012]

The feedback system of the frequency synchronizer of the present invention has a feedback characteristic as shown in (2) of FIG. As shown in the figure, in the range of the arrow including the portion where the phase error is zero, the output voltage of the low-pass filter 3, that is, the feedback voltage to the VCO 1 does not change the oscillation frequency regardless of the phase error. This range is, for example, −π
To + π. When the frequencies of the two clock signals match and only the phases differ, the phase error is constant and the oscillation frequency of the VCO 1 does not change because it always falls within the range of the arrow. However, when the frequencies are different, even if the phases match at the initial stage, the phase error gradually expands, and when the frequency exceeds the range of the arrow, feedback is applied, so that the frequencies match.

An apparatus for reproducing a clock signal in synchronization with a second reference signal whose frequency may differ from the first reference signal fr within a certain range and whose phase is also indefinite is a frequency synchronizing apparatus of the present invention. If the output signal of the VCO 1 or its frequency-divided signal and the phase difference between the second reference signal are detected to form a second loop for feeding back to the VCO 1, the output signal of the VCO 1 is always the first reference signal fr.
Since the feedback is performed so as to match the frequency of, the problem with switching that occurs in the conventional clock signal reproducing device of FIG. 16 does not occur.

[0014]

FIG. 2 is a diagram showing the overall configuration of a frequency synchronizer according to a first embodiment of the present invention. In FIG. 2, reference numeral 1
Reference numeral 1 is a VCO, 21 is a digital phase frequency detector (PFD), and 22 is a PFD.
A PFD charge pump that converts the output of 21 into a charge / discharge signal for the low-pass filter 31, 23 is a digital phase detector (PD: Phase Detector), and 24 is a PD 23.
Is a charge pump for converting the output of the above into a charge / discharge signal for the low-pass filter 31, and 31 is a low-pass filter. The low pass filter 31 is composed of a resistance and a capacitance element as shown in the figure.

FIG. 3 is a diagram showing a circuit configuration of the PFD 21 and the PFD charge pump 22, and FIG. 4 is a time chart showing the operation thereof. The PFD in FIG. 3 is a normal PLL.
In the circuit, it may be simply called a phase comparator, but here, a phase frequency comparator (PFD) and a phase comparator (PFD) are used.
It is distinguished from D). The PFD of FIG. 3 is widely known,
Although detailed description is omitted here, U or D is determined depending on whether the S input leads or lags the R input in phase.
A positive or negative signal appears at. D if the phase is advanced
The pulse is output to U. If the phase is delayed, the pulse is output to U, and the pulse width changes according to the amount of advance of the phase. However, since the circuit of FIG. 3 is a sequential circuit,
The states of the terminals U and D are not uniquely determined only by the levels of the input terminals R and S, but are influenced by the previous states. The U pulse is inverted by the inverter and then applied to the gate of the P-channel transistor of the charge pump 24 to make the P-channel transistor conductive. As a result, the output terminal is charged through the resistor from the power supply terminal on the high potential side only during the pulse width period. The D pulse is applied to the gate of the N-channel transistor of the charge pump 24 to make the N-channel transistor conductive. As a result, discharge is performed from the output terminal to the power supply terminal on the low potential side through the resistor only during the pulse width period. That is, the low-pass filter 31 is charged and discharged according to the phase difference,
It is fed back to the VCO 11 and controlled so that the phase difference becomes zero. Here, the reference signal f is used as the R input.
Since r is input and the clock signal output from the VCO 1 is input as the S input, when the phase of the clock signal output from the VCO 1 is ahead of the reference signal fr, a pulse is output to D and discharge is performed. Is delayed, a pulse is output to U and charging is performed.

FIG. 5 shows the PD 23 and the PD charge pump 2.
4 is a diagram showing a circuit configuration of No. 4, and FIG. 6 is a time chart showing its operation. In the circuit of FIG. 5, the R input signal is frequency-divided by the 1/2 frequency divider 231 and then input to the exclusive OR (EXOR) gate 234. The signal of the S input is inverted by the inverter gate 232, frequency-divided by the 1/2 frequency divider 233, and input to the EXOR gate 234. As shown in FIG. 6, the output of the EXOR gate 234 has the same period in the high level state and the low level state when the phases match, and the S input signal leads the R input signal in phase. When the phase is delayed, the proportion of the low-level state becomes large, and when the phase is delayed, the proportion of the high-level state becomes large. The output of the EXOR gate 234 is applied to the gates of the P-channel transistor and the N-channel transistor that form the CMOS inverter gate. As a result, when the output of the EXOR gate 234 is at a low level, the P-channel transistor is turned on and the output terminal is charged from the power supply terminal on the high potential side through the resistor for that period, and the output of the EXOR gate 234 becomes high. In the level state, the N-channel transistor becomes conductive, and during that period, discharging is performed from the output terminal to the power supply terminal on the low potential side through the resistor. That is, the low-pass filter 31 is charged and discharged according to the phase difference, and is fed back to the VCO 11 and controlled so that the phase difference becomes zero. This circuit is also a sequential circuit, and the state of the output is affected by the state immediately before. In this case as well, the reference signal fr is input as the R input and the clock signal output by the VCO 1 is input as the S input. Therefore, when the phase of the clock signal output by the VCO 1 leads the reference signal fr, the conduction of the P-channel transistor is turned on. The rate of charging increases and charging is performed. The phase of the clock signal is the reference signal f
When it is delayed from r, the rate of conduction of the N-channel transistor increases, and discharge is performed.

Here, the first feedback system of the PFD 21 and the PFD charge pump 22, the PD 23 and the PF.
In the second feedback system of the D charge pump 24, it is important that the feedback direction with respect to the phase error is opposite. The gain of the two systems is from -π to +
π is set to be equal in the range. This will be described later.

FIG. 7 is a diagram showing a circuit configuration of the VCO 11. The VCO 11 in FIG. 7 is an oscillation circuit composed of MES transistors, and oscillates by repeating charging and discharging of the capacitive element while the two MES transistors are alternately conducting, but the MES transistor between the power supply terminal on the low potential side By changing the gate voltage Vc of, the time constant of charging / discharging the capacitive element changes and the oscillation frequency changes. Here, if the voltage Vc is increased, the oscillation frequency is also increased, and if the voltage Vc is decreased, the oscillation frequency is also decreased.

The above is a description of each element of the frequency synchronizing apparatus according to the first embodiment of FIG. 2, and the feedback system of the entire apparatus will be described with reference to FIG. FIG. 8 is a diagram of phase error output characteristics showing the relationship between the phase error in the feedback system of the entire apparatus and the output voltage of the low-pass filter 31, that is, the voltage applied to the VCO 11.

In FIG. 8, the alternate long and short dash line indicates PFD21 and PFD21.
The phase error output characteristic of the first feedback system of the FD charge pump 22 is shown, and the chain double-dashed line shows the phase error output characteristic of the second feedback system of the PD 23 and the PD charge pump 24. As described above, since the gains of the two feedback systems are equal and the feedback directions are opposite, as shown in FIG.
When 2 and the output of the PD charge pump 24 are connected and input to the low-pass filter 31, the combined phase error output characteristic is as shown by the solid line. That is, -π to + π
Within the phase error range of, the outputs of the two feedback systems cancel each other out, and the output voltage of the low-pass filter is kept constant even if there is a phase error. Also, −
Outside the range of π to + π, the output voltage of the low-pass filter changes according to the phase error, but the output voltage of the low-pass filter does not change beyond the central level when the phase is advanced or delayed.

By having such a phase error output characteristic, when the frequencies of the two clock signals are slightly different and the phase difference is gradually increased, feedback is performed so that the frequencies of the two clock signals match. Works, but if the two clock signals have the same frequency,
Since the phase difference does not expand below −π or above + π, feedback does not work even if there is a phase difference.

The above is the description of the frequency synchronizer of the first embodiment, but an embodiment of the clock regenerator for regenerating a clock signal from a data signal using such a frequency synchronizer will be described below. FIG. 9 is a diagram showing the configuration of the clock recovery device of the second embodiment. In FIG. 9, reference numeral 91 is a VCO, 93 is a low pass filter, and 921 is a PF.
D, 922 is a PFD charge pump, 923 is a PD,
Reference numeral 924 denotes a PD charge pump, which are the same as the elements of the frequency synchronizer of FIG. The clock regenerator of this embodiment further includes a data signal phase detector (PD).
94 and a data signal charge pump 95.

FIG. 10 is a diagram showing the circuits of the data signal PD 94 and the data signal charge pump 95. As is clear from comparison between FIG. 5 and FIG. 10, the circuit of FIG. 10 is similar to the circuit of FIG. 5, except that the 1/2 divider 231 is not provided. This circuit compares the clock signal and the data signal output from the VCO 91, and since the data signal is the NRZ signal, the basic period of the data signal is equal to the period obtained by dividing the clock signal in half. Therefore, it is not necessary to divide the frequency of the data signal input as the R input, and the 1/2 frequency divider 231 is omitted.

Further, in the circuit of FIG. 10, the EXOR gate 9
Although 43 is used, an exclusive NOR (EXNOR) gate may be used instead. In any case, in the circuit of FIG. 9, the clock signal output from the VCO 91 is the PFD 921 and the PFD charge pump 922.
, A PD 923, a PD charge pump 924, and a low-pass filter 93 are constantly controlled to match the frequency of the reference signal fr by a frequency synchronizer, and the data signal PD 94 and the data signal charge pump are also controlled. A loop constituted by 95 and the low-pass filter 93 controls the frequency and the phase of the original clock signal of the data signal so that they match. This solves the problem in the conventional clock signal reproducing device shown in FIG. 16 that it takes time from switching to pulling in.

FIG. 11 is a block diagram showing the structure of the clock signal reproducing apparatus of the third embodiment. The present embodiment is an example in which the present invention is applied to a frequency synthesizer (synthesizer).
In FIG. 11, reference numeral 111 is a VCO, 113 is a low-pass filter, 1121 is a PFD, 1122 is a PFD.
Charge pump, 1123 PD, 1124 PD charge pump, 117 data signal phase detector (P
D) and 118 are data signal charge pumps 95,
These are the same as the respective elements of the second embodiment of FIG. In the present embodiment, further, a 2-module prescaler 114 for dividing the clock signal output from the VCO 111,
The swallow counter 115 and the programmable counter 11
6 and 6.

Since the PFD 1121 has a relatively long response time, it is difficult to directly detect the phase difference between the reference signal and the clock signal when the clock signal output from the VCO 111 has a very high frequency. Therefore, the clock signal is divided by the division ratio N and the reference signal is also divided by 1 / N. The portion configured by the two-module prescaler 114, the swallow counter 115, and the programmable counter 116 is a portion for dividing the clock signal with a division ratio of an arbitrary integer N.

FIG. 12 shows a 2-modulus prescaler (2-
It is a figure which shows the circuit structure of Modulous Prescaler) 114. This circuit divides the frequency into 1 / P or 1 / (P + 1) (P is an arbitrary integer). 1 / P and 1 / (P + 1)
Which of the two is to be divided is selected by the signal applied to the mode selection terminal. In the configuration of FIG. 11, the swallow counter 115 outputs the output of the 2-modulus prescaler 114
(A is an arbitrary integer) The 2-modulus prescaler 114 divides the frequency by (P + 1) until counting is completed. Therefore, A (P + 1) is counted during this period. Thereafter, the 2 modular prescaler 114 performs P frequency division until the programmable counter 116 counts the output of the 2 modulus prescaler 114 by (MA). Therefore, (MA) P is counted during this period. Therefore, as a whole, the number N counted during this period is as follows.

N = A (P + 1) + (MA) P = MP + A Therefore, N can be arbitrarily set by appropriately determining P, A, and M. In the operation of the third embodiment shown in FIG. 11, the reference signal is divided by 1 / N and the VCO 11
The operation is the same as that of the second embodiment except that the output of is divided by 1 / N.

FIG. 13 is a diagram showing the structure of the clock signal reproducing apparatus of the fourth embodiment. In FIG. 13, the first VCO
131, the first low-pass filter 133, the first PFD 13
21, first PFD charge pump 1322, first PD
1323, a first portion including a first PD charge pump 1324, a second VCO 151, a second low pass filter 136, a second PFD 1351, a second PFD charge pump 1352, a second PD 1353, and a second portion.
The second portion composed of the PD charge pump 1354 has the same configuration as that of the frequency synchronizer shown in FIG. 2, respectively, except that the first VCO 131 and the second VCO 151 operate complementarily in accordance with the data signal. different. 1st V
The clock signals output from the CO 131 and the second VCO 151 are combined by the OR gate 137, and the phase difference between the combined clock signal and the reference signal fr is detected by the third PD 138. The error signal detected by the third PD 138 is the third P
The low-pass filter 1 of the first portion via the D charge pump A139 and the third PD charge pump B140.
It is fed back to the low pass filter 136 of 33 and the second part. The third PD 138 is the first PD and the second P.
It has the same configuration as D.

In the clock signal reproducing apparatus of FIG. 13, the first
And the second part are the first VCO 131 and the second VCO, respectively.
Since the CO 151 operates complementarily according to the data signal, the operating state and the non-operation state are complementarily repeated according to the data signal. Moreover, since the change from the non-operating state to the operating state is synchronized with the change of the data signal, the first
The phase of the clock signal output from the VCO 131 and the second VCO 151 matches the phase of the data signal. Moreover, since each part has the same configuration as the frequency synchronizer of FIG. 2, the frequency of the clock signal output from the first VCO 131 and the second VCO 151 matches the frequency of the reference signal fr, and the output of the first VCO 131 and the second VCO 151. If the clock signals to be generated are combined by the OR gate 137,
A clock signal having the same phase as the data signal having the same frequency as the reference signal can be obtained.

The phase difference between the composite clock signal thus obtained and the reference signal fr is detected by the third PD 138,
When feedback is made to the first portion and the second portion via the third PD charge pump A139 and the third PD charge pump B139, the combined clock signal and the reference signal f
The first VCO 131 and the second VCO 13 depending on the phase difference of r.
The oscillation frequency of 4 will be changed. As apparent from the above description, since the phase of the combined clock signal surely matches the change of the data signal, by applying such feedback, the first VCO 131 and the second VC
The oscillation frequency of O134 is controlled so as to match the basic clock signal of the data signal. Therefore, finally, the clock signal synchronized with the basic clock signal of the data signal is reproduced.

FIG. 14 is a diagram showing the structure of the clock signal reproducing apparatus of the fifth embodiment. In FIG. 14, the VCO 14
1, low-pass filter 143, PFD 1421, PFD
The charge pump 1422, the PD 1423, the PD charge pump 1424, the data signal PD 144, and the data signal first charge pump 145 correspond to the respective elements in FIG. 9 and have the same configurations. 9 is different from FIG. 9 in that a reference VCO 146 that generates a reference signal is provided outside the device, and the phase error detected by the data signal PD 144 is fed back to the reference VCO 146 via the data signal second charge pump 147 and the low pass filter 148. Is what you are doing.

In the embodiments described so far, including the second embodiment shown in FIG. 9, the reference signal fr is output from an oscillator using a crystal oscillator or the like, and continuously oscillates at a constant frequency. It was a signal. The oscillation frequency of the reference signal fr is selected close to the frequency of the basic clock signal of the data signal, but since it does not completely match, even if the oscillation frequency of the VCO is matched with the reference signal fr in the frequency synchronizer. In addition to matching the phases based on the result of phase comparison with the data signal, it is necessary to slightly change the frequencies so as to match. Therefore, in the actual feedback control, the oscillation frequency of the VCO is set to the reference signal fr.
In this case, two feedback controls are performed to try to match with the frequency of the basic clock signal of the data signal and extremely complicated control is performed.

On the other hand, in the fifth embodiment, VCO1
After controlling the clock signal of 41 to be equal to the frequency of the reference signal fr output from the reference VCO 146,
The reference VCO 146 is controlled to match the frequency and phase of the basic clock signal of the data signal. However, since feedback according to the phase difference between the clock signal of the VCO 141 and the data signal is performed to the reference VCO 146, the reference VCO 146
The oscillation frequency itself is controlled so as to match the frequency of the basic clock signal of the data signal. As a result, the reference signal fr generated by the reference VCO 146 and the VCO
The clock signals generated by 141 are both synchronized with the basic clock signal of the data signal.

[0035]

As described above, by using the frequency synchronizing device of the present invention, the response of the clock signal reproducing device for reproducing the basic clock signal from the NRZ data signal can be improved, thereby improving the communication efficiency. Can be improved.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a frequency synchronization device of the present invention.

FIG. 2 is an overall configuration diagram of a frequency synchronizer of a first embodiment.

FIG. 3 is a circuit diagram of a phase frequency comparator (PFD) and its charge pump.

FIG. 4 is a diagram illustrating operations of the PFD and the charge pump of FIG.

FIG. 5 is a circuit diagram of a phase comparator (PD) and its charge pump.

FIG. 6 is a diagram illustrating operations of the PD and the charge pump of FIG.

FIG. 7 is a circuit diagram of a voltage controlled oscillator (VCO).

FIG. 8 is a graph showing a phase error output characteristic of the frequency synchronizer of the first embodiment.

FIG. 9 is a configuration diagram of a clock signal reproducing device according to a second embodiment.

FIG. 10 is a circuit diagram of a data signal PD and its charge pump.

FIG. 11 is a configuration diagram of a clock signal reproducing device according to a third embodiment.

FIG. 12 is a circuit diagram of a two-module prescaler.

FIG. 13 is a configuration diagram of a clock signal reproducing device according to a fourth embodiment.

FIG. 14 is a configuration diagram of a clock signal reproducing device of a fifth embodiment.

FIG. 15 is a diagram showing a first example of a conventional clock signal reproduction device.

FIG. 16 is a diagram showing a second example of a conventional clock signal reproduction device.

[Explanation of symbols]

1 ... Voltage controlled oscillator (VCO) 2 ... Reference phase detecting means 3 ... Low-pass filter

Claims (15)

(57) [Claims] And 1. A voltage controlled oscillator capable of changing the oscillation frequency in accordance with a voltage applied, the phase difference by comparing the oscillation signal and the first reference signal to output of the voltage controlled oscillator and the reference phase detection <br/> means to output a response signal, and a low pass filter for removing high frequency components from the output signal of the reference phase detection hand stage, the voltage controls the output of the low pass filter by full <br/> fed back to the oscillator, a frequency synchronization apparatus for synchronizing an oscillation signal to output <br/> force of said voltage controlled oscillator to said first reference signal, the first reference signal And the oscillation output from the voltage controlled oscillator
The signals are compared, and the comparison result is input to the voltage controlled oscillator.
First feedback system, oscillation generated by the first reference signal and the voltage controlled oscillator
The signals are compared, and the comparison result is input to the voltage controlled oscillator.
And a second feedback system , wherein the first feedback system and the second feedback system are provided.
Have almost the same gain and feedback
A frequency synchronizer characterized in that the directions of are opposite . 2. The reference phase detection means includes a phase frequency comparator that compares the first reference signal with an oscillation signal output from the voltage controlled oscillator, and an output of the phase frequency comparator is applied to the low pass filter. a first phase comparing means that consists in a PFD charge pump which converts the discharge signal, the phase comparator the first reference signal and comparing the output oscillating signal of the voltage controlled oscillator, the output of the phase comparator frequency synchronization apparatus according to the second phase comparator means that will be composed of a PD charge pump which converts the charge and discharge signal to the low pass filter, to claim 1, characterized in that it comprises a. 3. A frequency dividing means for dividing the oscillation signal output from the voltage controlled oscillator into 1 / N (a positive integer other than N: 1), wherein the oscillation frequency of the first reference signal is the voltage control. 3. The frequency synchronizer according to claim 1, wherein the frequency is 1 / N of the oscillation frequency of the oscillator. 4. A compares the voltage controlled oscillator capable of changing the oscillation frequency, the oscillation signal output from the first reference signal and <br/> the voltage controlled oscillator in accordance with a voltage applied and the reference phase detection means for outputting a signal corresponding to the phase difference Te, and a low pass filter for removing high frequency components from the output signal of the reference phase detection means, a predetermined phase including the case where the phase error is zero without changing the oscillation <br/> frequency of the voltage controlled oscillator in the error range, the direction in other ranges to match the oscillation frequency of the voltage controlled <br/> oscillator to the frequency of the first reference signal wherein the frequency synchronization apparatus of the output of the low pass filter is fed back to the voltage controlled oscillator, the oscillation signal or position by comparing the frequency-divided signal and the second reference signal to output of the voltage controlled oscillator to serve in Output signal according to phase difference And a second reference phase detector that, the second reference phase detector
By the output of the vessel to enter the low-pass filter is fed back to the voltage controlled oscillator, a frequency for the first reference signal synchronized the voltage controlled oscillator the <br/> said second reference clock reproducing apparatus according to claim further be synchronized for the signal. Wherein said second reference signal is a serial transmission data signal, a clock reproducing apparatus according to claim 4, the output of the voltage controlled oscillator is characterized in that it is a reproduction clock signal. 6. The first phase comparison means, wherein the reference phase detection means compares the first reference signal with an oscillation signal output from the voltage controlled oscillator and converts the comparison signal into a charge / discharge signal for the low-pass filter. and a second phase comparing means for converting the charge and discharge signal to the low pass filter compares the oscillation signal output of the voltage controlled oscillator with a first reference signal, the second phase comparator and said first phase comparing means A means according to claim 4 or 5, characterized in that the means have substantially the same gain and are substantially subtracted when their outputs are combined.
Clock reproduction device . 7. The first phase comparing means compares a phase frequency comparator that compares the first reference signal with an oscillation signal output from the voltage controlled oscillator, and outputs the output of the phase frequency comparator to the low pass filter. And a phase comparator for comparing the oscillation signal output from the voltage controlled oscillator with the first reference signal, and the phase comparator. 7. The clock regenerator according to claim 6, further comprising: a PD charge pump that converts the output of the above into a charge / discharge signal for the low-pass filter.
Place 8. A frequency dividing means for dividing an oscillation signal output from the voltage controlled oscillator into 1 / n (a positive integer other than n: 1), wherein the oscillation frequency of the first reference signal is the voltage control. 8. The clock regenerator according to claim 4, wherein the frequency is 1 / n of the oscillation frequency of the oscillator. 9. The circuit for generating the first reference signal is a reference voltage controlled oscillator capable of changing an oscillation frequency according to an applied voltage, and an output of the second reference phase detector is the reference voltage control oscillator. 9. The clock regenerator according to claim 4, wherein the clock regenerator is applied to a voltage controlled oscillator. 10. The clock regenerator according to claim 9, wherein each element except the reference voltage controlled oscillator is formed on one chip, and the reference voltage controlled oscillator is provided outside the chip. 11. A voltage-controlled oscillator capable of changing the oscillation frequency in accordance with a voltage applied, the first reference signal
And the reference phase detection means for outputting a signal corresponding to the phase difference by comparing the output oscillating signal of the voltage controlled oscillator and a low-pass filter for removing high frequency components from the output signal of the reference phase detection means comprising, calling of the voltage controlled oscillator at a predetermined phase error range including a case where the phase error is zero
Without changing the oscillation frequency, the output of the low pass filter as in the other ranges acts in a direction to match the oscillation frequency of the voltage controlled oscillator to the frequency of the first reference signal to said voltage controlled oscillator comprising a plurality of frequency synchronization apparatus for feedback, the voltage controlled oscillator and the second reference signal
Clock reproducing apparatus characterized by operate complementarily in accordance with. 12. continuous clock signal synthesis hand for generating a clock signal synthesized continuously outputs of the voltage controlled oscillator
Characterized in that it comprises a stage, and a phase detecting means for outputting a signal corresponding to the phase difference by comparing the composite clock signal and a first reference signal output from the continuous clock signals synthesized hand stage to said low-pass filter The clock recovery device according to claim 11. 13. A voltage control oscillator capable of changing an oscillation frequency according to an applied voltage, and a first reference signal and an oscillation signal output from the voltage control oscillator are compared to generate a signal corresponding to a phase difference. A reference phase detecting means for outputting, and a low pass filter for removing a high frequency component from the output signal of the reference phase detecting means, by feeding back the output of the low pass filter to the voltage controlled oscillator, A frequency synchronizer for synchronizing an output oscillation signal with the first reference signal, comprising: a first phase comparison means for comparing the first reference signal with the oscillation signal output from the voltage controlled oscillator; ratio
The output of the comparing means is output to the low-pass filter .
A feedback system; and a second phase comparison means for comparing the first reference signal with the oscillation signal output from the voltage controlled oscillator .
The second output of the comparing means is output to the low-pass filter
A feedback system, wherein the first feedback system and the second feedback system have substantially the same gain, and the feedback directions are opposite to each other. 14. The frequency synchronization according to claim 13, wherein when the outputs of the first phase comparison means and the second phase comparison means are combined, the outputs are substantially subtracted. apparatus. 15. The first feedback system and the second feedback system.
The feedback system configured by the feedback system does not change the oscillation frequency of the voltage controlled oscillator within a predetermined phase error range including the case where the phase difference is zero, and the oscillation of the voltage controlled oscillator within the other range. 15. A characteristic that acts in a direction in which the frequency is made to match the frequency of the first reference signal.
The frequency synchronizer according to any one of 1.