JPH09307432A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit which can suppress the phase shift and the disturbance of an output clock caused by the phase difference between subsidiary clocks. SOLUTION: One of two subsidiary clocks CLK0 and CLK1 is selected by a selection circuit 11 and inputted to a phase comparator 13 after undergoing M-division via an M-division circuit 12. This divided subsidiary clock is compared in terms of phase with the clock that is obtained by applying N-division to an output clock CLKout produced by a VCO (voltage control oscillator) 15 via an N-division circuit 16. Then the phase difference signal obtained through the phase comparison is converted into a control voltage signal of the VCO 15 by an LPF 14. A selection control part 17 controls the selection switching of the circuit 11 with the changing timing of one of both clocks CLK0 and CLK1 that is newly selected according to a switch signal S1. At the same time, the part 17 controls at least one of both division phases of circuits 12 and 16 synchronously with the output changing point of the comparator 13. Thus, it's possible to suppress the phase shift and the disturbance of an output clock caused by the phase difference between both subsidiary clocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit that generates an output clock in synchronization with a dependent clock, and is particularly used in a transmission device having a redundant clock dependent configuration.
The present invention relates to a technique for performing timing control when switching a subordinate clock.

[0002]

2. Description of the Related Art Conventionally, in a PLL circuit used in a transmission device having a redundant clock dependent configuration, when switching the dependent clock, the clock switching timing is controlled by a new clock to be a dependent system and the phase is controlled. It is common to employ a method of suppressing the waveform distortion such as whisker superposition caused by switching between different redundant clocks as much as possible and suppressing the disturbance of the clock system.

FIG. 4 shows an example of a conventional PLL circuit according to the dependent clock switching system. In FIG. 4, CLK0 is 0
System dependent clock, CLK1 is a 1-system dependent clock,
These subordinate clocks CLK0 and CLK1 are selected by the selection circuit 1
One of them is selected by, the frequency is divided by M in the M (M is a natural number of 2 or more) frequency dividing circuit 2, and then input to the phase comparator 3.

In this phase comparator 3, the output clock CLKout of the VCO (voltage controlled oscillator) 5 is divided by N (N is a natural number of 2 or more) by the frequency dividing circuit 6 and M by the M frequency dividing circuit 2. It detects the phase difference between the frequency-divided dependent clock and the phase-dependent signal, and the phase difference signal is L
It is input to a PF (low pass filter) 4.

The LPF 4 cuts the high frequency components of the input phase difference signal and extracts the low frequency components to generate a voltage control signal for the VCO 5. VC
O5 controls the frequency according to the level of the input voltage control signal to generate the output clock CLKout synchronized with the dependent clock from the selection circuit 1.

On the other hand, the selection control unit 7 has a switching signal S1,0.
A system control clock CLK0 and a system control clock CLK1 generate switching control signals to the selection circuit 1. That is,
When the switching signal S1 is input to the selection control unit 7, the selection control unit 7 synchronizes with the timing of the change point of the newly selected clock of the 0-system dependent clock CLK0 and the 1-system dependent clock CLK1. The switching control signal is output to the selection circuit 1.

By the above control, waveform distortion due to superimposition of whiskers on the output clock waveform or the like can be suppressed as much as possible in the selection circuit 1 to switch the dependent clocks.

However, in the PLL circuit based on the conventional dependent clock switching method as described above, in a system in which the phases of the dependent clocks forming the dependent redundant configuration are independently defined, unnecessary clocks accompanying the switching are provided. The suppression effect can be expected for the disturbance of the output clock due to the waveform distortion, but the suppression effect cannot be expected for the phase transition or the disturbance of the output clock depending on the phase difference between the subordinate clocks.

On the other hand, as an example of the conventional method, Japanese Patent Laid-Open No.
Japanese Patent No. 262619 (hereinafter referred to as "prior art")
A PLL circuit which prevents the worst phase state between the two clocks to the PLL when the LL switches from the free-running state to the dependent state of the input clock and prevents a significant frequency jump of the output clock for the device. The configuration of is described.

In the PLL circuit described in this prior art, the transmission path clock input by the first frequency dividing circuit is divided to generate two kinds of divided clocks having different phases, while the second dividing circuit is used. The frequency divider divides the output clock for the device, and the phase comparator compares the two types of frequency-divided clocks output from the first frequency-divided circuit and the frequency-divided clock output from the second frequency-divided circuit. Compare the phases.

Here, regarding the transmission path clock, the presence / absence of input is monitored by the clock break detection circuit, and two types of divided clocks output from the first frequency dividing circuit are input to the selector, and one of them is input. Either one is selected in response to the information output from the clock loss detection circuit and the phase comparison circuit.

At this time, in the phase-locked loop, when the transmission line clock is input, the frequency of the output clock is responsive to the frequency-divided clock selected and output by the selector and the frequency-divided output of the second frequency-dividing circuit. To the transmission line clock,
Also, when the input of the transmission line clock is cut off, it is made to run by itself.

However, even in the configuration disclosed in the above-mentioned prior art, since the phase adjustment is not performed at the time of switching the selection of the divided clock of the selector, the disturbance of the output clock due to the unnecessary distortion of the clock waveform due to the switching is prevented. It cannot be suppressed.

[0014]

As described above, in the conventional PLL circuit based on the dependent clock switching method, in the case of a system in which the phases of the clocks forming the dependent redundant configuration are independently defined, the dependent clocks are There is a problem that it is not possible to deal with the phase transition and the disturbance of the output clock depending on the phase difference between them.

An object of the present invention is to solve the above problems and to provide a PLL circuit capable of suppressing the phase transition and the disturbance of the output clock depending on the phase difference between the dependent clocks.

[0016]

In order to solve the above problems, a PLL circuit according to the present invention uses a clock generating means for generating a clock having a frequency according to a control signal, and an output clock of the clock generating means for N clocks. (N is an arbitrary natural number of 2 or more), a N dividing circuit for dividing, a selection circuit for inputting a plurality of dependent clocks and selectively outputting any of the dependent clocks, and an output clock of the selection circuit. M divider circuit for dividing M (M is an arbitrary natural number of 2 or more) and this M divider circuit
A phase comparator for phase-comparing the output clock of the frequency dividing circuit and the output clock of the N frequency dividing circuit, and a high frequency component of the output of the phase comparator are removed to thereby generate a frequency control signal of the clock generating means. The selection switching of the selection circuit is controlled at a change timing of a clock that is newly selected from among the plurality of dependent clocks in accordance with the filter unit that is generated and the switching signal for selecting the dependent clock, and the phase comparator A selection control unit for controlling a frequency division phase for at least one of the M frequency dividing circuit and the N frequency dividing circuit is provided so as to be synchronized with the change point of the output.

That is, in the PLL circuit having the above-mentioned configuration, when the plurality of dependent clocks having the redundant configuration are selected and switched, the switching is performed at the changing point of the selected clock and the phase control is performed on the input of the phase comparator. This will solve this problem.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of a PLL circuit according to the present invention. One of the dependent clocks CLK0 and CLK1 is selected by a selection circuit 11, and the M frequency dividing circuit 12 is selected.
It is divided by M and input to the phase comparator 13. The phase comparator 13 outputs a clock obtained by dividing the output clock CLKout from the VCO 15 by N by the N divider 16 and the M divider 1
Phase comparison with the dependent clock divided by N by 2
Output to PF16.

The LPF 16 cuts the high frequency components of the input signal to generate a voltage control signal, and the VCO 15
Output to The VCO 15 controls the oscillation frequency according to the level of the input voltage control signal, and outputs the output clock CLK.
Generate out.

The selection controller 17 controls the 0-system dependent clock CL.
K0, the 1-system dependent clock CLK1, the switching signal S1 from the outside, and the output of the phase comparator 13 are input, and the M divider circuit 1
A control signal to the 2 / N frequency dividing circuit 16 and the selecting circuit 11 is generated.

The operation of the above configuration will be described below.

First, when the switching signal S1 is input to the selection control unit 17, the selection control unit 17 causes the 0-system dependent clock CLK.
The phase difference between the 0 and 1 system dependent clocks CLK1 is monitored, and in synchronization with the change point of the output of the phase comparator 13, the M divider circuit 1
The frequency division phase is controlled for 2 or N frequency dividing circuit 16 or both, and a switching control signal to the selection circuit 11 is output.

The M dividing circuit 12 or the N dividing circuit 16,
The frequency division phase control executed for both or both is 0
It depends on the phase difference between the system dependent clock CLK0 and the 1-system dependent clock CLK1 and absorbs the phase difference so that the output waveform of the phase comparator 13 does not change when the dependent clock is switched.

2 and 3 show time charts in the configuration of the above embodiment.

2A and 3A show the waveform of the 0-system dependent clock CLK0, and FIG. 2B and FIG. 3B show 1 waveforms.
The waveform of the system dependent clock CLK1 is shown. In this embodiment, the 0-system dependent clock CLK0 to the 1-system dependent clock C
The subordinate clock switching to LK1 will be described as an example. still,
2 (c) and 3 (c) show output waveforms of the M frequency dividing circuit 4, and M = 2 in this example.

2 (d) and 3 (d) show output waveforms of the VCO 15, and FIGS. 2 (e) and 3 (e) show N divider circuit 1.
6 is an output waveform of No. 6. In this example N = 4. FIG.
(F) and FIG. 3 (f) show the output waveform of the phase comparator 13, and t1 in FIG. 2 and t2 in FIG. 3 show the switching timing of the selection circuit 11. In this example, when the output waveform of the phase comparator 13 changes at the falling edge (the 0-system dependent clock CLK before switching)
The change timing is when the rising edge of 0 changes.

FIG. 2 shows the 0-system dependent clock CL of FIG. 2 (a).
2 shows the case where the phase of the 1-system dependent clock CLK1 of FIG. 2B leads K0 by the phase difference of A in the figure.
In the case of this figure, in the clock switching, the selection control unit 17
Performs the phase control (advancing the phase) with the same phase difference amount as the phase difference A in the figure for the N divider circuit 16 (dotted line part in FIG. 2E).

Similarly, in FIG. 3, in contrast to the 0-system dependent clock CLK0 of FIG. 3A, the 1-system dependent clock C of FIG. 3B is used.
The case where the phase of LK1 is delayed by the phase difference of B in the figure is shown. In the case of this figure, in clock switching, the selection control unit 17 performs phase control (delays the phase) of the same amount of phase difference as the phase difference of B in the figure for the N frequency dividing circuit 16 (FIG. 3).
(Dotted line part of (e)).

As a result of the above, the distortion of the output waveform of the phase comparator 13 shown in FIG. 2 (f) and FIG. 3 (f) is suppressed, and the disturbance of the clock output from the VCO 15 (frequency fluctuation). Can be suppressed and the dependent clock can be switched to the 1-system dependent clock CLK1.

[0031]

As described above, according to the present invention, in the dependent clock switching control, the phase difference between the dependent clocks is monitored, and the frequency division phase control is executed in the clock switching control. It is possible to provide a PLL circuit that can suppress the phase fluctuation of the output clock and the disturbance of the clock system as much as possible even at the time of switching.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a time chart for explaining the operation of the same embodiment.

FIG. 3 is a time chart for explaining the operation of the same embodiment.

FIG. 4 is a block circuit diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 1, 11 Selection circuit 2, 12 M frequency divider circuit 3, 13 Phase comparator 4, 14 LPF 5, 15 VCO 6, 16 N frequency divider circuit 7, 17 Selection control unit

Claims (3)

[Claims] 1. A clock generating means for generating a clock having a frequency according to a control signal, and an N dividing circuit for dividing an output clock of the clock generating means by N (N is an arbitrary natural number of 2 or more). A selection circuit for inputting each of the dependent clocks and selectively outputting any of the dependent clocks, and an M divider circuit for dividing the output clock of the selection circuit by M (M is an arbitrary natural number of 2 or more), A phase comparator for phase-comparing the output clock of the M frequency dividing circuit and the output clock of the N frequency dividing circuit, and a frequency control signal of the clock generating means by removing high frequency components from the output of the phase comparator. And a switching means for selectively switching the selection circuit at a change timing of a clock that is newly selected from among the plurality of dependent clocks according to a switching signal for selecting the dependent clocks. While controlling, in synchronization with the change point of the output of the phase comparator,
A PLL circuit, comprising: a selection control unit that controls a frequency division phase for at least one of the M frequency divider circuit and the N frequency divider circuit. 2. The plurality of dependent clocks are clocks generated independently of each other.
The PLL circuit as described in the above. 3. The clock generation means comprises a voltage controlled oscillator, and the filter means removes a high frequency component from the output of the phase comparator and converts it into a DC voltage signal to control the voltage of the voltage controlled oscillator. The PLL circuit according to claim 1, wherein the PLL circuit is configured by a low-pass filter that generates a signal.