JP2000244311A - Clock changeover adjustment method and its circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock changeover adjustment circuit that suppresses phase fluctuation in a selected clock signal so as to allow a PLL circuit to stably follow the phase of the selected clock signal. SOLUTION: One of the clock input systems of this circuit is provided with an inverting circuit 17 that inverts a 1/2 frequency clock signal 16 resulting from applying 1/2 frequency division to a clock signal 1 by a frequency divider 11 to provide an output of a 1/2 frequency inverted clock signal 16', a selector 12 that selects either of the signals 16, 16' and outputs the selected signal according to a prescribed switch control signal 18, and a phase difference detecting changeover control circuit consisting of a phase comparator 13, a CR integration device 14, and a comparator 15 that detects the phase difference between a selected clock signal 5 selected at present by a clock signal selection circuit 40 and the signal 16 outputted from the selector 12 in a usual state, outputs a signal 18 when the phase difference is ±90 degrees or over to allow the selector 12 to output the signal 16' or to output the signal 16 when the phase difference is ±90 degrees or below for the changeover control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a phase by suppressing phase fluctuation in a selected clock signal.
A clock switching adjustment method capable of stably following the phase of a selected clock signal with Lock · Loop (hereinafter, referred to as PLL) and an Exclu as a phase comparator to which the method is applied
The present invention relates to a clock switching adjustment circuit including a PLL circuit using a five-OR (hereinafter referred to as Ex-OR) circuit.

[0002]

2. Description of the Related Art Conventionally, in a clock switching adjustment circuit including a PLL circuit of this type, the condition is that the duty of two clock signals whose phases are compared by a phase comparator (Ex-OR) is 50%. Otherwise, it is necessary to generate a frequency-divided clock signal with a duty of 50% by dividing the frequency of the input clock signal by a frequency divider.

FIG. 3 is a circuit block diagram showing a basic configuration of an example of a conventional clock switching adjustment circuit. This clock switching adjustment circuit is adapted to control the input clock signal 10
Frequency dividers 111, 121, 131 for dividing, １ ，, and 103 into 1/2 and outputting ク ロ ッ ク frequency clock signals 112, 122, 132, respectively, and a switching signal 104 input. 1/2 frequency-divided clock signal 11
Clock signal selection circuit 1 for selecting any one of 2, 122 and 132 and outputting as selected clock signal 105
And a voltage controlled oscillator (VCO) 10 for generating an output clock signal according to a predetermined cycle according to the low-pass filtered signal
8, the output clock signal from the voltage controlled oscillator 108 and the selected clock signal 1 from the clock signal selection circuit 114
A phase comparator (Ex-OR circuit) 10 that outputs a phase comparison signal as a result of performing an exclusive OR operation with respect to the phase comparison signal 05 and an exclusive OR operation.
6 and a low-pass frequency filter (Low · Pas) that filters the phase comparison signal at a predetermined low-pass frequency and outputs a low-pass filtered signal.
s · Filter / LPF) 107.

That is, the phase comparator 106, the low-frequency filter 107, and the voltage-controlled oscillator 108 constitute a PLL circuit, and generate an output clock signal generated in the voltage-controlled oscillator 108 according to a predetermined cycle. ,
An exclusive OR of the selected clock signal 105 and the output clock signal is calculated by the phase comparator 106 and the phase comparison signal obtained as a result of the phase comparison is filtered by the low-pass frequency filter 107 at a predetermined low-pass frequency. The PLL process for following the phase of the selected clock signal 105 is performed by obtaining the low-pass filtered signal in accordance with the low-pass filtered signal.

[0005] Incidentally, a known technique (PLL circuit, phase comparison, phase difference detection, phase adjustment, clock control, synchronization adjustment, etc.) related to such a clock switching adjustment circuit is disclosed in Japanese Patent Application Laid-Open No. Hei 6-177866. Clock control method, a clock recovery circuit in a subordinate synchronous network disclosed in JP-A-6-197101, and JP-A-7-7
No. 9157, a synchronizing circuit disclosed in
A clock generation circuit disclosed in Japanese Patent No. 46601 is known.

[0006]

In the case of the above-described clock switching adjusting circuit, a frequency divider is provided in order to generate a 50% duty clock signal, and a 1/2 frequency divider is provided in the circuit configuration. Since the configuration is such that the uncertainty of the phase after 1/2 frequency division is not avoided, for example, even when a clock signal of the same phase is input as an input condition, each of the frequency dividers is independently set to 1/2. By performing the frequency division, the phase difference after 1/2 frequency division often becomes 180 degrees, and the phase fluctuation increases when the clock signal is switched by the clock selection circuit. As a result, the clock signal is reduced by the clock selection circuit. Is switched, the phase difference of 180 degrees occurs in the selected clock signal, and the phase variation increases when the phase of the selected clock signal is followed by the PLL circuit. The entire clock signal systems with click switch adjustment circuit there is a problem that causes a phase skip.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. A technical problem of the present invention is to suppress the phase fluctuation in a selected clock signal to stably follow the phase of the selected clock signal by a PLL. An object of the present invention is to provide a clock switching adjustment method and circuit capable of avoiding possible phase jump.

[0008]

According to the present invention, a plurality of clock signals which are synchronized with each other are separately frequency-divided by ２, and a plurality of clocks which are synchronized with 50% duty are divided by の. A clock dividing step of outputting a clock signal; a clock selecting step of selecting one of a plurality of 1/2 frequency-divided clock signals based on an input switching signal and outputting the selected clock signal as a selected clock signal; A signal obtained by exclusive-ORing a signal with an output clock signal generated in accordance with a predetermined cycle and comparing the phases with each other is filtered at a predetermined low-frequency by a low-pass filtered signal. And a PLL processing step of following the phase of the selected clock signal by generating a signal. A frequency-divided clock inversion step of separately inverting and obtaining a 1/2 frequency-divided clock inversion signal in a one-to-one set, and outputting a plurality of 1/2 frequency-divided clock signals in a normal state, A clock switching step of switching and outputting either one of a 1/2 frequency-divided clock signal and a 1/2 frequency-divided clock inverted signal in a one-to-one set according to a predetermined switching control signal, A phase difference between the selected clock signal being selected and each of a plurality of 1/2 frequency-divided clock signals obtained in the clock switching step is detected, and the phase difference is ± 90%.
If the angle is equal to or more than 1/2 degrees, a 1/2 frequency-reversed clock inversion signal in a one-to-one set is output as a predetermined switching control signal at the clock switching stage.
And a clock phase difference detection switching control step of performing switching control to output a divide-by-2 clock signal.

Further, according to the present invention, in the above-described clock switching adjustment method, the clock phase difference detection switching control step includes an exclusive logic operation of the selected clock signal and a plurality of 1/2 frequency-divided clock signals in the switching step. A phase comparison step of outputting a phase comparison result signal as a result of the phase comparison by taking the sum;
An integration step of integrating the phase comparison value indicated by each phase comparison result signal and outputting a phase comparison integration value, and generating a predetermined switching control signal based on a result of comparing each phase comparison integration value with a predetermined numerical value A clock switching adjustment method having a comparison control step of outputting is obtained. In this clock switching adjustment method, in the comparison control stage, when the predetermined numerical value is set to 0.5 and the phase comparison integral value is 0.5 or more, the phase difference is determined to be in the range of 90 to 270 degrees, and then the predetermined switching control signal is set. It is preferable to output a 1/2 frequency-reversed clock inversion signal at the clock switching stage.

On the other hand, according to the present invention, a plurality of clock signals input to each other are synchronized with each other by 1/2.
A plurality of frequency dividers for dividing the frequency to output a plurality of 1/2 frequency-divided clock signals synchronized with a duty of 50%, and any of a plurality of 1/2 frequency-divided clock signals based on an input switching signal A clock signal selection circuit for selecting the selected clock signal and outputting the selected clock signal as a selected clock signal; and a voltage controlled oscillator for generating an output clock signal according to a predetermined cycle in accordance with the low-pass filtered signal; A phase comparator that outputs an exclusive OR of the output clock signal and the selected clock signal from the clock signal selection circuit and outputs a phase comparison signal as a result of phase comparison, and filters the phase comparison signal at a predetermined low frequency. And a low-pass frequency filter for outputting a low-pass filtered signal by a PLL circuit. And a plurality of inverting circuits that output a 1/2 frequency-divided clock inversion signal as a set, and in a normal state, output a plurality of 1/2 frequency-divided clock signals and output one-to-one according to a predetermined switching control signal. 1 in the set of
A plurality of switching circuits for switching and outputting one of a frequency-divided clock signal and a 分 frequency-divided clock inversion signal; and a plurality of switching circuits each of which is currently being selected by the clock signal selection circuit and is being selected. Multiple 1/2 from the circuit
A phase difference from each frequency-divided clock signal is detected, and when the phase difference is ± 90 degrees or more, a half-frequency-divided clock inversion is performed as a predetermined switching control signal by the plurality of switching circuits in a one-to-one set. A clock switching adjustment circuit including a plurality of phase difference detection switching control circuits for performing switching control for outputting a signal and outputting a 1/2 frequency clock signal when the signal is less than ± 90 degrees is obtained.

On the other hand, according to the present invention, in the above-mentioned clock switching adjusting circuit, the plurality of phase difference detection switching control circuits include a selected clock signal and a plurality of 1/2 frequency-divided clock signals from the plurality of switching circuits. A phase comparator that outputs a phase comparison result signal as a result of phase comparison by taking an exclusive OR, an integrator that integrates a phase comparison value indicated by the phase comparison result signal and outputs a phase comparison integrated value, And a comparator that generates and outputs a predetermined switching control signal based on the result of comparing the phase comparison integrated value with a predetermined numerical value. In this clock switching adjustment circuit, the comparator sets a predetermined value to 0.5
When the phase comparison integral value is 0.5 or more, the phase difference 9
It is preferable that the switching circuit outputs a 1/2 frequency-reversed clock inversion signal as a predetermined switching control signal after determining that the angle is in the range of 0 degrees to 270 degrees.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

First, an outline of the clock switching adjustment method of the present invention will be described. This clock switching adjustment method is
A clock frequency dividing step of independently dividing a plurality of clock signals inputted in the conventional manner into ２ and outputting a plurality of 周 frequency synchronized clock signals with a duty of 50%; A clock selecting step of selecting any one of the plurality of 1/2 frequency-divided clock signals based on the switching signal to be output and outputting the selected clock signal as a selected clock signal; and selecting the selected clock signal and an output clock signal generated according to a predetermined cycle. By generating an output clock signal in accordance with a low-pass filtered signal obtained by filtering a phase comparison signal obtained as a result of performing an exclusive OR operation on the phase comparison signal at a predetermined low-pass frequency, the phase of the selected clock signal is changed. In addition to the above, prior to the PLL processing stage, a plurality of 1/2 frequency-divided clock signals are individually inverted to form a one-to-one In this case, a divided clock inverting step of obtaining a 1/2 frequency-divided clock inversion signal is performed, and in a normal state, output is performed for each of a plurality of 1/2 frequency-divided clock signals, and one-to-one in accordance with a predetermined switching control signal. A clock switching step of switching and outputting one of a 1/2 frequency-divided clock signal and a 1/2 frequency-divided clock inverted signal in a set, and a clock switching step and a selected clock signal which is currently being selected in the clock selection step, respectively A phase difference between each of a plurality of 1/2 frequency-divided clock signals obtained by the step is detected. When the phase difference is equal to or more than ± 90 degrees, a predetermined switching control signal is used as a predetermined switching control signal. The inverted clock of the frequency-divided-by-2 is output, and ± 90
A clock phase difference detection switching control step of performing switching control to output a 1/2 frequency-divided clock signal when the frequency is less than one degree.

However, the clock phase difference detection switching control step is a phase comparison result signal obtained by performing an exclusive OR operation on the selected clock signal and each of a plurality of 分 frequency-divided clock signals in the switching step and comparing the phases. A phase comparison step of outputting
An integration step of integrating the phase comparison value indicated by each phase comparison result signal and outputting a phase comparison integration value, and generating a predetermined switching control signal based on a result of comparing each phase comparison integration value with a predetermined numerical value And outputting a comparison control step. In the comparison control step, when a predetermined numerical value is set to 0.5 and the phase comparison integral value is 0.5 or more, it is determined that the phase difference is in the range of 90 degrees to 270 degrees. In this case, a 1/2 frequency inverted clock signal is output as a predetermined switching control signal at the clock switching stage.

According to such a clock switching adjustment method, when the phase comparison integral value is 0.5 or more in the comparison control stage, it is determined that the phase difference is 90 degrees to 270 degrees, and the 1/2 frequency division is performed in the clock switching stage. Since the control for outputting the inverted clock signal is given independently, the phase difference of the currently selected clock signal is set to ± 90 degrees or less (that is, 0 to 9 degrees).
0 degrees or 270 degrees to 360 degrees), and the phase fluctuation of the selected clock signal can be suppressed small.
The phase of the selected clock signal can be stably followed by LL.

FIG. 1 is a circuit block diagram showing a basic configuration of a clock switching adjustment circuit according to one embodiment to which the clock switching adjustment method is applied. Also in the case of this clock switching adjustment circuit, compared to the conventional circuit shown in FIG. 3, a plurality of clock signals 1 (herein, the following components are also shown as having three components) synchronized with each other are input. , 2,3
Are separately divided by ２, and a plurality of １ ／ frequency-divided clock signals 16, 26, 36 synchronized with a 50% duty
And a selected clock signal by selecting one of a plurality of 1/2 frequency-divided clock signals 16, 26, 36 based on the input switching signal 4. And a voltage control oscillator (VCO) for generating an output clock signal according to a predetermined cycle according to the low-pass filtered signal.
8, a phase comparator (Ex-OR circuit) 6 for outputting a phase comparison signal as a result of phase comparison between the output clock signal from the voltage controlled oscillator 8 and the selected clock signal 5 from the clock signal selection circuit 40, A common configuration has a PLL circuit including a low-pass frequency filter (LPF) 7 that filters the comparison signal at a predetermined low-pass frequency and outputs a low-pass filtered signal.

That is, also in this case, the phase comparator 6, the low-frequency filter 7 and the voltage-controlled oscillator 8 together constitute a PLL circuit, and the output clock signal generated in the voltage-controlled oscillator 8 according to a predetermined cycle is An exclusive OR of the selected clock signal 5 and the output clock signal is calculated by the phase comparator 6 and a phase comparison signal obtained as a result of the phase comparison is filtered by a low-pass frequency filter 7 at a predetermined low-pass frequency. The PLL processing for following the phase of the selected clock signal 5 is performed by obtaining the low-pass filtered signal in accordance with the low-pass filtered signal.

However, in the case of this clock switching adjustment circuit,
A plurality of inversions for inverting a plurality of 1/2 frequency-divided clock signals 16, 26, and 36 individually and outputting 1/2 frequency-divided clock inversion signals 16 ', 26', and 36 'in a one-to-one set Circuits 17, 27, 37 and a plurality of 1/2
Output is performed for each of the divided clock signals 16, 26, and 36, and the 1/2 divided clock signal 1 in a one-to-one set according to predetermined switching control signals 18, 28, and 38, respectively.
6, 26, 36 and 1/2 frequency inverted clock signal 16 ',
Selectors 12, 22, 32 as a plurality of switching circuits for switching and outputting either one of the selected clock signals 26 ', 36', a selected clock signal 5 which is currently being selected by the clock signal selection circuit 40, and a plurality of selectors. 12, 22, 32
The phase difference from each of the 1/2 frequency-divided clock signals 16, 26, and 36 is detected, and when the phase difference is ± 90 degrees or more, each of the selectors 12, 22, and At 32, the inverted 1/2 frequency clock signals 16 ', 26', 36 'in a one-to-one set are output, and when less than ± 90 degrees, the 1/2 frequency clock signals 16, 26, 36 are output. And a plurality of phase difference detection switching control circuits for performing switching control to effect the switching.

The plurality of phase difference detection switching control circuits include a selected clock signal 5 and a plurality of selectors 12 and 2.
2, 32 from a plurality of 1/2 frequency-divided clock signals 16, 2
And a phase comparator (Ex-OR) for outputting a phase comparison result signal as a result of performing an exclusive OR operation with each of the signals 6, 36
Circuits) 13, 23, 33, and CR integrators 14, 2 each including a resistor R and a capacitor C for integrating the phase comparison value indicated by the phase comparison result signal and outputting the phase comparison integrated value.
4, 34, and a predetermined switching control signal 18, based on the result of comparing the respective phase comparison integrated values with a predetermined numerical value.
And comparators 15, 25, and 35 for generating and outputting 28 and 38, respectively. Further, the comparators 15, 25, 35
When the predetermined numerical value is set to 0.5 and the phase comparison integral value is 0.5 or more, it is determined that the phase difference is in the range of 90 degrees to 270 degrees, and the selectors 12, 22, and 32 are set as the predetermined switching control signals 18, 28, and 38. And the 1/2 frequency inverted clock signal 1
6 ', 26' and 36 'are output.

That is, in this clock switching adjusting circuit, the frequency dividers 11, 21, 31 output the clock signals 1,
1/2 is divided into two and a half frequency clock signal 16,
When the selectors 12, 22, and 32 receive the switching control signals 18, 28, and 38 indicating the normal 0 value from the comparators 15, 25, and 35, respectively, the 1/2 frequency-divided clock signal is generated. 16, 26 and 36 are switched and output, and when switching control signals 18, 28 and 38 each indicating a value of 1 are inputted, the inverted 1/2 frequency clock signal 16 ′ inverted by the inverting circuits 17, 27 and 37, 26 'and 36' are switched and output.

The phase comparators 13, 23, and 33 output the 1/2 frequency-divided clock signal 16, 26, 36 or the 1/2 frequency-divided clock inverted signal 16 selected by the selectors 12, 22, 32.
', 26', 36 '(normally 1/2 frequency-divided clock signal 1
6, 26, 36) and the selected clock signal 5 currently selected by the clock selection circuit 40, and outputs a phase comparison result signal as a result of phase comparison by taking an exclusive OR.
The integrators 14, 24, and 34 have an LPF function to block and smooth the high-frequency components of the rectangular wave, thereby integrating the phase comparison result signals output from the phase comparators 13, 23, and 33. And outputs the phase comparison integrated value.

The comparators 15, 25 and 35 are composed of comparators based on 0.5, and the CR integrators 14, 2
Since the phase comparison integrated value output from each of the selectors 4, 22, and 34 is in the range of 0 to 1, the switching control signal indicating a value of 1 to the selectors 12, 22, and 32 when the phase comparison integrated value is 0.5 or more. To select the 1/2 frequency-reversed clock inverted signals 16 ', 26', 36 ', and a switching control signal indicating a value of 0 to the selectors 12, 22, 32 when the signal is less than 0.5. Is output to select the 1/2 frequency-divided clock signal 16, 26, 36.

The clock selection circuit 40 receives the frequency-divided clock signal 16, 26, 36 or the 1/2 frequency-reversed clock inverted signal 16 ', 26', 36 'inputted based on the switching signal 4.
Is selected and output as the selected clock signal 5, and the PLL circuit performs the above-described operation.

FIG. 2 is a timing chart showing a waveform of a processing signal in a main part of the clock switching adjustment circuit.

Here, the clock selection circuit 40 selects the 周 frequency-divided clock signal 16 by the switching signal 4, and the input clock signal 1 is divided by the frequency divider 11 into １ ／.
The operation is premised on an operation in which the frequency-divided clock signal 16 is selected by the selector 12 to be divided by the selector 12, and the clock signal 16 is selected by the clock selection circuit 40 and output as the selected clock signal. .

Therefore, when the input clock signal 1 and the input clock signal 2 are input at substantially the same phase, the 1/2 frequency output from the frequency divider 11 is output due to the indefinite phase of the frequency dividers 11 and 21. The phase difference between clock signal 16 and 1/2 frequency-divided clock signal 26 output from frequency divider 21 is 1
Assuming that the angle is 80 degrees, the output of the phase comparator 23 becomes 1 except at the changing point as shown in FIG.

The output of the phase comparator 23 is output to the integrator 2
When the input is input to 4 and integrated, almost a value of 1 can be obtained. Therefore, the comparator 25 outputs 1 to the selector 22 because the output of the integrator 24 (phase comparison integrated value) is 0.5 or more.
Is controlled to output the value of divided clock inverted signal 26 ′. By selecting the 1/2 frequency-reversed clock inverted signal 26 ′ by the selector 22, the output 23 ′ of the phase comparator 23 becomes 0 except at the change point. As a result,
When the output 23 'of the phase comparator 23 is input to the integrator 24 and integrated, a value of almost 0 can be obtained, and the phase difference from the 1/2 frequency-divided clock signal 16 can be made ± 90 degrees or less.

When the input clock signal 1 and clock signal 3 are input with a phase difference of 90 degrees, the output of the frequency divider 11 is halved due to the indefinite phase of the frequency dividers 11 and 31. The phase difference between the divided clock signal 16 and the 1/2 frequency clock signal 36 output from the frequency divider 31 is 45
Degrees, the output of the phase comparator 33 is 1 at 25%.
And the remaining 75% is a value of 0.

The output of the phase comparator 33 is output to the integrator 3
Since the value of approximately 0.25 can be obtained by inputting the signal to the input terminal 4 and integrating it, the comparator 35 outputs 0 to the selector 32 because the output (phase comparison integrated value) of the integrator 34 is less than 0.5. Is controlled to select and output the 1/2 frequency-divided clock signal 26. In the phase comparator 13, the phase of the input signals is the same and the phase difference is 0 degree.
Similarly to the case of 3, the comparator 15 outputs a value of 0 to the selector 12 because the output of the integrator 14 (phase comparison integrated value) is less than 0.5, and outputs the 1/2 frequency clock signal 16 Is controlled to select and output.

[0030]

As described above, according to the clock switching adjustment method and circuit of the present invention, a 1/2 frequency inverted clock signal obtained by inverting a 1/2 frequency clock signal is obtained.
One of the 1/2 frequency-divided clock signal and the 1/2 frequency-reversed clock inverted signal is switched and output, and the currently selected clock signal being selected and the 1/2 frequency-divided clock signal are output. And outputs a 1/2 frequency inverted clock signal at the time of switching output when the phase difference is ± 90 degrees or more, and outputs a 1/2 frequency clock signal when the phase difference is less than ± 90 degrees. Since the switching control is performed, the phase difference of the currently selected selected clock signal is ± 90 degrees or more due to the phase uncertainty of the frequency divider and the phase difference of the selected clock signal after 1/2 frequency division. Even if it becomes, the phase fluctuation can be suppressed by adjusting within ± 90 degrees, and even if the clock is switched by the clock selection circuit, the phase fluctuation is within ± 90 degrees. , And the phase jump in a system to which the clock switching adjustment circuit is applied can be avoided.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a basic configuration of a clock switching adjustment circuit according to an embodiment to which a clock switching adjustment method of the present invention is applied.

FIG. 2 is a timing chart showing a waveform of a processing signal in a main part of the clock switching adjustment circuit shown in FIG. 1;

FIG. 3 is a circuit block diagram illustrating a basic configuration according to an example of a conventional clock switching adjustment circuit.

[Explanation of symbols]

1, 2, 3, 101, 102, 103 Clock signal 4, 104 Switching signal 5, 105 Selected clock signal 6, 13, 23, 33, 106 Phase comparator (Ex-O
R circuit) 7,107 Low frequency filter (LPF) 8,108 Voltage controlled oscillator (VCO) 11,21,31,111,121,131 Divider 12,22,32 Selector 14,24,34 CR integration Units 15, 25, 35 Comparators 16, 26, 36, 112, 122, 132 1/2 frequency-divided clock signal 16 ', 26', 36 '1/2 frequency-reversed clock inverted signal 17, 27, 37 Inverting circuit 18 , 28,38 Switching control signal 40,114 Clock signal selection circuit

Claims (6)

[Claims] 1. A duty cycle of a plurality of clock signals which are synchronized with each other is divided by 周.
% Of a plurality of 1/2 frequency-divided clock signals that are synchronized with each other, and selecting one of the plurality of 1/2 frequency-divided clock signals based on an input switching signal. A clock selecting step of outputting the selected clock signal, and an exclusive OR of the selected clock signal and an output clock signal generated according to a predetermined cycle, and filtering the phase comparison signal as a result of the phase comparison at a predetermined low frequency. A phase-lock-loop processing step of following the phase of the selected clock signal by generating the output clock signal in accordance with the low-pass filtered signal obtained by / 2
A divided clock inverting step of separately inverting the divided clock signals to obtain a 分 -divided clock inverted signal in a one-to-one set, and in a normal state, each of the plurality of 分 -divided clock signals A clock switching step of outputting any one of the 1/2 frequency-divided clock signal and the 1/2 frequency-divided clock inverted signal in a one-to-one set according to a predetermined switching control signal. Detecting a phase difference between the currently selected clock signal currently selected in the clock selection step and each of the plurality of 1/2 frequency-divided clock signals obtained in the clock switching step, and detecting the phase difference. When the angle is more than ± 90 degrees, the half switching clock inversion signal in a one-to-one set is output as the predetermined switching control signal at the clock switching stage, and ± 9 A clock phase difference detection switching control step of performing switching control to output the 1/2 frequency clock signal when the angle is less than 0 degrees. 2. The clock switching adjustment method according to claim 1, wherein said clock phase difference detection switching control step comprises: said selected clock signal and said plurality of ones in said switching step.
A phase comparison step of outputting a phase comparison result signal as a result of performing an exclusive OR operation with each of the ２ frequency-divided clock signals and integrating a phase comparison value indicated by the phase comparison result signal to perform a phase comparison A clock comprising: an integration step of outputting an integrated value; and a comparison control step of generating and outputting the predetermined switching control signal based on a result of comparing each of the phase comparison integration values with a predetermined numerical value. Switching adjustment method. 3. The clock switching adjustment method according to claim 2, wherein said predetermined numerical value is set to 0.
When the phase comparison integral value is 0.5 or more, the phase difference is determined to be in the range of 90 degrees to 270 degrees, and the predetermined switching control signal is used as the predetermined switching control signal in the clock switching step.
A clock switching adjustment method, characterized in that a half-frequency-divided clock inversion signal is output. 4. A duty cycle of a plurality of clock signals which are synchronized with each other and which are separately divided by ２.
% Of the plurality of 1/2 frequency-divided clock signals, and selecting one of the plurality of 1/2 frequency-divided clock signals based on an input switching signal. A clock signal selection circuit that outputs the selected clock signal as a selected clock signal, and a voltage-controlled oscillator that generates an output clock signal according to a predetermined cycle in accordance with the low-pass filtered signal;
A phase comparator that outputs an exclusive OR of the output clock signal from the voltage controlled oscillator and the selected clock signal from the clock signal selection circuit and performs a phase comparison, and the phase comparison signal And a low-pass frequency filter that outputs the low-pass filtered signal by filtering the plurality of signals at a predetermined low-pass frequency.
/ 2 frequency-divided clock signals are separately inverted to obtain one-to-one
A plurality of inverting circuits for outputting a 1/2 frequency-divided clock inversion signal as a set, and in a normal state, output for each of the plurality of 1/2 frequency-divided clock signals, and one pair in accordance with a predetermined switching control signal. A plurality of switching circuits for switching and outputting any one of the 分 frequency-divided clock signal and the 分 frequency-divided clock inverted signal in one set, and each of which is currently selected by the clock signal selection circuit; Detecting a phase difference between the selected clock signal and each of the plurality of 1/2 frequency-divided clock signals from the plurality of switching circuits, and when the phase difference is ± 90 degrees or more, the predetermined switching control signal is used as the predetermined switching control signal. The plurality of switching circuits output the 1/2 frequency-reversed clock inversion signals in a one-to-one set, and output the 1/2 frequency-divided clock signal when less than ± 90 degrees. And a plurality of phase difference detection switching control circuits for performing switching control of the clock switching adjustment circuit. 5. The clock switching adjustment circuit according to claim 4, wherein said plurality of phase difference detection switching control circuits are each for said selected clock signal and said plurality of 1/2 frequency-divided clock signals from said plurality of switching circuits. A phase comparator that outputs a phase comparison result signal obtained by performing an exclusive OR operation on the phase comparison result and an integrator that integrates the phase comparison value indicated by the phase comparison result signal and outputs a phase comparison integrated value And a comparator that generates and outputs the predetermined switching control signal based on a result of comparing each of the phase comparison integrated values with a predetermined numerical value. 6. The clock switching adjustment circuit according to claim 5, wherein the comparator sets the predetermined numerical value to 0.5 and sets a phase difference of 90 when the phase comparison integrated value is 0.5 or more.
A clock switching adjustment circuit, wherein the switching circuit outputs the inverted 1/2 frequency inverted clock signal as the predetermined switching control signal after judging the angle to be in the range of degrees to 270 degrees.