JP4103620B2 - Digital PLL circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital PLL circuit, which achieves both jitter characteristics and frequency pull-in range characteristics.
[0002]
[Prior art]
The digital PLL circuit is used to generate a signal processing internal clock synchronized with a network clock in a digital communication terminal such as a router or a terminal adapter. A specific example of a digital PLL circuit in an LSI element incorporated in a conventional ISDN terminal is shown in FIG. A 4 kHz network clock is input to one input terminal of the phase comparator 10. The crystal oscillator 12 oscillates a 12.288 MHz clock signal. This clock signal is frequency-divided into two by the fixed frequency divider 14 to be a 6.144 MHz clock signal, and further divided sequentially by the variable frequency divider 16 and the fixed frequency divider 18, and then the other input of the phase comparator 10. Input at the end. The phase comparator 10 compares both inputs and outputs a signal corresponding to the phase relationship (which is first and which is later).
[0003]
The frequency division ratio control unit 20 variably controls the frequency division ratio of the variable frequency divider 16 according to the output signal of the phase comparator 10. In other words, the frequency dividing ratio of the variable frequency divider 16 can be switched to 3, 4, or 5 and is normally set to 4, and the 6.144 MHz clock signal is divided by 4. A 1.536 MHz clock signal is output. The division ratio of the fixed frequency divider 18 is set to 384 frequency division, and a 1.536 MHz clock signal is divided by 384 to generate a 4 kHz clock signal and input to the phase comparator 10. As a result of the phase comparison by the phase comparator 10, when the clock signal output from the fixed frequency divider 18 is delayed with respect to the network clock, the frequency division ratio of the variable frequency divider 16 is 1 within the phase comparison period. (Ie, one period of the divided output of the variable frequency divider 16) is switched to 3 division (the remaining period in the phase comparison period is held at 4 division), and as a result, variable division The phase of the output clock signal of the counter 16 and the output clock signal of the fixed frequency divider 18 are advanced by one clock of 6.144 MHz clock within the phase comparison period. Conversely, when the clock signal output from the fixed frequency divider 18 is advanced with respect to the network clock, the frequency division ratio of the variable frequency divider 16 is once within the phase comparison period (that is, the variable frequency divider). (1 period of 16 divided outputs) is switched to 5 divisions (the remaining period in the phase comparison period is held at 4 divisions). As a result, the output clock signal of the variable frequency divider 16 and further The phase of the output clock signal of the fixed frequency divider 18 is delayed by one clock of 6.144 MHz clock within the phase comparison period.
[0004]
In this manner, the phase of the output clock signal of the variable frequency divider 16 is delayed by one clock of the 6.144 MHz clock in accordance with the phase relationship between the two inputs of the phase comparator 10 for each phase comparison period. Or advanced and adjusted and phase locked to the network clock. The output clock signal of the variable frequency divider 16 phase-locked to the network clock is used for various signal processing as a network synchronization clock in the LSI element. The output clock signal of the variable frequency divider 16 is output to the outside of the LSI element, supplied to other circuit elements in the ISDN terminal, and used as various types of signal processing as a network synchronization clock.
[0005]
[Problems to be solved by the invention]
According to the digital PLL circuit of FIG. 2, the phase comparator 10 always gives a comparison result that the phase of one input is delayed or advanced with respect to the phase of the other input every phase comparison period. (The comparison result that the phases of both inputs are the same is not output.) Therefore, the variable frequency divider 16 is switched once every phase comparison period, from the 4th frequency division to the 3rd frequency division, or from the 4th frequency division to the 5th frequency division. Each time the division ratio is switched, a jitter (phase fluctuation) of one 6.144 MHz clock (about 160 nsec) occurs. In addition, since the phase adjustment for one clock of 6.144 MHz clock can be performed for each phase comparison period by switching the frequency division ratio, the frequency pull-in range of this digital PLL circuit is centered on 4 kHz which is the frequency of the network clock. This is a frequency range in which the phase is shifted by ± 1 clock of 6.144 MHz clock per cycle of 4 kHz.
[0006]
Therefore, in the digital PLL circuit of FIG. 2, the input clock frequency of the variable frequency divider 16 may be increased in order to reduce the jitter associated with the frequency division ratio switching, but in this case, the frequency pull-in range is narrowed. On the contrary, in order to widen the frequency pull-in range, the input clock frequency of the variable frequency divider 16 may be lowered, but this causes an increase in jitter associated with switching of the division ratio. For this reason, it was impossible to achieve both jitter characteristics and frequency pull-in range characteristics. Further, according to the digital PLL circuit of FIG. 2, the frequency division ratio of the variable frequency divider 16 is always switched every phase comparison period, and jitter is generated each time.
[0007]
The present invention aims to provide a digital PLL circuit that solves the problems in the prior art and achieves both jitter characteristics and frequency pull-in range characteristics. Another object of the present invention is to provide a digital PLL circuit in which the number of frequency division switching is reduced.
[0008]
[Means for Solving the Problems]
The digital PLL circuit of the present invention includes an oscillator that outputs an oscillation signal of a predetermined frequency, a first variable frequency divider that receives and divides a first clock signal based on the oscillation signal of the oscillator, and the first A phase comparator that compares the phase of the clock signal based on the frequency-divided output of the variable frequency divider and a predetermined input signal, and outputs a phase comparison result indicating the phase relationship of the two signals for each phase comparison; Based on the phase comparison result of the phase comparator, the frequency division ratio of the first variable frequency divider is temporarily compared with the normal frequency division ratio until the next phase comparison is performed. The phase of the clock signal based on the frequency-divided output of the first variable frequency divider is increased by a predetermined amount when it is ahead of the phase of the input signal, and is decreased by a predetermined amount when it is delayed. By changing the phase of the frequency-divided output of the first variable frequency divider. A first frequency dividing ratio control unit for the divided output of the frequency divider is phase synchronized with the input signal, synchronized with the first clock signal A clock signal having a higher frequency than the first clock signal A second variable frequency divider that receives and divides a second clock signal and a frequency dividing ratio of the second variable frequency divider are temporarily set according to a phase comparison result of the phase comparator. The phase of the frequency-divided output of the second variable frequency divider is changed by increasing a predetermined amount or decreasing the predetermined amount with respect to the normal frequency dividing ratio. A second frequency division ratio control unit for phase-synchronizing the frequency-divided output with the input signal, and the frequency-divided output per cycle by increasing or decreasing the frequency-divided ratio of the second variable frequency divider. The division of the second variable frequency divider is such that the amount of phase change is smaller than the amount of phase change per cycle of the divided output due to the increase or decrease of the division ratio of the first variable frequency divider. The increase amount and decrease amount of the circumferential ratio are set.
[0009]
According to this, the phase change amount per cycle of the frequency-divided output due to the increase or decrease of the frequency division ratio of the second variable frequency divider is the increase or decrease of the frequency division ratio of the first variable frequency divider. Therefore, the jitter due to the change in the frequency division ratio from the second variable frequency divider is caused by the change in the frequency division ratio of the first variable frequency divider. Divided output smaller than jitter can be obtained. Further, the phase change amount per cycle of the frequency-divided output due to the increase or decrease of the frequency division ratio of the first variable frequency divider constituting the PLL loop is the increase of the frequency division ratio of the second variable frequency divider. Alternatively, the frequency pull-in range is larger than the phase change amount per cycle of the divided output, so that a wide frequency pull-in range can be secured. Therefore, a frequency-divided output with a small jitter accompanying a change in the frequency division ratio is obtained from the second variable frequency divider, and a digital PLL circuit with a wide frequency pull-in range is realized.
[0010]
The second frequency division ratio control unit calculates a phase difference between the frequency division output of the second variable frequency divider and the frequency division output of the first variable frequency divider. No. Execute frequency change of the second variable frequency divider by changing the frequency division ratio of the first variable frequency divider to a value smaller than the phase change amount per cycle of the frequency division output. Thus, the frequency-divided output of the second variable frequency divider can be phase-synchronized with the input signal with high accuracy.
[0011]
The normal frequency division ratio of the second variable frequency divider can be set higher than the normal frequency division ratio of the first variable frequency divider (for example, an integer multiple of 2 or more). Further, the second clock signal can be an oscillation signal of the oscillator, for example, and the first clock signal can be a signal obtained by dividing the oscillation signal of the oscillator. Further, the frequency of the second clock signal is set to a times the frequency of the first clock signal (a is an integer equal to or greater than 2. In the embodiments described later, a = 2 is set), and The normal frequency division ratio of the second variable frequency divider is set lower than a times the normal frequency division ratio of the first variable frequency divider, and the frequency division of the first variable frequency divider is performed. The frequency of the frequency-divided output of the second variable frequency divider can be adjusted higher than the frequency of the output. Further, the frequency of the second clock signal is set to a times (a is an integer of 2 or more) with respect to the frequency of the first clock signal, and the normal frequency division ratio of the second variable frequency divider is set. The frequency division output of the first variable frequency divider and the frequency division output of the second variable frequency divider are set to a times the normal frequency division ratio of the first variable frequency divider. It can be adjusted to an equal frequency.
[0012]
The digital PLL circuit of the present invention includes an oscillator that outputs an oscillation signal of a predetermined frequency, a first variable frequency divider that receives and divides a first clock signal based on the oscillation signal of the oscillator, and the first A phase comparator that compares the phase of the clock signal based on the frequency-divided output of the variable frequency divider and a predetermined input signal, and outputs a phase comparison result indicating the phase relationship of the two signals for each phase comparison; Based on the phase comparison result of the phase comparator, the frequency division ratio of the first variable frequency divider is set to one time (the frequency division output of the first variable frequency divider before the next phase comparison is performed). 1 cycle), when the phase of the clock signal based on the frequency-divided output of the first variable frequency divider is ahead of the phase of the input signal, it is changed by +1 with respect to the normal frequency division ratio. When it is delayed, change the output of the first variable frequency divider by changing -1. And a first frequency division ratio control unit that synchronizes the frequency-divided output of the first variable frequency divider with the input signal, and is synchronized with the first clock signal (of the oscillator). A second variable frequency divider that divides the frequency by inputting a second clock signal that is a clock signal (based on an oscillation signal) and has a frequency higher than that of the first clock signal; and the second variable frequency divider The frequency division ratio of the second variable frequency divider is temporarily changed by +1 or −1 with respect to the normal frequency division ratio according to the phase comparison result of the phase comparator. And a second frequency division ratio control unit that changes the phase of the frequency output and synchronizes the frequency-divided output of the second variable frequency divider with the input signal.
[0013]
According to this, the higher the frequency of the operation clock (second clock signal) of the second variable frequency divider, the smaller the jitter amount of the frequency-divided output associated with the frequency-division ratio switching. As the frequency of the operation clock (first clock signal) of one variable frequency divider is lowered, the frequency pull-in range can be widened, and both jitter characteristics and frequency pull-in range characteristics can be achieved.
[0014]
The digital PLL circuit of the present invention includes an oscillator that outputs an oscillation signal of a predetermined frequency, a first variable frequency divider that receives and divides a first clock signal based on the oscillation signal of the oscillator, and the first A phase comparator that compares the phase of the clock signal based on the frequency-divided output of the variable frequency divider and a predetermined input signal, and outputs a phase comparison result indicating the phase relationship of the two signals for each phase comparison; Based on the phase comparison result of the phase comparator, the frequency division ratio of the first variable frequency divider is set to one time (the frequency division output of the first variable frequency divider before the next phase comparison is performed). 1 cycle), when the phase of the clock signal based on the frequency-divided output of the first variable frequency divider is ahead of the phase of the input signal, it is changed by +1 with respect to the normal frequency division ratio. When it is delayed, change the output of the first variable frequency divider by changing -1. And a first frequency division ratio control unit that synchronizes the frequency-divided output of the first variable frequency divider with the input signal, and is synchronized with the first clock signal (of the oscillator). A second variable frequency divider that receives and divides a second clock signal that is a clock signal (based on an oscillation signal) and has a frequency a times higher than the first clock signal (a is an integer of 2 or more). And the division ratio of the second variable frequency divider based on the phase comparison result of the phase comparator within a time corresponding to one period of the phase comparison (for example, until the next phase comparison is performed) ) A times (that is, a period of the divided output of the second variable frequency divider), for example, evenly distributed and divided by the first variable frequency divider with respect to its normal frequency dividing ratio. If the phase of the clock signal based on the output is ahead of the phase of the input signal, change it by +1 and delay When it is, the phase of the frequency-divided output of the second variable frequency divider is changed by changing −1, and the frequency-divided output of the second variable frequency divider is phase-synchronized with the input signal. 2 and a frequency division ratio control unit.
[0015]
According to this, jitter accompanying switching of the division ratio of the second variable frequency divider can be dispersed, and the amount of jitter generated by the single switching of the division ratio can be reduced. Further, since the frequency division ratio of the second variable frequency divider is switched by the number of times corresponding to the amount of jitter generated by the frequency division ratio switching of the first variable frequency divider, the frequency division output of the second variable frequency divider Can be phase-synchronized with the input signal with high accuracy.
[0016]
The digital PLL circuit of the present invention includes an oscillator that outputs an oscillation signal of a predetermined frequency, a first variable frequency divider that receives and divides a first clock signal based on the oscillation signal of the oscillator, and the first A phase comparator that compares the phase of the clock signal based on the frequency-divided output of the variable frequency divider and a predetermined input signal, and outputs a phase comparison result indicating the phase relationship of the two signals for each phase comparison; Based on the phase comparison result of the phase comparator, the frequency division ratio of the first variable frequency divider is set to one time (the frequency division output of the first variable frequency divider before the next phase comparison is performed). 1 cycle), when the phase of the clock signal based on the frequency-divided output of the first variable frequency divider is ahead of the phase of the input signal, it is changed by +1 with respect to the normal frequency division ratio. When it is delayed, change the output of the first variable frequency divider by changing -1. And a first frequency division ratio control unit that synchronizes the frequency-divided output of the first variable frequency divider with the input signal, and is synchronized with the first clock signal (of the oscillator). A second variable frequency division that is a clock signal (based on an oscillation signal) and that divides by inputting a second clock signal having a frequency higher than or equal to that of the first clock signal. And by temporarily changing the frequency division ratio of the second variable frequency divider by +1 or −1 with respect to the normal frequency division ratio according to the phase comparison result of the phase comparator. Changing the phase of the frequency-divided output of the second variable frequency divider to synchronize the frequency-divided output of the second variable frequency divider with the input signal. The phase difference between the divided output of the second variable divider and the divided output of the divider is No. The frequency division ratio of the second variable frequency divider is changed once every time the time corresponding to the phase change amount per cycle of the frequency division output due to the change of the frequency division ratio of the first variable frequency divider is reached. And a second frequency division ratio control unit for executing the change.
[0017]
According to this, when the cumulative value of the frequency division ratio switching of the first variable frequency divider exceeds a certain threshold, the frequency division ratio of the second variable frequency divider is switched. When the division ratio of the variable frequency divider is alternately switched to +1, -1, +1, -1,... For each phase comparison period (when switching of the division ratio is unnecessary), depending on the threshold setting, It can be avoided that the frequency division ratio of the second variable frequency divider is switched in conjunction with this, and the number of occurrences of jitter can be reduced.
[0018]
In this case, the second variable frequency divider is a clock signal synchronized with the first clock signal (based on the oscillation signal of the oscillator) and has a frequency a times (a Is an integer greater than or equal to 2) and inputs a high second clock signal to divide the frequency, and the second frequency division ratio control unit determines the frequency of the first variable frequency divider as a result of the phase comparison. A first counter that counts up when the phase of the clock signal based on the peripheral output is delayed from the phase of the input signal, and the result of the phase comparison based on the frequency-divided output of the first variable frequency divider A second counter that counts up when the phase of the clock signal is ahead of the phase of the input signal; and the first counter and the second counter for each 1 / a period of the phase comparison period Monitor the count value of (a) When the count value is other than 0, the frequency division ratio of the second variable frequency divider is maintained at the normal frequency division ratio until the next monitoring timing, and the count values of both counters are respectively counted down by 1 ( b) When the count value of the first counter is 0 and the count value of the second counter is greater than a predetermined value of 1 or more, the second variable frequency division is performed once before the next monitoring timing. And the counter value of the second counter is decremented by 1, and (c) the count value of the first counter is greater than a predetermined value of 1 or more and the second counter When the count value is 0, the frequency division ratio of the second variable frequency divider is changed by −1 once before the next monitoring timing, and the count value of the first counter is counted down by 1 (d ) Count value of both counters When the combination is other than that, counter monitoring and control for maintaining the frequency dividing ratio of the second variable frequency divider at the normal frequency dividing ratio and the count values of both counters as they are until the next monitoring timing. Part. According to this, when the frequency division ratio of the first variable frequency divider is alternately switched to +1, -1, +1, -1,... For each phase comparison period, the division of the second variable frequency divider. The number of switching of the frequency division ratio of the second variable frequency divider is reduced as compared with the case where the frequency ratio is switched by the number of times corresponding to the amount of jitter generated by the frequency division ratio switching of the first variable frequency divider. Can do. In particular, when the “predetermined value of 1 or more” in the above (b) and (c) is set to “a / 2” (that is, “when it is greater than the predetermined value of 1 or more” is greater than “a / 2”. When the frequency division ratio of the first variable frequency divider is alternately switched to +1, -1, +1, -1,... For each phase comparison period, the second variable The frequency division ratio of the frequency divider can be prevented from being switched in conjunction with this, and the second variable is compared with the case where the frequency division ratio of the second variable frequency divider is switched every phase comparison period. The frequency | count of switching of the frequency divider ratio of a frequency divider can be reduced, and the frequency | count of a jitter generation can be reduced compared with the conventional circuit of the said FIG.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an embodiment when the present invention is applied to a digital communication terminal such as a router or a terminal adapter. The same reference numerals are used for parts common to the conventional circuit of FIG. In the embodiment of FIG. 1, a case where a clock signal of 2.048 MHz is generated and output while using the configuration of the conventional circuit of FIG. 2 is shown. A portion where a conventional circuit is used is indicated by a one-dot chain line. A 4 kHz network clock is input to one input terminal of the phase comparator 10. The crystal oscillator 12 oscillates a 12.288 MHz clock signal. This clock signal is frequency-divided into two by the fixed frequency divider 14 to be a 6.144 MHz clock signal, and further divided sequentially by the variable frequency divider 16 and the fixed frequency divider 18, and then the other input of the phase comparator 10. Input at the end. The phase comparator 10 compares both inputs and outputs a signal corresponding to the phase relationship of the phases.
[0020]
The frequency division ratio control unit 20 variably controls the frequency division ratio of the variable frequency divider 16 according to the output signal of the phase comparator 10. In other words, the frequency dividing ratio of the variable frequency divider 16 can be switched to 3, 4, or 5 and is normally set to 4, and the 6.144 MHz clock signal is divided by 4. A 1.536 MHz clock signal is output. The division ratio of the fixed frequency divider 18 is set to 384 frequency division, and a 1.536 MHz clock signal is divided by 384 to generate a 4 kHz clock signal and input to the phase comparator 10. As a result of the phase comparison by the phase comparator 10, when the clock signal output from the fixed frequency divider 18 is delayed with respect to the network clock, the frequency division ratio of the variable frequency divider 16 is 1 within the phase comparison period. (Ie, one period of the divided output of the variable frequency divider 16) is switched to 3 division (the remaining period in the phase comparison period is held at 4 division), and as a result, variable division The phase of the output clock signal of the counter 16 and the output clock signal of the fixed frequency divider 18 are advanced by one clock of 6.144 MHz clock within the phase comparison period. Conversely, when the clock signal output from the fixed frequency divider 18 is advanced with respect to the network clock, the frequency division ratio of the variable frequency divider 16 is once within the phase comparison period (that is, the variable frequency divider). (1 period of 16 divided outputs) is switched to 5 divisions (the remaining period in the phase comparison period is held at 4 divisions). As a result, the output clock signal of the variable frequency divider 16 and further The phase of the output clock signal of the fixed frequency divider 18 is delayed by one clock of 6.144 MHz clock within the phase comparison period.
[0021]
In this way, the phase relationship between the two inputs of the phase comparator 10 is determined for each phase comparison period, and the phase of the output clock signal of the variable frequency divider 16 is delayed by one clock of the 6.144 MHz clock. Or advanced and adjusted and phase locked to the network clock.
[0022]
The variable frequency divider 22 divides the 12.288 MHz clock signal output from the crystal oscillator 12. The frequency division ratio control unit 24 is controlled by the frequency division ratio control unit 20 according to the frequency division ratio control of the variable frequency divider 16 (that is, according to the phase comparison result of the phase comparator 10). Variable division ratio control. In other words, the frequency dividing ratio of the variable frequency divider 22 can be switched to 5 division, 6 division, and 7 division, and is normally set to 6 division, and the 12.288 MHz clock signal is divided by 6. A 2.048 MHz clock signal is output. When the frequency dividing ratio of the variable frequency divider 22 is switched to 5 times in the phase comparison period of the phase comparator 10 (that is, one period of the frequency divided output of the variable frequency divider 22), the variable frequency divider 22 The phase of the 22 output clock signals is advanced by one clock of 12.288 MHz within the phase comparison period. Further, when the frequency division ratio of the variable frequency divider 22 is switched to 7 times in the phase comparison period of the phase comparator 10 (that is, one period of the frequency division output of the variable frequency divider 22), The phase of the output clock signal of the frequency divider 22 is delayed by one clock of 12.288 MHz within the phase comparison period. Since the operation clock frequency (12.288 MHz) of the variable frequency divider 22 is twice (that is, a = 2) the operation clock frequency (6.144 MHz) of the variable frequency divider 16, the phase of the phase comparator 10. Within the comparison period, the output clock signal of the variable frequency divider 22 can be phase-adjusted in half time units as compared with the output clock signal of the variable frequency divider 16.
[0023]
Therefore, when the frequency division ratio of the variable frequency divider 16 is switched once in the phase comparison cycle from the fourth frequency division to the third frequency division, the frequency division ratio control unit 24 performs the variable frequency division within the phase comparison cycle. The frequency dividing ratio of the frequency divider 22 is evenly distributed twice and switched from 6 frequency division to 5 frequency division. Further, when the frequency division ratio of the variable frequency divider 16 is switched once in the phase comparison period from the 4 frequency division to the 5 frequency division, the frequency division ratio of the variable frequency divider 22 is changed within the phase comparison period. Evenly distributed twice and switched from 6-divided to 7-divided. As a result, the phase correction amount in the entire phase comparison period becomes equal between the variable frequency divider 16 and the variable frequency divider 22, and as a result, the output clock signal of the variable frequency divider 22 is phase-locked to the network clock. Is done. In this case, the phase correction amount per time of the output clock signal of the variable frequency divider 22 is ½ that of the phase correction amount per time of the output clock signal of the variable frequency divider 16. The jitter of the output clock signal of the variable frequency divider 22 that is generated when the frequency ratio is switched is suppressed to ½ of the jitter of the output clock signal that is generated when the frequency ratio of the variable frequency divider 16 is switched. Further, the frequency pull-in range of this digital PLL circuit is a frequency range in which the phase is shifted by ± 1 clock of 6.144 MHz clock per cycle of 4 kHz around the network clock frequency of 4 kHz (that is, phase comparison). If the phase shift with respect to the network clock is 1 / 6.144 MHz or less within the period, it can be pulled into the locked state.), The same frequency pulling range as the conventional circuit of FIG.
[0024]
The output clock signal of the variable frequency divider 22 phase-locked to the network clock is used for various signal processing as a network synchronization clock in the LSI element. The output clock signal of the variable frequency divider 22 is output to the outside of the LSI element, supplied to other circuit elements in the ISDN terminal, and used for various signal processing as a network synchronization clock.
[0025]
In the above description, the frequency division ratio of the variable frequency divider 22 is switched every time the frequency division ratio of the variable frequency divider 16 is switched. When switching to frequency dividing and switching from dividing by 4 to dividing by 5 occur alternately every phase comparison period (when the phases of both inputs of the phase comparator 10 are almost the same). In this case, it is not necessary to switch the fractional ratio of the variable frequency divider 22 each time. Rather, it is considered preferable not to switch every time because there is no occurrence of jitter associated with switching of the frequency dividing ratio. Therefore, in such a case, the frequency division ratio control unit 24 may not switch the frequency division ratio of the variable frequency divider 22. A configuration example of the frequency division ratio control unit 24 that realizes such an operation is shown in FIG. The frequency division ratio control unit 20 divides the network clock by −1 when the phase comparison period is delayed with respect to the network clock according to the phase comparison result (the frequency division ratio of the variable frequency divider 16 is set once for four minutes). Command to change -1 from divide by 3 to divide by 3), and advance to the network clock, +1 divide command (divide variable divider 16 once, divide by 4 to divide by 5 Command to change to +1). The −1 frequency division command and the +1 frequency division command are sent to the variable frequency divider 16. When the variable frequency divider 16 inputs a −1 frequency division command, the variable frequency divider 16 switches once from within the phase comparison period (that is, one period of the frequency division output of the variable frequency divider 16) to 4 frequency division. As a result, the phase of the frequency-divided output of the variable frequency divider 16 is advanced by one clock of the 6.144 MHz clock that is the operation clock of the variable frequency divider 16. Further, when the variable frequency divider 16 receives the +1 frequency division command, it is once within the phase comparison cycle (that is, one cycle of the frequency division output of the variable frequency divider 16), and from the 4th frequency division to the 5th frequency division. As a result, the phase of the frequency-divided output of the variable frequency divider 16 is delayed by one clock of the 6.144 MHz clock that is the operation clock of the variable frequency divider 16.
[0026]
The −1 frequency division command and the +1 frequency division command output from the frequency division ratio control unit 20 are also sent to the frequency division ratio control unit 24. The frequency division ratio control unit 24 includes two counters (A) 26, a counter (B) 28, a counter monitoring and control unit 30, and a counter monitoring timing generation unit 32. The counter (A) 26 counts down by 2 every time a −1 frequency division command is input. The counter (B) 28 is incremented by 2 every time a +1 frequency division command is input. The counter monitoring timing generator 32 generates a timing signal for monitoring the count values of the counters (A) 26 and (B) 28 every half of the phase comparison period. For example, the variable frequency divider 22 The counter monitoring timing signal is output at the rising timing every two cycles of the output clock signal. The counter monitoring and control unit 30 monitors the count values of the counters (A) 26 and (B) 28 at each counter monitoring timing, and in each case, according to the relationship between the two count values, a -1 frequency division command (variable The frequency division ratio of the frequency divider 22 is changed once, and a command to change the frequency division from -6 to -5 is −1) or +1 frequency division command (the frequency division ratio of the variable frequency divider 22 is changed once, from frequency division 6 to frequency 7 minutes) Command to change the frequency to +1), or neither the -1 frequency division command nor the +1 frequency division command is output. When the variable frequency divider 22 receives the -1 frequency division command, the frequency division ratio is switched once (that is, one cycle of the frequency division output of the variable frequency divider 22) from 6 frequency division to 5 frequency division, As a result, the phase of the divided output is advanced by one clock of the 12.288 MHz clock that is the operation clock of the variable frequency divider 22. Further, when the variable frequency divider 22 inputs a +1 frequency division command, the frequency division ratio is switched from 6 frequency division to 7 frequency division once (that is, one period of the frequency division output of the variable frequency divider 22). As a result, the phase of the frequency-divided output is delayed by one clock of the 12.288 MHz clock which is the operation clock of the variable frequency divider 22. Further, every time the counter monitoring and control unit 30 monitors the count values of the counters (A) 26 and (B) 28, the counter monitoring and control unit 30 sets the counters (A) 26 and (B) 28 according to the relationship between the two count values. Control to count down the count value by 1 is also performed.
[0027]
A control algorithm by the counter monitoring and control unit 30 is shown in FIG. Every time the counter monitoring timing arrives every half of the phase comparison period, the count values of the counters (A) 26 and (B) 28 are monitored (S1). As a result, if neither of the counters (A) 26 and (B) 28 is 0 (S2), the counter (A) 26, (B ) Each of the count values of 28 is counted down by 1 (S3). When the count value of the counter (A) 26 is 0 and the count value of the counter (B) 28 is 2 or more (S4), the +1 frequency division command is output and the count value of the counter (B) 28 is counted down by 1 (S5). When the count value of the counter (A) 26 is 2 or more and the count value of the counter (B) 28 is 0 (S6), a −1 frequency division command is output and the count value of the counter (A) 26 is set to 1. Count down (S7). When none of the above applies (when the count values of the counters (A) 26 and (B) 28 are both 0), or one of the count values of the counters (A) 26 and (B) 28 is 0 and the other is In the case of 1), nothing is done (that is, neither the -1 frequency division command nor the +1 frequency division command is output, and the counters (A) 26 and (B) 28 are not counted down by 1).
[0028]
According to the above algorithm, the output clock signal of the variable frequency divider 22 is controlled to be synchronized with the output clock signal of the variable frequency divider 16 with a phase difference of one clock of 12.288 MHz. Further, when the switching of the frequency dividing ratio of the variable frequency divider 16 from 4 division to 3 division and from 4 division to 5 division occurs alternately every phase comparison period (phase In the case where the phases of both inputs of the comparator 10 are almost the same), the count values of the counters (A) 26 and (B) 28 merely repeat the combination of 0, 1 and the combination of 1, 0. Since neither the −1 frequency division command nor the +1 frequency division command is output, the frequency division ratio of the variable frequency divider 22 is not switched. With the above operation, unnecessary frequency division ratio switching of the variable frequency divider 22 is avoided, and jitter of the output clock signal of the variable frequency divider 22 that occurs due to frequency division ratio switching is suppressed.
[0029]
An example of the operation of the digital PLL circuit of FIG. 1 is shown in FIG. 5, (a) to (e) are the signals of the respective parts in FIG. 1, (a) is the network clock signal I (Fi) which is one input of the phase comparator 10, and (b) is the other of the phase comparator 10. The output clock signals I ′ (Fi ′) and (c) of the fixed frequency divider 18 as inputs are the output clock signals O (Fx), (d) and (e) of the variable frequency divider 16, respectively. 22 output clock signals (output clock signals of this digital PLL circuit) O ′ (Fy), of which (d) is variable each time the frequency division ratio control unit 24 switches the frequency division ratio of the variable frequency divider 16. FIG. 3E shows a case where the frequency division ratio of the frequency divider 22 is switched, and FIG. 3E shows a case where the frequency division ratio control unit 24 is configured as shown in FIG. 3 and operated according to the control algorithm shown in FIG. is there. (F) and (g) are the count values of the counters (A) 26 and (B) 28 in FIG. 3 in the case of (e). In FIG. 5, the frequency dividing ratios of the variable frequency dividers 16 and 22 and the fixed frequency divider 18 are changed as follows, unlike the above description. That is, the frequency division ratio of the variable frequency divider 16 is switched to three levels of m-1, m, and m + 1, where the normal frequency division ratio is m. The frequency dividing ratio of the variable frequency dividing ratio 22 is switched to three levels of 2m-1, 2m, and 2m + 1 when the normal frequency dividing ratio is 2 m. The normal frequency division ratio (2m) of the variable frequency divider 22 is twice the normal frequency division ratio (m) of the variable frequency divider 16, and the operation clock frequency (12.288 MHz) of the variable frequency divider 22 is The frequency of the output clock signals O (Fx) and O ′ (Fy) of the variable frequency dividers 16 and 22 is controlled to be equal to each other since they are twice the operation clock frequency (6.144 MHz) of the variable frequency divider 16. Is done. The frequency division ratio of the fixed frequency divider 18 is set to 4 frequency division.
[0030]
The phase comparator 10 generates the network clock signal I (Fi) in FIG. 5A and the clock signal I ′ (Fi ′) in FIG. 5B at each rising timing of the clock signal I ′ (Fi ′). And a phase comparison result indicating the front-rear relationship of both clock signals is output each time. When the phase comparison result indicating that the phase of the clock signal I ′ (Fi ′) is delayed with respect to the network clock signal I (Fi) is output, the frequency division ratio control unit 20 performs the next phase comparison. Once, the frequency division ratio of the variable frequency divider 16 is switched from m to m-1. Conversely, when a phase comparison result indicating that the phase of the clock signal I ′ (Fi ′) is advanced with respect to the network clock signal I (Fi) is output, it is once before the next phase comparison is performed. The frequency division ratio of the variable frequency divider 16 is switched from m to m + 1. Since the phase comparator 10 does not give a phase comparison result indicating that the phases of both inputs are equal, the frequency division ratio of the variable frequency divider 16 is always switched once every phase comparison period. In the example of FIG. 5, at the phase comparison timing I, the phase of the clock signal I ′ (Fi ′) is delayed with respect to the network clock signal I (Fi). The frequency division ratio of the variable frequency divider 16 is switched once from m to m−1 (with the period of the output clock signal of the frequency divider 16), so that the output clock of the variable frequency divider 16 is one clock of 6.144 MHz. The phase is advanced. Further, at the phase comparison timing II, the phase of the clock signal I ′ (Fi ′) is advanced with respect to the network clock signal I (Fi), so immediately (the phase of the variable frequency divider 16 to which the phase comparison timing II belongs). The frequency division ratio of the variable frequency divider 16 is switched once from m to m + 1 (with the period of the output clock signal), and as a result, the phase of the output clock of the variable frequency divider 16 is delayed by one clock of 6.144 MHz. .
[0031]
When the frequency division ratio control unit 24 is set to switch the frequency division ratio of the variable frequency divider 22 every time the frequency division ratio of the variable frequency divider 16 is switched, as shown in FIG. The frequency division ratio of the variable frequency divider 22 is switched between the timing at which the frequency division ratio of the variable frequency divider 16 is switched and the intermediate timing. That is, at the phase comparison timing I, since the phase of the clock signal I ′ (Fi ′) is delayed with respect to the network clock signal I (Fi), the timing immediately thereafter and the intermediate timing (after two clocks) are twice. The frequency division ratio of the variable frequency divider 22 is switched from 2m to 2m-1. As a result, the phase of the output clock of the variable frequency divider 22 is advanced by being divided into two times for each clock of 12.288 MHz. At the phase comparison timing II, since the phase of the clock signal I ′ (Fi ′) is advanced with respect to the network clock signal I (Fi), the timing immediately after that and the intermediate timing (after two clocks) are twice. The frequency division ratio of the variable frequency divider 22 is switched from 2 m to 2 m + 1. As a result, the phase of the output clock of the variable frequency divider 22 is delayed by being divided into two times for each clock of 12.288 MHz. Therefore, the jitter of the output clock signal of the variable frequency divider 22 that occurs when the variable frequency divider 22 is switched once is suppressed to one clock of 12.288 MHz.
[0032]
In the above, the case where the operation clock frequency of the variable frequency divider 22 is twice (12.288 MHz) the operation clock frequency (6.144 MHz) of the variable frequency divider 16 has been described. However, the operation frequency is 3 times (18.432 MHz). ), The dividing ratio of the variable frequency divider 22 may be changed by −1 or +1 every 1/3 period of the phase comparison period, and when it is four times (24.576 MHz), the phase comparison is performed. The frequency division ratio of the variable frequency divider 22 may be changed by −1 or +1 every quarter period. That is, generally speaking, when the operation clock frequency of the variable frequency divider 22 is a times the operation clock frequency of the variable frequency divider 16 (a is an integer of 2 or more), 1 / a of the phase comparison period. It is only necessary to change the frequency division ratio of the variable frequency divider 22 by −1 or +1 for each period.
[0033]
On the other hand, when the frequency division ratio control unit 24 is configured as shown in FIG. 3 and controlled by the algorithm shown in FIG. 4, the frequency division ratio of the variable frequency divider 22 is counted by the counters (A) 26 and (B) 28. Switching is performed according to the value as shown in FIG. That is, in FIG. 5G, the counter monitoring timing is determined as a rising timing every two cycles of the output clock signal of the variable frequency divider 22 (not limited to this, but from the next phase comparison timing). Any timing may be used as long as it is before). At the counter monitoring timing i, the count values of the counters (A) 26 and (B) 28 are 0 and 0, so nothing occurs. At the phase comparison timing I, since the phase of the clock signal I ′ (Fi ′) is delayed with respect to the network clock signal I (Fi), the counter (A) 26 is counted up by two. At the counter monitoring timing ii, the count values of the counters (A) 26 and (B) 28 are 2 and 0, and immediately after that (in the cycle of the output clock signal of the variable frequency divider 22 to which the counter monitoring timing ii belongs). ) The frequency division ratio of the variable frequency divider 22 is switched from 2 m to 2 m−1, and the phase of the output clock signal of the variable frequency divider 22 is advanced by one clock of 12.288 MHz. At the same time, the counter (A) 26 is counted down by one. At the counter monitoring timing iii, since the count values of the counters (A) 26 and (B) 28 are 1, 0, nothing occurs. At the phase comparison timing II, since the phase of the clock signal I ′ (Fi ′) is advanced with respect to the network clock signal I (Fi), the counter (B) 28 is counted up by two. At the counter monitoring timing iv, the count values of the counters (A) 26 and (B) 28 are 1 and 2, so that the frequency division ratio of the variable frequency divider 22 is not switched and the counters (A) 26 and (B ) 28 are both counted down by one. At the counter monitoring timing v, the count values of the counters (A) 26 and (B) 28 are 0 and 1, so nothing occurs. As described above, the frequency division ratio switching of the variable frequency divider 22 is suppressed, and even if the frequency division ratio switching is performed, the variable generated with one frequency division ratio switching of the variable frequency divider 22. The jitter of the output clock signal of the frequency divider 22 is suppressed to one clock of 12.288 MHz.
[0034]
In the above, the case where the operation clock frequency of the variable frequency divider 22 is twice (12.288 MHz) the operation clock frequency (6.144 MHz) of the variable frequency divider 16 has been described. However, the operation frequency is 3 times (18.432 MHz). ), The counter monitoring timing is set to the timing of every 1/3 period of the phase comparison period, and the count-up number for each of the counters (A) 26 and (B) 28 is set to 3 (one count-down number). Is changed to -1 or +1 when the difference between the count values of the counters (A) 26 and (B) 28 is 3 or more (step S4 in FIG. A = 0 and B> 2 ”and step S6 can be changed to“ A> 2 & B = 0 ”). In addition, in the case of 4 times (24.576 MHz), the counter monitoring timing is set to the timing of every quarter period of the phase comparison period, and the count-up number for each time of the counters (A) 26 and (B) 28 is 4 (the countdown number at one time remains 1), and when the difference between the count values of the counters (A) 26 and (B) 28 is 4 or more, the frequency division ratio of the variable frequency divider 22 is changed by −1 or +1. (Step S4 in FIG. 5 is changed to “A = 0 &B> 3” and step S6 is changed to “A> 3 & B = 0”).
[0035]
That is, generally speaking, when the operation clock frequency of the variable frequency divider 22 is a times the operation clock frequency of the variable frequency divider 16 (a is an integer of 2 or more), the phase comparison is performed for each phase comparison period. Depending on the result, one of the counters (A) 26 and (B) 28 is counted up, and the count values of the counters (A) 26 and (B) 28 are monitored every 1 / a period of the phase comparison period. When both count values are other than 0, the frequency division ratio of the variable frequency divider 22 is maintained at the normal frequency division ratio until the next monitoring timing, and both counters (A) 26 and (B) 28 are set. When the count value of the counter (A) 26 is 0 and the count value of the counter (B) 28 is larger than a / 2, it is changed once every time until the next monitoring timing. Change the division ratio of the frequency divider by +1 And the count value of the counter (B) 28 is decremented by 1, and when the count value of the counter (A) 26 is greater than a / 2 and the count value of the counter (B) 28 is 0, the next monitoring timing is reached. Once, the frequency division ratio of the variable frequency divider 22 is changed by −1 and the count value of the counter (A) 26 is decremented by 1 to combine the count values of both counters (A) 26 and (B) 28. In other cases, the frequency division ratio of the variable frequency divider 22 is maintained at the normal frequency division ratio until the next monitoring timing, and the count values of both counters (A) 26 and (B) 28 are maintained as they are. In this case, when the frequency division ratio of the variable frequency divider 16 is alternately switched to +1, -1, +1, -1,... For each phase comparison period, the frequency division ratio of the variable frequency divider 22 is changed. Switching in conjunction with this It is possible to avoid be. In addition, if “greater than 1” is used instead of “greater than a / 2”, the number of switching of the frequency division ratio of the variable frequency divider 22 is divided by the variable frequency divider 16 in the same case. This can be reduced as compared with {FIG. 5 (d)} in which switching is performed by the number of times corresponding to the amount of jitter generated by switching the circumferential ratio.
[0036]
In the above embodiment, the operation clock frequency (12.288 MHz) of the variable frequency divider 22 is twice the operation clock frequency (6.144 MHz) of the variable frequency divider 16, but is larger than twice. It can also be an integer multiple. In the above-described embodiment, the present invention is applied to a digital communication terminal such as a router or a terminal adapter. However, the present invention is also applied to other communication devices and electric devices other than communication devices. be able to.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a digital PLL circuit of the present invention.
FIG. 2 is a block diagram showing a conventional digital PLL circuit.
3 is a block diagram illustrating a configuration example of a frequency division ratio control unit 24 in FIG.
4 is a flowchart showing a control algorithm by a frequency division ratio control unit 24 in FIG. 3;
FIG. 5 is a time chart showing an operation of the digital PLL circuit of FIG. 1;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Phase comparator, 12 ... Oscillator, 16 ... 1st variable frequency divider, 20 ... 1st frequency division ratio control part, 22 ... 2nd variable frequency divider, 24 ... 2nd frequency division ratio control , 26, 28 ... counter, 30 ... counter monitoring and control unit.

Claims (6)

An oscillator that outputs an oscillation signal of a predetermined frequency;
A first variable frequency divider that receives and divides a first clock signal based on an oscillation signal of the oscillator;
A phase comparison that compares the phase of a clock signal based on the frequency-divided output of the first variable frequency divider and a predetermined input signal and outputs a phase comparison result indicating the phase relationship between the two signals for each phase comparison. And
Based on the phase comparison result of the phase comparator, the frequency division ratio of the first variable frequency divider is temporarily compared with the normal frequency division ratio until the next phase comparison is performed. The phase of the clock signal based on the frequency-divided output of the first variable frequency divider is increased by a predetermined amount when it is ahead of the phase of the input signal, and is decreased by a predetermined amount when it is delayed. A first frequency division ratio controller that changes the phase of the frequency-divided output of the first variable frequency divider and synchronizes the frequency-divided output of the first variable frequency divider with the input signal;
A second variable frequency divider that divides the frequency by inputting a second clock signal that is synchronized with the first clock signal and has a frequency higher than that of the first clock signal ;
The frequency division ratio of the second variable frequency divider is temporarily increased or decreased by a predetermined amount with respect to the normal frequency division ratio according to the phase comparison result of the phase comparator. A second frequency division ratio control unit that changes the phase of the frequency-divided output of the second variable frequency divider and synchronizes the frequency-divided output of the second variable frequency divider with the input signal. Equipped,
The amount of phase change per cycle of the frequency-divided output due to the increase or decrease of the frequency division ratio of the second variable frequency divider is the amount corresponding to the increase or decrease of the frequency division ratio of the first variable frequency divider. A digital PLL circuit in which an increase amount and a decrease amount of a frequency division ratio of the second variable frequency divider are set so as to be smaller than a phase change amount per cycle of the peripheral output. An oscillator that outputs an oscillation signal of a predetermined frequency;
A first variable frequency divider that receives and divides a first clock signal based on an oscillation signal of the oscillator;
A phase comparison that compares the phase of a clock signal based on the frequency-divided output of the first variable frequency divider and a predetermined input signal and outputs a phase comparison result indicating the phase relationship between the two signals for each phase comparison. And
Based on the phase comparison result of the phase comparator, the frequency division ratio of the first variable frequency divider is set to the normal frequency division ratio once before the next phase comparison is performed. When the phase of the clock signal based on the frequency-divided output of one variable frequency divider is ahead of the phase of the input signal, it is changed by +1, and when it is behind, the first variable is changed by -1. A first frequency division ratio controller that changes the phase of the frequency-divided output of the frequency divider and synchronizes the frequency-divided output of the first variable frequency divider with the input signal;
A second variable frequency divider that divides the frequency by inputting a second clock signal that is synchronized with the first clock signal and has a frequency higher than that of the first clock signal;
The frequency division ratio of the second variable frequency divider is temporarily changed by +1 or −1 with respect to the normal frequency division ratio in accordance with the phase comparison result of the phase comparator. And a second frequency division ratio control unit that changes the phase of the frequency division output of the second variable frequency divider and synchronizes the frequency division output of the second variable frequency divider with the input signal. A digital PLL circuit. Said second frequency dividing ratio control unit, the first variable frequency divider for dividing the phase difference between the divided output of said second variable frequency divider for division output, before Symbol first variable frequency divider 3. The frequency division ratio of the second variable frequency divider is changed by the number of times the frequency division output is reduced to a value smaller than the phase change amount per cycle of the frequency division output due to the change of the frequency division ratio. Digital PLL circuit. An oscillator that outputs an oscillation signal of a predetermined frequency;
A first variable frequency divider that receives and divides a first clock signal based on an oscillation signal of the oscillator;
A phase comparison that compares the phase of a clock signal based on the frequency-divided output of the first variable frequency divider and a predetermined input signal and outputs a phase comparison result indicating the phase relationship between the two signals for each phase comparison. And
Based on the phase comparison result of the phase comparator, the frequency division ratio of the first variable frequency divider is set to the normal frequency division ratio once before the next phase comparison is performed. When the phase of the clock signal based on the frequency-divided output of one variable frequency divider is ahead of the phase of the input signal, it is changed by +1, and when it is behind, the first variable is changed by -1. A first frequency division ratio controller that changes the phase of the frequency-divided output of the frequency divider and synchronizes the frequency-divided output of the first variable frequency divider with the input signal;
A second clock signal that is synchronized with the first clock signal and has a frequency a times higher than the first clock signal (a is an integer equal to or greater than 2) is input and frequency-divided. A variable divider,
Based on the phase comparison result of the phase comparator, the frequency division ratio of the second variable frequency divider is a times within the time corresponding to one period of the phase comparison, with respect to its normal frequency division ratio, When the phase of the clock signal based on the frequency-divided output of the first variable frequency divider is advanced from the phase of the input signal, it is changed by +1, and when it is delayed, it is changed by -1. A digital frequency divider comprising: a second frequency division ratio control unit that changes the phase of the frequency division output of the variable frequency divider and synchronizes the frequency division output of the second variable frequency divider with the input signal. PLL circuit. An oscillator that outputs an oscillation signal of a predetermined frequency;
A first variable frequency divider that receives and divides a first clock signal based on an oscillation signal of the oscillator;
A phase comparison that compares the phase of a clock signal based on the frequency-divided output of the first variable frequency divider and a predetermined input signal and outputs a phase comparison result indicating the phase relationship between the two signals for each phase comparison. And
Based on the phase comparison result of the phase comparator, the frequency division ratio of the first variable frequency divider is set to the normal frequency division ratio once before the next phase comparison is performed. When the phase of the clock signal based on the frequency-divided output of one variable frequency divider is ahead of the phase of the input signal, it is changed by +1, and when it is behind, the first variable is changed by -1. A first frequency division ratio controller that changes the phase of the frequency-divided output of the frequency divider and synchronizes the frequency-divided output of the first variable frequency divider with the input signal;
A second clock signal that is synchronized with the first clock signal and that has a frequency higher than or equal to that of the first clock signal and that divides the frequency by inputting a second clock signal. Variable dividers of
The frequency division ratio of the second variable frequency divider is temporarily changed by +1 or −1 with respect to the normal frequency division ratio in accordance with the phase comparison result of the phase comparator. And changing the phase of the frequency-divided output of the second variable frequency divider to synchronize the frequency-divided output of the second variable frequency divider with the input signal, the first variable frequency divider min phase difference between the divided output of said second variable frequency divider for division output is phase change amount per one cycle of the divided output by prior Symbol dividing ratio change in the first variable frequency divider of A digital PLL circuit comprising: a second frequency division ratio control unit that executes a change in the frequency division ratio of the second variable frequency divider once every time equal to or longer than a time corresponding to The second variable frequency divider is a clock signal synchronized with the first clock signal, and a second clock signal whose frequency is a times higher than the first clock signal (a is an integer of 2 or more). To divide
The second frequency division ratio control unit is
A first counter that counts up when the phase of the clock signal based on the divided output of the first variable frequency divider is delayed from the phase of the input signal as a result of the phase comparison;
As a result of the phase comparison, a second counter that counts up when the phase of the clock signal based on the frequency-divided output of the first variable frequency divider is ahead of the phase of the input signal;
The count values of the first counter and the second counter are monitored every 1 / a period of the phase comparison period, and when both count values are other than 0, the second monitoring period is until the next monitoring timing. The frequency division ratio of the variable frequency divider is maintained at the normal frequency division ratio, and the count values of both counters are decremented by 1, respectively. When the count value of the first counter is 0 and the count value of the second counter When the value is larger than a predetermined value of 1 or more, the division ratio of the second variable frequency divider is changed by +1 once before the next monitoring timing, and the count value of the second counter is counted down by 1 When the count value of the first counter is larger than a predetermined value of 1 or more and the count value of the second counter is 0, the second variable frequency division is performed once before the next monitoring timing. Change the divider ratio by -1 and The count value of the first counter is decremented by 1, and when the combination of the count values of the two counters is other than that, the division ratio of the second variable frequency divider is set to the normal division until the next monitoring timing. 6. The digital PLL circuit according to claim 5, further comprising a counter monitoring and control unit that maintains the frequency ratio and maintains the count values of both counters as they are.

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