JPH0661848A - Phase lock oscillator - Google Patents

Abstract

PURPOSE:To simply realize a highly accurate PLL by means of a digital circuit. CONSTITUTION:An oscillator is provided with a controlled oscillation circuit 1 comprising a ring oscillator 11 formed by the series connection of N-sets of inverters and comprising a selector SEL 12 selecting one of N-sets of inverter outputs or the like, with a phase comparator circuit 2 and with a control circuit 3. the control circuit 3 generates control outputs of N sets among which one output is active to indicate a selected position to the SEL 12 and uses an SFTB 32 and an REG 34 to shift the active output by M outputs each every time in matching with a frequency of an input reference clock. An SFTC 33 and a REG 35 correct the value M for frequency synchronization and an SFTA 31 synchronizes the phase.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a phase locked oscillator.

[0002]

2. Description of the Related Art A phase-locked oscillator (hereinafter referred to as a PLL) generates an output clock phase-locked with an input reference clock, suppresses phase jitter of the input reference clock, and multiplies the input reference clock. Generally, a PLL is configured by using a phase comparator and a controlled oscillator, but the controlled oscillator normally uses an oscillation circuit by an analog circuit such as a VCXO (voltage controlled crystal oscillator) or an oscillator by a current source and a capacitor. Further, in the past, in some cases, a PLL using a digital circuit that divides an operation clock by a counter to generate an output clock and corrects the count value of the counter at that time to configure a controlled oscillator is also used.

[0003]

The conventional PLL using a digital circuit has a problem that the precision of phase control is not finer than the cycle of the operation clock.

An object of the present invention is to provide a highly accurate PLL using a digital circuit such as an inverter circuit or a flip-flop circuit without using an analog circuit.

[0005]

A phase-locked oscillator (PLL) of the present invention is a ring oscillator in which N (N is an odd number) inverters are connected in series to form a ring, and N inverters of the ring oscillator. And a control oscillation circuit having a selection circuit for selecting one of them as an output clock and selecting one of them as an output clock, and comparing the phase difference between the input reference clock and the output clock of the control oscillation circuit to obtain a comparison result. A phase comparison circuit for outputting and a control circuit for generating a control signal to the control oscillation circuit by using an output of the phase comparison circuit as an input are provided, and an output clock synchronized with the input reference clock is generated. .

The control circuit is constructed so that one of the N control output lines indicates an inverter position to be selected by the selection circuit, and the output clock is the input reference clock. In order to oscillate in the same cycle as the above cycle, the position of the active control output line is changed by M each time so as to select the inverter which is shifted by a fixed amount M each time from the N inverter outputs arranged in the order of phase. It is characterized by including a shift circuit for shifting and a register.

Further, the selection circuit switches the output clock in synchronization with a clock delayed by a delay time corresponding to a plurality of the inverters.

Further, the control circuit corrects the fixed amount M by the phase comparison circuit output in order to frequency synchronize with the input reference clock, or the active control output line is changed by the information of the phase comparison circuit output. It is characterized by having a shift circuit for shifting by ± 1.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a block diagram showing one embodiment of the PLL of the present invention, FIG. 2 is a time chart for explaining the operation principle of the control oscillation circuit in FIG. 1, and FIG. 3 is for explaining the operation of the PLL of this embodiment. Is a time chart of.

As shown in FIG. 1, the PLL of this embodiment comprises a controlled oscillator circuit 1, a phase comparison circuit 2 and a control circuit 3. The control oscillator circuit 1 includes N = 9 inverters 101,
A ring oscillator (to be referred to as an OSC hereinafter) 11 in which ~ 109 are connected in series, and nine inverters 101 of the OSC11, and a selection circuit (to be referred to as a SEL hereinafter) that selects one of the outputs to 109 as an output clock CLK. 12 and SE
A delay circuit (hereinafter, DLY) 13 that creates a switching timing CLKdelay of L12, and a switching timing CLKd.
It is composed of a register (hereinafter referred to as REG) 14 necessary for switching the control of the SEL 12 in synchronization with elay.
The phase comparison circuit 2 compares the phase difference between the input reference clock CLKref and the output clock CLK and outputs the comparison result. The control circuit 3 receives the result of the phase comparison circuit 2 as an input and inputs a control signal to the SEL 12 of the control oscillation circuit 1.

First, the operation of the controlled oscillator circuit will be described in detail with reference to FIG. 9 inverters 101 of FIG.
Outputs P1 to P9 of ~ 109 oscillate as shown in FIG. The delay time around the ring is half the oscillation period.
When the inverter outputs are arranged in the order of # 0, # 8, instead of the order of outputs P1, ..., P9, the phases are arranged in order at the interval of oscillation period / 9. Therefore, considering the # number, SEL1
Considering Modulo 9 in FIG. 2, the phase of the output clock is advanced when the number smaller than the present is selected, and the phase of the output clock is delayed when the number larger than the present is selected. That is, as shown in FIG. 2 for M = -2 and M = 2, the switching timing CLKdela
Considering Modulo 9 in SEL12 for each y, and selecting a number whose # number is smaller by 2 (M =-
In 2), since # 0 → # 7 → # 5 → # 3 is selected, the phase of the output clock advances and the frequency increases. On the other hand, if the # number is increased by 2 each (M
= 2), # 0 → # 2 → # 4 will be selected in order, so
The phase of the output clock is delayed and the frequency is increased.

Here, the DLY 13 creates a switching timing CLKdelay for switching the SEL 12 when the output clock is stable at a high level.

Next, the control circuit 3 will be described. The control circuit 3 is a shift circuit (hereinafter referred to as SFTA, SFTB, SFT).
C) 31, 32, 33 and the register (hereinafter, REG) 34
And 35.

The control circuit 3 receives the output of the phase comparison circuit 2 as an input and performs processing to generate a control signal to the SEL 12. Only one control signal is output and only one corresponding to the position to be selected is active so that one of the N inverter outputs can be selected by the SEL 12. SF
TA31 is a shift circuit for shifting the position of the active control output line by the output number of the phase comparison circuit 2 by ± 1 with the # number of Modulo 9 in order to synchronize the CLKref phase with the input reference clock. Shift the active position of the signal by ± 1. The frequency of the output clock CLK of the SFTB 32 is the input reference clock CLK.
This is a shift circuit for shifting the selection of the # number in the OSC 11 by M times so that it matches the frequency of ref, and the control is performed by inputting N control signal outputs and shifting the position of the active control output line by M. The signal is output to REG34. REG 34 is a register for storing a control signal. REG35 is an input reference clock CLK
It is a register for adaptively correcting the value of M and holding the value for frequency synchronization with ref. If M has m possible values, it is composed of m registers. Only one is active. SF
The TC 33 is a shift circuit for inputting the REG 35, shifting it by ± 1 by the output of the phase comparison circuit 2, and correcting the value of M by ± 1. Since the processing of these circuits is simple and the delay time is small, it is easy to make the processing time shorter than the cycle of the output clock determined by the delay time of the multistage inverter, and a high-speed PLL circuit can be easily realized.

Next, referring to the time chart of FIG.
The operation of the PLL will be described. FIG. 3 shows that the output of the phase comparison circuit 2 determines the same phase from the input reference clock CLKref and the output clock CLK, and as a result, M of the REG 35
Value, # number value of REG34 (A2 point), SFTA3
How the value of # number of 1 output (A1 point) changes and S
It shows what # number is selected by EL12 and what happens to the output clock.

From FIG. 3, the frequency of the output clock CLK is adjusted by setting M to -1 or -2 with respect to the reference clock CLKref having a cycle slightly shorter than the cycle of the ring oscillator 11, and in the SEL 12,
It can be seen that the phases are selected with # 0 → # 7 → # 6 → # 4 and the phases are synchronized with a small phase error. In principle, the phase error can be controlled by the fineness of the delay time of the inverter, and high precision P
LL can be realized.

[0017]

As described above, the present invention has the effect that it is possible to easily realize a highly accurate PLL in which the phase can be controlled by the fineness of the delay time of the inverter circuit by the digital circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL of the present invention.

FIG. 2 is a time chart for explaining the operation principle of the controlled oscillator in FIG.

FIG. 3 is a time chart for explaining the operation of the PLL of this embodiment.

[Explanation of symbols]

1 Controlled Oscillation Circuit 2 Phase Comparison Circuit 3 Control Circuit 11 Ring Oscillator (OSC) 12 Selection Circuit (SEL) 13 Delay Circuit (DLY) 14, 34, 35 Registers (REG) 31, 32, 33 Shift Circuits (SFTA, SFT)
B, SFTC) 101 to 109 Inverter CLKref Input reference clock CLK Output clock

Claims (5)

[Claims] 1. A ring oscillator in which N inverters (N is an odd number) are connected in series to form a ring shape, and respective outputs of the N inverters of the ring oscillator are input, and one of them is selected and output. A control oscillating circuit having a clock selection circuit, a phase comparing circuit for comparing a phase difference between an input reference clock and an output clock of the control oscillating circuit and outputting a comparison result, and an output of the phase comparing circuit And a control circuit for generating a control signal to the control oscillating circuit for generating an output clock synchronized with the input reference clock. 2. The control circuit is configured to indicate an inverter position to be selected by the selection circuit by one active control output line among N control output lines, and the output clock is the input reference clock. In order to oscillate in the same cycle as the above cycle, the position of the active control output line is changed by M each time so as to select the inverter which is shifted by a fixed amount M each time from the N inverter outputs arranged in the order of phase. 2. The phase-locked oscillator according to claim 1, wherein the phase-locked oscillator includes a shift circuit for shifting and a register. 3. The phase-locked oscillator according to claim 1, wherein the selection circuit switches the output clock in synchronization with a clock delayed by a delay time corresponding to a plurality of the inverters. 4. The phase-locked oscillator according to claim 3, wherein the control circuit corrects the constant amount M by the output of the phase comparison circuit in order to frequency synchronize with the input reference clock. 5. The control circuit has a shift circuit for shifting the active control output line by ± 1 according to the information of the output of the phase comparison circuit in order to synchronize the phase with the input reference clock. 3. The phase-locked oscillator according to 3.