KR100189773B1 - Digital phase synchronous circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase synchronizing circuit. The digital phase synchronizing circuit according to the present invention receives a master clock of a predetermined frequency from an external source and outputs a divided signal obtained by dividing the input master clock at a predetermined division ratio. And a delay unit for receiving the division signal output from the division unit, outputting a delay signal for delaying the division signal for a predetermined time, and receiving the delay signal output from the delay unit, and receiving a predetermined feedback signal. A selection output unit for outputting a recovery clock in response thereto, a counter controller for receiving predetermined NRZ data from an external source, a recovery clock output from the selection output unit, and outputting an enable signal and an up-down control signal; The in signal of the recovery clock is input from the selection output unit, and the in is input from the counter controller. And a counter unit for counting the inverted signal of the recovery clock and feedback the output signal to the selection output unit in response to the enable signal and the up-down control signal. By such a device, a digital phase synchronization circuit capable of operating at a high frequency can be realized.

Description

A circuit of digital phase locked loop

The present invention relates to a digital phase synchronization circuit, and more particularly, to a digital phase synchronization circuit that can be implemented even at a high frequency.

A phase locked loop (PLL) consisting of three circuits, a phase comparison circuit, a voltage controlled oscillation circuit, and a low pass filter, includes an FM / PM demodulation circuit, a frequency synthesis circuit, a telemetry transceiver, and a digital It is applied to a wide range of fields such as demodulation of carrier frequency in data transmission. These phase-lock circuits are roughly classified into analog and digital types according to the method of the phase comparison circuit, but the basic functions are the same.

Conventional analog phase synchronization circuits have been applied in many fields in such a way that a large number of frequencies can be easily synchronized. However, such an analog phase synchronizing circuit has a large circuit area, difficulty in measurement and periodic adjustment, and a digital phase synchronizing circuit in which a circuit is replaced by a digital circuit has been proposed and used in recent years.

Conventional digital phase synchronization circuits have a wide range of applications because they are easy to implement as the integration technology develops, and are superior to existing analog phase synchronization circuits. The integration allows the circuit area to be reduced and the power consumption to be reduced, thereby reducing the production cost. In addition, it is possible to process a variety of signals that are difficult to implement in an analog phase-locked circuit. In addition, the use of digital phase synchronization circuits has recently been in the spotlight because the difficulty of measurement and periodic adjustment, which are a problem in analog phase synchronization circuits, can be solved.

However, such a conventional digital phase synchronization circuit divides the master clock input from the outside at a predetermined division ratio to produce a recovery clock. The frequency of the input master clock is several ten times higher than the frequency of the recovery clock to be obtained. Only a few hundred times the high frequency signal could function properly. Therefore, when the frequency of the recovery clock to be obtained has a high frequency equal to the frequency of the master clock, there is a problem in that it does not function.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a digital phase lock circuit capable of operating at a high frequency having the same frequency as a master clock to which a recovery clock is input.

1 shows schematically a digital phase locked circuit according to an embodiment of the invention;

2 is a view showing the configuration of a counter control unit according to an embodiment of the present invention;

3A-3B are timing diagrams illustrating the operation of a digital phase lock circuit in accordance with an embodiment of the invention.

Explanation of symbols on the main parts of the drawings

10: dispensing unit 20: delay unit

30: selective output unit 40: counter control unit

50: counter part 60, 70, 80: D flip-flop

90: end gate

(Configuration)

According to a feature of the present invention for achieving the above object, in a digital phase synchronization circuit for recovering a clock component from data received in data communication, the digital phase synchronization circuit inputs a master clock of a predetermined frequency from an external source. A divider which receives a divided signal obtained by dividing the input master clock at a predetermined division ratio, and the division signal outputted from the division portion, and outputs a delayed signal that delays the divided signal for a predetermined time period. And a selection output unit for receiving the delay signal output from the delay unit, outputting a recovery clock in response to a predetermined feedback signal, and receiving predetermined NRZ data from an external device and outputting the predetermined NRZ data. A counter controller for receiving a recovery clock and outputting an enable signal and an up-down control signal; A counter unit which receives an inverted signal of a recovery clock from an output unit, counts an inverted signal of the recovery clock and feeds it back to the selection output unit in response to the enable signal and an up-down control signal input from the counter control unit; It is configured by.

In a preferred embodiment of this aspect, the counter control unit receives first NRZ data from an external source and outputs the NRZ data by delaying the NRZ data for a predetermined time in response to a recovery clock input from the selection output unit. Second delay means for receiving the recovery clock from the selection output unit, delaying the recovery clock for a predetermined time in response to predetermined NRZ data input from the outside, and outputting the up-down control signal; Inverting means for receiving an output signal of the delay means and inverting and outputting the output signal of the first delay means in response to a recovery clock input from the selection output section; and each output of the first delay means and the inverting means; And an AND gate configured to combine the signals to output the enable signal. In a preferred embodiment of this aspect, the first and second delay means and the inverting means each consist of a D flip-flop.

(Action)

By such a device, it is possible to implement a digital phase synchronizing circuit capable of operating even at a high frequency at which the recovery clock frequency is the same as that of the master clock as the input signal.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 3.

Referring to FIG. 1, a novel digital phase synchronization circuit according to a preferred embodiment of the present invention includes a divider for dividing a master clock input from the outside at a predetermined division ratio, and a delay for a predetermined time from an output signal of the divider. A delay unit, a selection output unit which receives an output signal of the delay unit, outputs a recovery clock in response to a predetermined feedback signal, receives predetermined NRZ data from an external source, receives the recovery clock, and an enable signal; A counter controller for outputting an up-down control signal and an inverted signal of the recovery clock, and counting the inverted signal of the recovery clock in response to the enable signal and the up-down control signal, and outputting the feedback signal to the selection output unit; It is comprised including the counter part. By such a device, it is possible to implement a digital phase lock circuit capable of obtaining a recovery clock having a frequency as high as the input master clock.

1 is a block diagram schematically showing a configuration of a digital phase synchronization circuit according to an embodiment of the present invention.

Referring to FIG. 1, reference numeral 10 denotes a divider which receives a master clock MCLK having a predetermined frequency from the outside and divides the master clock MCLK at a predetermined division ratio M, and 20 denotes the division. Delay unit for delaying the output signal of the main unit 10 by a predetermined time and output, 30 is a selective output unit for selecting and outputting one of the plurality of output signals output from the delay unit 20, 40 is A counter control unit receives the recovery clock RCLK and a predetermined non return zero (NRZ) signal and generates an enable signal and an up-down control signal (UP / DOWN), and 50 is the counter control unit 40. The counter unit performs a counter operation in response to the enable signal ENABLE and the up-down control signal UP / DOWN.

The operation of the digital phase synchronization circuit according to the embodiment of the present invention will be described with reference to FIG. 1.

First, the frequency division unit 10 divides the master clock MCLK input from the outside into a predetermined division ratio M in order to match the frequency of the recovery clock to be obtained. The divided signal is inputted to the delay unit 20 and delayed for a predetermined time through 2 ^N -1 delay elements having a minimum jitter time. Here, the number of delay elements is determined by dividing the delay element time in the recovery clock period, and always sets the number of 2 ^N −1. For example, if the minimum jitter is 2nS and the frequency of the recovery clock is 20MH _Z , then the period of the recovery clock is 50nS divided by the minimum jitter time to be 25. Therefore, 31 delay elements having a delay time of 2 nS are required for N = 5. If N = 4, 16 becomes lower than 25, and thus N is determined as the smallest N larger than the divided number.

Subsequently, the output of the delay unit 20 is 2 ^N , and each output is input to the selection output unit 30 by being distributed at intervals of minimum jitter up to a clock delayed by at least one cycle with respect to the center clock. These clocks are selected by the selection output unit 30 according to a predetermined control signal, and the input master clock MCLK and the recovery clock RCLK are output in synchronization with each other.

Next, the counter control unit 40 and the counter unit 50 serve to control the selection output unit 30, and the counter unit 50 operates up and down, and the operation is input from the counter control unit 40. It is determined by comparing the recovered data and the recovery clock RCLK. For example, when N = 5, when the initialization signal RESET is applied, the counter unit 50 is fixed to the center value 01111, and the recovery clock RCLK is the center clock among the outputs of the delay unit 20. do. The up-down is determined by the clock and the up-down control signal UP / DOWN input from the counter controller 40. Accordingly, the counter unit 50 becomes 10000 when it is up, and the selection output unit 30 outputs a clock delayed one step further from the output signals of the delay unit 20 to the recovery clock RCLK. In the case of down, the counter unit 50 becomes 01110, and the selection output unit 30 outputs the clock delayed by one step to the recovery clock RCLK. By repeating this process, the input signal MCLK and the recovery clock RCLK are synchronized with each other on the rising edge, and the counter unit 50 recovers the clock component from the input signal MCLK while repeating up and down in sequence.

2 shows the configuration of the counter control unit 40 according to the embodiment of the present invention. In the present invention, the D flip-flop and the AND gate are used.

Referring to FIG. 2, reference numeral 60 denotes inputting a predetermined NRZ data to an input terminal D, and delaying and outputting the NRZ data for a predetermined time in response to a recovery clock RCLK input to a clock terminal CLK. First delay means, 70 is the recovery clock (RCLK) is input to the input terminal (D), the recovery clock (RCLK) is delayed for a predetermined time in response to the NRZ data input to the clock terminal (CLK) up-down control A second delay means for outputting a signal, and 80 denotes an output signal of the first delay means 60 through an input terminal D, and in response to a recovery clock RCLK input to a clock terminal CLK. Inverting means for inverting and outputting the output signal of the first delay means 60, 90 is a combination of the output signal of the first delay means 60 and the inverting means 80 to enable the enable signal (ENABLE) The end gate is generated.

3A to 3B are timing diagrams illustrating an operation of a digital phase synchronization circuit according to an exemplary embodiment of the present invention, in which FIG. 3A is a case in which the counter unit 50 is up, and FIG. 3B is a case in which the counter unit 50 is down. Is shown.

Referring to FIG. 3A, a rising edge of NRZ data occurs when the recovery clock RCLK is high. In this case, only one clock goes high between the rising edge of the recovery clock RCLK and the enable signal ENABLE. Then, the up-down control signal UP / DOWN is up, and this signal is input to the selection output unit 30 to output a clock delayed by one step.

Referring to FIG. 3B, the rising edge of the NRZ data is shown when the recovery clock RCLK is low. In this case, the up-down control signal UP / DOWN goes down at the rising edge of the NRZ data, and this signal is input to the selection output section 30 to output a clock one step ahead.

Conventional digital phase synchronization circuit has a problem that can operate only when the frequency of the input signal is several tens or more times the frequency of the recovery clock.

The present invention for solving such a problem comprises a digital phase synchronizing circuit capable of operating at high frequency, including a frequency divider, a delay unit, a selective output unit, a counter control unit, and a counter unit.

Accordingly, the digital phase synchronization circuit can be operated not only when the frequency of the recovery clock to be obtained is smaller than that of the input signal but also in the same case. And by implementing all the parts of the circuit in digital logic, it is possible to save considerable area when used in integrated circuits.

Claims (3)

In a digital phase synchronization circuit for recovering a clock component from data received in data communication, The digital phase synchronization circuit, A divider unit 10 which receives a master clock MCLK of a predetermined frequency from the outside and outputs a divided signal obtained by dividing the input master clock MCLK at a predetermined division ratio M; A delay unit (20) for receiving the divided signal outputted from the frequency division unit (10) and outputting a delay signal for delaying the frequency division signal for a predetermined time period; A selection output unit 30 which receives the delay signal output from the delay unit 20 and outputs a recovery clock RCLK in response to a predetermined feedback signal; A counter controller for receiving predetermined NRZ data from an external source, receiving a recovery clock RCLK output from the selection output unit 30, and outputting an enable signal ENABLE and an up-down control signal UP / DOWN; 40); In response to the inverted signal of the recovery clock RCLK received from the selection output unit 30 and in response to the enable signal ENABLE and the up-down control signal UP / DOWN, which are input from the counter controller 40, Counter unit 50 for counting the inverted signal of the recovery clock (RCLK) and feedback output to the selection output unit 30 Digital phase synchronization circuit comprising a. The method of claim 1, The counter control unit 40, First delay means (60) for receiving predetermined NRZ data from the outside and delaying and outputting the NRZ data for a predetermined time in response to a recovery clock (RCLK) input from the selection output section (30); The recovery clock RCLK is input from the selection output unit 30, and the recovery clock RCLK is delayed by a predetermined time in response to predetermined NRZ data input from the outside, so that the up-down control signal UP / DOWN is received. Second delay means (70) for outputting; An inversion for receiving the output signal of the first delay means 60 and inverting and outputting the output signal of the first delay means 60 in response to the recovery clock RCLK input from the selection output unit 30. Means (80); And gate 90 for outputting the enable signal (ENABLE) by combining the respective output signals of the first delay means 60 and the inverting means 80 Digital phase synchronization circuit comprising a. The method of claim 2, And said first and second delay means (60, 70) and said inverting means (80) are each composed of D flip-flops.