US7599457B2 - Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits - Google Patents
Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits Download PDFInfo
- Publication number
- US7599457B2 US7599457B2 US11/199,287 US19928705A US7599457B2 US 7599457 B2 US7599457 B2 US 7599457B2 US 19928705 A US19928705 A US 19928705A US 7599457 B2 US7599457 B2 US 7599457B2
- Authority
- US
- United States
- Prior art keywords
- clock
- data
- phase
- signal
- offset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
Definitions
- the present invention relates to electronics, and, in particular, to clock-and-data-recovery circuits.
- a receiver can perform clock-and-data-recovery (CDR) processing to recover a clock signal from each data stream, where the clock signal is derived based on the timing of the data represented in the data stream.
- CDR clock-and-data-recovery
- a typical CDR circuit comprises a sampling clock generator, such as a phase-locked loop (PLL) or a delay-locked loop (DLL), that generates one or more sampling clocks used to sample the received data stream.
- PLL phase-locked loop
- DLL delay-locked loop
- a single receiver may receive multiple, different data streams, potentially having different data rates. Such a receiver will typically have a different CDR circuit for each different data stream. Implementing multiple CDR circuits, each with its own sampling clock generator can require too much layout area and/or operating power for some integrated circuit applications.
- the present invention is a clock-and-data recovery system, comprising a clock generator and one or more channel circuits.
- the clock generator generates a plurality of phase-offset clock signals
- each channel circuit generates an output data stream and a recovered clock signal based on an input data signal.
- Each channel circuit comprises a data for each phase-offset clock signal, a logic circuit, and a data sampler.
- Each data register generates an output signal based on the level of the corresponding phase-offset clock signal at a transition in the input data signal.
- the logic circuit processes the output signals from the data registers to select one of the phase-offset clock signals as a sampling clock signal, and the data sampler samples the input data signal based on the sampling clock signal to generate the output data stream and generates the recovered clock signal based on the sampling clock signal.
- the present invention is a clock-and-data recovery system, comprising a clock generator and two or more channel circuits coupled to the clock generator.
- the clock generator generates a plurality of phase-offset clock signals.
- Each channel circuit generates an output data stream and a recovered clock signal based on an input data signal and the plurality of phase-offset clock signals.
- FIG. 1 is a block diagram of a clock-and-data-recovery system, according to one embodiment of the present invention
- FIG. 2 is a more-detailed block diagram of one possible implementation of the CDR system of FIG. 1 ;
- FIG. 3 shows an exemplary timing diagram illustrating the relationship between the input data signal and the sixteen clock signals of FIG. 2 .
- FIG. 1 is a block diagram of a clock-and-data-recovery system 100 , according to one embodiment of the present invention.
- CDR system 100 has a multi-phase clock generator 102 and N CDR channel circuits 104 , where N ⁇ 1.
- Clock generator 102 generates a multi-phase set of clock signals 106 (i.e., multiple versions of a clock signal sequentially separated from each other in phase over one clock period by a specified phase-offset increment). For example, in one implementation, clock generator 102 generates 16 clock signals, each having the same frequency, but separated in phase from the previous clock signal by about 22.5 degrees. Clock signals 106 are all applied to each CDR channel circuit 104 , which uses the set of clock signals to generate a (different) recovered clock signal 110 and a (different) output data stream 112 from a corresponding (different) input data signal 108 , potentially having different data rates.
- FIG. 2 is a more-detailed block diagram of one possible implementation of CDR system 100 of FIG. 1 .
- FIG. 2 shows only one CDR channel circuit 104 , the implementation may include other, similar CDR channel circuits.
- multi-phase clock generator 102 is a delay-locked loop (DLL) that is capable of selectively generating either 16 clock signals (separated by phase-offset increments of about 22.5 degree) or 8 clock signals (separated by phase-offset increments of about 45 degrees).
- a received reference clock (REFCLK) is applied to the first delay element in delay chain 204 , where each delay element in the chain delays the reference clock by an incremental amount of time, which corresponds to a reasonably predictable amount of phase for a given clock rate.
- Each clock signal 106 corresponds to the output of (a different) one of the delay elements in delay chain 204 , as selected using a corresponding multiplexer (not shown) in delay chain 204 .
- the number of delay elements in delay chain 204 and the number of clock signals output from delay chain 204 are metal mask programmable.
- delay chain 204 receives, from PD/ALU 202 , 16 DelNumber values, each of which dictates the number of delay elements in delay chain 204 between a different pair of successive clock signals 106 .
- reference clock REFCLK has a period of 100 nsec
- each delay element in delay chain 204 delays the reference clock by 1 nsec (i.e., corresponding to a phase shift of about 3.6 degrees)
- clock generator 102 is configured to generate 16 clock signals.
- the sixteen clock signal 106 would be selected to be the output from the 100 th (i.e., 6+6+7+6+6+6+7+6+6+6+7+6+6+6+7+6+6+7+6) delay element in delay chain 204 , where that sixteenth clock signal corresponds to reference clock REFCLK delayed by 100 nsec (i.e., one complete 360-degree clock cycle of REFCLK).
- the 8 clock signals 106 could be generated using (12, 13, 12, 13, 12, 13, 12, 13) as the 8 DelNumber values, where the eighth clock signal would correspond to reference clock REFCLK delayed by one complete clock cycle.
- the values used in these examples are for purposes of explanation only; actual values may be larger or smaller.
- the last selected clock (i.e., either the sixteenth clock signal or the eighth clock signal, depending on whether clock generator 102 is configured to generate 16 or 8 clock signals) is fed back from delay chain 204 as feedback clock signal DelClk to PD/ALU 202 , which also receives reference clock REFCLK.
- PD/ALU 202 generates the phase difference between REFCLK and DelClk and uses that phase difference to adjust the DelNumber values as necessary to ensure that those two clock signals are as close to being in phase (i.e., separated by one complete clock cycle of REFCLK) as possible.
- PD/ALU 202 sets the 1-bit status signal MASTER LOCK to a value (e.g., 1) that indicates that clock signals 106 are valid.
- CDR channel circuit 104 receives input data signal 108 and (up to) 16 clock signals 106 , referred to as CLK 0 -CLK 15 .
- CDR channel circuit 104 has 16 data registers 206 (e.g., flip-flops, although other types of data registers are possible) arranged in two banks 208 and 210 , where input data signal 108 is applied to the clock input of each flip-flop.
- each of the first eight clock signals CLK 0 -CLK 7 is applied to the data input of a different flip-flop.
- bank 210 also has a (2 ⁇ 1) multiplexer (mux) 212 for each flip-flop, where one of the second eight clock signals CLK 8 -CLK 15 is applied to the “0” input of each mux 212 and a corresponding one of the first eight clock signals CLK 0 -CLK 7 is applied to the mux's “1” input.
- the output of each mux 212 is applied to the data input of the corresponding flip-flop 206 , where the selection of which received clock signal to apply is dictated by control signal CLK_WIDTH.
- both the first flip-flop (in bank 208 ) and the eighth flip-flop (in bank 210 ) receive clock signal CLK 0 , and analogously for clock signals CLK 1 -CLK 7 and the other seven pairs of flip-flops in banks 208 and 210 .
- each flip-flop when CDR system 100 is configured in its 16-phase mode, a different one of the 16 clock signals CLK 0 -CLK 15 is applied to the data input of a different one of the 16 flip-flops 206 , while input data signal 108 is applied to the clock input of each flip-flop.
- flip-flops 206 are triggered by rising edges (in alternative implementations, falling-edge-triggered flip-flops could be used)
- input data signal 108 e.g., corresponding to a data transition from a “0” to a “1”
- each flip-flop will (substantially) simultaneously present the current value of its received clock signal CLKi as its output value Qi.
- clock signals CLK 0 -CLK 15 represent a sequence of increasingly phase-offset clock signals, eight consecutive clock signals 106 will be either high or low and the rest will be the opposite.
- FIG. 3 shows an exemplary timing diagram illustrating the relationship between input data signal 108 and the sixteen clock signals CLK 0 -CLK 15 .
- the portion of input data signal 108 shown in FIG. 3 corresponds to a bit sequence of (0 1 0 0 1) and has rising transitions at times t 1 and t 3 and a falling transition at time t 2 .
- clocks CLK 0 -CLK 2 and CLK 11 -CLK 15 are high and eight consecutive clocks CLK 3 -CLK 10 are low.
- clock selector logic 214 analyzes the 16 Qi values to select one of clock signals CLKi as selected clock 216 for input to processing block 218 .
- clock selector logic 214 selects a clock 180 degrees away (e.g., CLK 11 ) for use as selected clock 216 . If the transition were a 0-to-1 transition, then clock selector logic 214 would select one of the clocks corresponding to the transition, rather than looking 180 degrees away.
- processing block 218 receives input data signal 108 and control signal BIT_WIDTH.
- processing block 218 samples input data signal 108 at every rising edge of selected clock 216 to generate sampled data.
- processing block 218 is capable of outputting the sampled data as a serial or parallel data stream, where the parallelism of output data stream 112 is controlled by the value of control signal BIT_WIDTH, such that output data stream 112 can be up to 4 bits wide.
- processing block 218 has a clock divider that divides selected clock 216 by the same value dictated by the BIT_WIDTH control signal to generate recovered clock signal 110 as a divided version of selected clock 216 .
- downstream digital logic e.g., used to decode the output data
- downstream digital logic is able to run at a lower frequency.
- a first-in, first-out (FIFO) buffer can be used to re-time the data to make chip routing less of an issue.
- CDR system 100 of FIG. 2 When CDR system 100 of FIG. 2 is configured in its 8-phase mode, only eight different clock signals CLK 0 -CLK 7 are generated by clock generator 102 and input to each CDR channel circuit 104 .
- muxes 212 are controlled by CLK_WIDTH to select the “1” inputs for application to the data inputs of the flip-flops in bank 210 .
- Q 0 and Q 8 provide substantially redundant information, which clock selector logic 214 can use to increase the reliability of its processing.
- CDR channel circuit 104 can operate at a higher frequency than during the 16-phase mode.
- the maximum frequency of the clock generator is a function of the number of phases and the intrinsic delay of each delay element. For example, if each delay element has a minimum delay of 1 ns, then the maximum frequency of clock generator 102 for the 16-phase mode would be 1/(16 ns) or about 62.5 MHz. For the 8-phase mode, however, the maximum frequency of the clock generator would be 1/(8 ns) or about 125 MHz.
- the frequency of input data signal 108 is the same as the frequencies of clock signals CLK 0 -CLK 15 .
- clock selector logic 214 may need to constantly change which clock signal is used for selected clock 216 .
- clock selector logic 214 there are limits placed on which clock signals can be selected by clock selector logic 214 .
- clock selector logic 214 can change the selected clock by at most one clock signal in either direction from the previously selected clock signal. If the desired change is greater than the specified limit, then the control loop is not correctly locked to the data, and lock signal LOCK is set low by clock selector logic 214 .
- the present invention has been described in the context of a CDR system in which a multi-phase DLL is used to generate the phase-offset clock signals, in other embodiments, other types of multi-phase clock generators can be used, including multi-phase voltage-controlled oscillators (VCOs). Furthermore, although the present invention has been described in the context of a CDR system capable of generating either 8 or 16 different clock signals, other embodiments may generate other numbers of phase-offset clock signals, including only one number of clock signals or more than two different numbers of clock signals.
- VCOs voltage-controlled oscillators
- circuits including possible implementation as a single integrated circuit, a multi chip module, a single card, or a multi card circuit pack
- present invention is not so limited.
- various functions of circuit elements may also be implemented as processing blocks in a software program.
- Such software may be employed in, for example, a digital signal processor, micro controller, or general purpose computer.
- each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range.
Abstract
Description
Claims (11)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/199,287 US7599457B2 (en) | 2005-08-08 | 2005-08-08 | Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits |
PCT/US2006/030501 WO2007019339A2 (en) | 2005-08-08 | 2006-08-07 | Clock-and-data-recovery system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/199,287 US7599457B2 (en) | 2005-08-08 | 2005-08-08 | Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
US20070030936A1 US20070030936A1 (en) | 2007-02-08 |
US7599457B2 true US7599457B2 (en) | 2009-10-06 |
Family
ID=37717592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/199,287 Active 2027-09-30 US7599457B2 (en) | 2005-08-08 | 2005-08-08 | Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits |
Country Status (2)
Country | Link |
---|---|
US (1) | US7599457B2 (en) |
WO (1) | WO2007019339A2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090080584A1 (en) * | 2007-09-21 | 2009-03-26 | Hitachi, Ltd. | Semiconductor system |
US20100142967A1 (en) * | 2008-12-10 | 2010-06-10 | Ronald Edward Perez | Reference Clock Rate Detection for Variable Rate Transceiver Modules |
US8564330B1 (en) * | 2012-06-05 | 2013-10-22 | Xilinx, Inc. | Methods and systems for high frequency clock distribution |
US9191020B2 (en) | 2014-02-05 | 2015-11-17 | Waveworks, Inc. | Traveling-wave based high-speed sampling systems |
TWI559684B (en) * | 2012-11-20 | 2016-11-21 | 輝達公司 | A matrix phase detector |
US10225068B2 (en) * | 2016-10-28 | 2019-03-05 | Fujitsu Limited | Clock recovery circuit, semiconductor integrated circuit device and radio frequency tag |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8718087B1 (en) | 2006-10-24 | 2014-05-06 | Marvell International Ltd. | Processing architecture for passive optical network |
US8014481B1 (en) * | 2006-11-13 | 2011-09-06 | Marvell International Ltd. | Upstream data recovery and data rate detection |
US9178713B1 (en) | 2006-11-28 | 2015-11-03 | Marvell International Ltd. | Optical line termination in a passive optical network |
WO2008104958A2 (en) * | 2007-03-01 | 2008-09-04 | Nxp B.V. | Data recovery system and method |
US7586344B1 (en) | 2007-10-16 | 2009-09-08 | Lattice Semiconductor Corporation | Dynamic delay or advance adjustment of oscillating signal phase |
US8634503B2 (en) * | 2011-03-31 | 2014-01-21 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Fast lock clock-data recovery for phase steps |
TWI637186B (en) * | 2017-03-28 | 2018-10-01 | 奇景光電股份有限公司 | Method and circuit for detecting abnormal clock |
CN108037332B (en) * | 2017-12-29 | 2023-11-07 | 陕西海泰电子有限责任公司 | Multi-channel reference clock generation module |
JP2022132859A (en) * | 2021-03-01 | 2022-09-13 | 富士通株式会社 | Optical transmission device and optical transmission system |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5920897A (en) * | 1996-08-07 | 1999-07-06 | Seeq Technology, Incorporated | Apparatus and method for providing multiple channel clock-data alignment |
US6215737B1 (en) * | 1997-05-05 | 2001-04-10 | Wea Manufacturing, Inc. | Using different sampling rates to record multi-channel digital audio on a recording medium and playing back such digital audio |
US6266799B1 (en) | 1997-10-02 | 2001-07-24 | Xaqti, Corporation | Multi-phase data/clock recovery circuitry and methods for implementing same |
US6292116B1 (en) * | 1999-05-17 | 2001-09-18 | Altera Corporation | Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit |
US20020080899A1 (en) * | 2000-11-10 | 2002-06-27 | Fyvie Clifford D. | Arrangement for capturing data |
US20030188235A1 (en) * | 2002-02-21 | 2003-10-02 | Minoru Kozaki | Multi-phase clock generation circuit and clock multiplication circuit |
US20040017243A1 (en) * | 2002-07-19 | 2004-01-29 | Nec Corporation | Multi-phase clock generation circuit |
US6711716B1 (en) * | 2002-09-26 | 2004-03-23 | Agilent Technologies, Inc. | Metal programmable clock distribution for integrated circuits |
US6753712B2 (en) * | 2002-05-17 | 2004-06-22 | Nec Electronics Corporation | Clock and data recovery circuit and clock control method thereof |
US6856661B2 (en) | 2001-03-08 | 2005-02-15 | Texas Instruments Incorporated | Using phase interpolator information to detect a loss of lock condition during recovery of a clock signal from a received data stream |
-
2005
- 2005-08-08 US US11/199,287 patent/US7599457B2/en active Active
-
2006
- 2006-08-07 WO PCT/US2006/030501 patent/WO2007019339A2/en active Application Filing
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5920897A (en) * | 1996-08-07 | 1999-07-06 | Seeq Technology, Incorporated | Apparatus and method for providing multiple channel clock-data alignment |
US6215737B1 (en) * | 1997-05-05 | 2001-04-10 | Wea Manufacturing, Inc. | Using different sampling rates to record multi-channel digital audio on a recording medium and playing back such digital audio |
US6266799B1 (en) | 1997-10-02 | 2001-07-24 | Xaqti, Corporation | Multi-phase data/clock recovery circuitry and methods for implementing same |
US6292116B1 (en) * | 1999-05-17 | 2001-09-18 | Altera Corporation | Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit |
US20020080899A1 (en) * | 2000-11-10 | 2002-06-27 | Fyvie Clifford D. | Arrangement for capturing data |
US6856661B2 (en) | 2001-03-08 | 2005-02-15 | Texas Instruments Incorporated | Using phase interpolator information to detect a loss of lock condition during recovery of a clock signal from a received data stream |
US20030188235A1 (en) * | 2002-02-21 | 2003-10-02 | Minoru Kozaki | Multi-phase clock generation circuit and clock multiplication circuit |
US6753712B2 (en) * | 2002-05-17 | 2004-06-22 | Nec Electronics Corporation | Clock and data recovery circuit and clock control method thereof |
US20040017243A1 (en) * | 2002-07-19 | 2004-01-29 | Nec Corporation | Multi-phase clock generation circuit |
US6711716B1 (en) * | 2002-09-26 | 2004-03-23 | Agilent Technologies, Inc. | Metal programmable clock distribution for integrated circuits |
Non-Patent Citations (1)
Title |
---|
"Data Recovery," by Nick Sawyer, Xilinx, XAPP224, v2.4, Jan. 24, 2005. |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090080584A1 (en) * | 2007-09-21 | 2009-03-26 | Hitachi, Ltd. | Semiconductor system |
US20100142967A1 (en) * | 2008-12-10 | 2010-06-10 | Ronald Edward Perez | Reference Clock Rate Detection for Variable Rate Transceiver Modules |
US8005370B2 (en) * | 2008-12-10 | 2011-08-23 | Applied Micro Circuits Corporation | Reference clock rate detection for variable rate transceiver modules |
US8564330B1 (en) * | 2012-06-05 | 2013-10-22 | Xilinx, Inc. | Methods and systems for high frequency clock distribution |
TWI559684B (en) * | 2012-11-20 | 2016-11-21 | 輝達公司 | A matrix phase detector |
US9191020B2 (en) | 2014-02-05 | 2015-11-17 | Waveworks, Inc. | Traveling-wave based high-speed sampling systems |
US10225068B2 (en) * | 2016-10-28 | 2019-03-05 | Fujitsu Limited | Clock recovery circuit, semiconductor integrated circuit device and radio frequency tag |
Also Published As
Publication number | Publication date |
---|---|
US20070030936A1 (en) | 2007-02-08 |
WO2007019339A3 (en) | 2008-01-03 |
WO2007019339A2 (en) | 2007-02-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7599457B2 (en) | Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits | |
US7366267B1 (en) | Clock data recovery with double edge clocking based phase detector and serializer/deserializer | |
US8559582B2 (en) | Techniques for varying a periodic signal based on changes in a data rate | |
US7826583B2 (en) | Clock data recovery apparatus | |
US8315349B2 (en) | Bang-bang phase detector with sub-rate clock | |
US6937685B2 (en) | Apparatus and method for counting high-speed early/late pulses from a high speed phase detector using a pulse accumulator | |
US8798223B2 (en) | Clock and data recovery unit without an external reference clock | |
CN112042125A (en) | Method and circuit for fine control of phase/frequency offset in phase locked loop | |
JP2005005999A (en) | Clock and data recovery circuit | |
EP1746724A1 (en) | Equiphase polyphase clock signal generator circuit and serial digital data receiver circuit using the same | |
JP2007215213A (en) | System and method for multiple-phase clock generation | |
US8023605B2 (en) | Oversampling circuit and oversampling method | |
JP2014222872A (en) | System and method for tracking received data signal with clock data recovery circuit | |
US7157953B1 (en) | Circuit for and method of employing a clock signal | |
US9438272B1 (en) | Digital phase locked loop circuitry and methods | |
US6477657B1 (en) | Circuit for I/O clock generation | |
US6933761B2 (en) | Techniques for dynamically selecting phases of oscillator signals | |
US8355478B1 (en) | Circuit for aligning clock to parallel data | |
CN111817712B (en) | Phase-based frequency divider, phase-locked loop, chip, electronic device and clock generation method | |
JP2014225874A (en) | System and method for obtaining reception data signal with clock data recovery circuit | |
JPH09149018A (en) | Bit phase synchronization circuit | |
US7151810B2 (en) | Data and clock synchronization in multi-channel communications | |
US8406258B1 (en) | Apparatus and methods for low-jitter transceiver clocking | |
KR100189773B1 (en) | Digital phase synchronous circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: LATTICE SEMICONDUCTOR CORPORATION, OREGON Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JOHNSON, PHILLIP;CHEN, ZHENG;BRITTON, BARRY;REEL/FRAME:016672/0735;SIGNING DATES FROM 20050722 TO 20050805 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: JEFFERIES FINANCE LLC, NEW YORK Free format text: SECURITY INTEREST;ASSIGNORS:LATTICE SEMICONDUCTOR CORPORATION;SIBEAM, INC.;SILICON IMAGE, INC.;AND OTHERS;REEL/FRAME:035223/0001 Effective date: 20150310 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: DVDO, INC., OREGON Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC;REEL/FRAME:049827/0326 Effective date: 20190517 Owner name: SILICON IMAGE, INC., OREGON Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC;REEL/FRAME:049827/0326 Effective date: 20190517 Owner name: LATTICE SEMICONDUCTOR CORPORATION, OREGON Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC;REEL/FRAME:049827/0326 Effective date: 20190517 Owner name: SIBEAM, INC., OREGON Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC;REEL/FRAME:049827/0326 Effective date: 20190517 Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINIS Free format text: SECURITY INTEREST;ASSIGNOR:LATTICE SEMICONDUCTOR CORPORATION;REEL/FRAME:049980/0786 Effective date: 20190517 Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT, COLORADO Free format text: SECURITY INTEREST;ASSIGNOR:LATTICE SEMICONDUCTOR CORPORATION;REEL/FRAME:049980/0786 Effective date: 20190517 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |