JPH09149018A - Bit phase synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the bit phase synchronization circuit taking bit phase synchronization very quickly with a simple configuration even when reception data are received at any phase. SOLUTION: A timing discrimination circuit 5 receives reception data whose phase is unknown and receives 3-phase clock from a reset voltage controlled oscillator(VCO)4 and when the received 3-phase clock 0 is proper with respect to a phase relation of data, the clock is unchanged and when improper, whether the clock phase is to be led or delayed is discriminated, the result is outputted as a discrimination result signal and given to a discrimination result signal input terminal of a selector control circuit 6. The timing discrimination circuit 5 latches the received data based on the 3-phase clock 0, the latch output is outputted from a data output terminal and the output data are given to a reproduction data output terminal 8. Simultaneously the clock used to latch the input reception data is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit phase synchronization circuit, and is suitable for bit phase synchronization in high speed data transmission such as a transmission system and a switching system.

[0002]

2. Description of the Related Art Generally, as a technique of a bit phase synchronizing circuit, for example, there is a method of selecting a clock of a phase whose timing with data is judged to be proper from a multiphase clock. The outline of the technique of this system will be described with reference to the explanatory diagram of FIG. In FIG. 2, the multiphase clock is input to the selector circuit A, and the selector circuit A outputs one of the multiphase clocks input according to the selector control signal, and the clock is the timing determination circuit B.
And the received data is input to the timing determination circuit B. The timing judgment circuit B judges whether or not the timings of the input clock and the input data are proper, outputs the judgment result signal, and the judgment result signal is input to the clock selection control circuit C. This clock selection control circuit C
Then, a selector control signal is generated from the determination result signal and output to the selector circuit A. Bit phase synchronization is established by repeating such operations.

[0003]

However, in the above-mentioned conventional circuit configuration, since the clock is switched by the selector circuit A, noise is superimposed on the clock in general selector control, and this is prevented. In order to achieve this, it is necessary to complicate the selector control and elaborately make the clock selection control circuit and the selector circuit for timing adjustment, and such a technology is extremely difficult. There is a problem that is very difficult.

Recently, the construction of a communication system to which the last transmission is applied has been proposed. For example, the following documents are examples of such a proposal. References: IEICE, September 1995 Technical Research Report, SSE95-83, IN-95-54, CS95-
103, "Bit synchronization circuit for burst transmission in high-speed PDS system", Atsushi Iwamura, Yoshihiro Ashi.

In such a conventional technique, a high-speed clock that is an integral multiple of the transmission rate is divided to generate a multi-phase clock, and after the reset signal is input, transmission data is sampled by the multi-phase clock and The change point of the transmission data was detected from the sampling data, and the data sampled at the phase judged to be stable from the result was selected.

However, since the circuit having the above configuration requires a high-speed clock that is an integral multiple of the transmission rate,
High-speed devices that form circuits in LSIs and the like inevitably become expensive.

Further, the bit phase synchronization operation is reset by a reset signal input to the boundary of the burst cell, the bit phase synchronization is established by the change point of the burst cell input thereafter, and the next reset signal is input. Since that state is held until, the clock frequency used in the bit phase synchronization circuit is matched with the transmission rate with high accuracy, or the cell length of the burst cell is set short so that loss of synchronization does not occur due to the frequency difference. It was necessary to do.

For this reason, it has been required that bit phase synchronization for burst data, which is more severe than that for continuous transmission data, can be performed in a very short cycle.

From the above, no matter what phase the received data is taken in, it outputs the synchronous data and the synchronous clock with a simple structure, very quickly and stably with bit phase synchronization. It is required to provide a bit phase synchronization circuit that can do this.

[0010]

Accordingly, a first aspect of the present invention provides
Received data and a times the bit rate of this received data (a
Is a natural number) or in a bit phase synchronization circuit that performs bit phase synchronization with a first clock having a clock frequency of 1 / a times, and the above-mentioned problems are solved by the following characteristic configurations.

That is, in the first aspect of the invention, the clock frequency is a times or 1 / a times the bit rate of the received data from the reference clock having a frequency of m times (m> 0) the clock rate of the first clock, Moreover, the n-phase clock obtained by shifting the 1-bit width of the received data to the n-phase (n is a natural number of 2 or more) is PLL.
A "phase locked loop" circuit is used to generate a frequency control signal with this PLL circuit, and an "n-phase clock generation means" is used to selectively output a clock having one of the n-phase clocks by a selection control signal. Selecting means "and the clock selected and output by the selecting means as a phase control signal, and the frequency control signal is also taken in to perform the phase control and the frequency control by the reset VCO (voltage controlled oscillation) circuit, and the first clock described above. And a phase difference between the first clock and the received data, a selection control signal is generated based on this phase difference signal and given to the selection means. "Timing judgment output means" for latching output of received data with a clock of 1 and outputting bit phase synchronization data
And

By adopting such a configuration, a selection for selecting any one of the n-phase clocks by the phase difference signal while detecting the phase difference between the first clock and the received data. Optimally generate the control signal,
By this signal, it is possible to constantly maintain the bit phase synchronization between the first clock and the received data while always adjusting the phase. Further, even if an abnormality occurs in the phase control signal, the first clock can be generated by self-oscillating with the frequency control signal.

Therefore, no matter what phase the received data is taken in, bit phase synchronization can be achieved very stably and very quickly with a simple structure. Therefore, it is particularly effective for bit phase synchronization in high-speed data transmission.

A second aspect of the present invention is a circuit for performing bit phase synchronization with respect to parallel reception data composed of a plurality of reception data having the same bit rate, wherein the parallel reception data and the bit rate of each reception data are multiplied by a ( a is a natural number) or a bit phase synchronization circuit that establishes a bit phase synchronization with the first clock having a clock frequency of 1 / a.

More specifically, the second aspect of the present invention uses the bit phase synchronizing circuit of the first aspect of the present invention to perform bit phase synchronization with respect to any one of the parallel received data, and the other remaining The reception data is latched and output using the first clock, and the bit phase synchronization data for each reception data is output.

By adopting such a configuration, the bit phase synchronization with any one of the parallel received data is performed, so that the bit phase synchronization with respect to the entire parallel received data is very stable. Moreover, it can be performed very quickly with a simple structure.

Furthermore, a third aspect of the present invention is a bit phase synchronizing circuit which outputs a synchronizing clock bit-phase-synchronized with received data and synchronizing data, with the following characteristic configuration to solve the above problems. To do.

That is, according to the third aspect of the present invention, the initial bit phase synchronization is established for the bit data of the head portion of the received data by comparison detection with the phase-shifted multi-phase clock for stable phase detection, and the synchronization data is obtained. And an initial bit phase synchronization means for outputting the synchronization clock, and after the initial bit phase synchronization is established, the variation tracking control for the phase variation or frequency variation of the received data after the bit data of the head portion is performed to maintain the bit phase synchronization state. And a fluctuation tracking type bit phase synchronization means for continuously outputting the synchronization data and the synchronization clock.

By adopting such a configuration, the initial bit phase synchronizing means, to which the data of the head portion of the received data is input, can be synchronized with the initial bit phase in a very short period, and after the initial bit phase synchronization is established. Can follow the phase fluctuation or frequency fluctuation of the received data by the fluctuation tracking type bit phase synchronizing means to continue the bit phase locked state.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. "First Embodiment of Bit Phase Synchronization Circuit of the Present Invention":
FIG. 1 is a functional configuration diagram of the bit phase synchronization circuit. In FIG. 1, the bit phase synchronization circuit is composed of a multiplication PLL circuit 2, a selector 3, a reset VCO circuit 4, a timing determination circuit 5, and a selector control circuit 6.

The multiplication PLL circuit 2 takes in the clock from the reference clock input terminal 1 to the reference clock input terminal. This clock is m times (m> 0) the same frequency as the bit rate of the received data. This multiplication PLL circuit 2
Generates a clock having the same frequency as the bit rate of the received data. Moreover, the multiplication PLL circuit 2 uses a VCO capable of generating a multi-phase clock such as a ring oscillator to generate a multi-phase clock having a phase difference obtained by dividing one clock width of the multiplication clock into n equal parts. output from n). The phase relationship of the multi-phase clocks is such that the multi-phase clock 1 is the head of the phase and the phase is delayed as the argument increases. Further, this multiplication PLL circuit 2 is
The control voltage for controlling the frequency is output from the frequency control voltage output terminal to give the reset VCO circuit 4.

The selector control circuit 6 takes in the polyphase clock from the multiplication PLL circuit 2 to the polyphase clock input terminal, takes in the judgment result signal from the timing judgment circuit 5 to the judgment result signal input terminal, and outputs the selection control signal. Output. The selector control circuit 6 takes a holding time from when the selection control signal of the selector 3 is changed to be accurately reflected in the determination result signal of the timing determination circuit 5, and corresponds to the determination result signal input thereafter. And outputs a selection control signal.

The selection control signal is a signal which is individually output to the signals 1 to n to be selected by the selector 3 and is output so as to be individually controlled. Further, the protection time of the selector control circuit 6 needs to be equal to or longer than the feedback time of the path from the selector control circuit 6 to the selector 3, the reset VCO circuit 4, the timing determination circuit 5, and the selector control circuit 6. This feedback time depends on the configurations of the reset VCO circuit 4 and the timing determination circuit 5, but the multiplication PLL
A short feedback time with a width of 3 to 10 cycles of the oscillation clock of the circuit 2 is possible.

The selector 3 takes in the multiphase clocks from the multiplication PLL circuit 2 and selects one of the phases of the multiphase clock by the selection control signal from the selector control circuit 6 and outputs it from the signal output terminal. To do.

The reset VCO circuit 4 has timing information as shown in FIG. 3, inputs a pulse signal, and can directly control or delay the oscillation phase of the VCO by the pulse, and its control response The time is a VCO capable of generating an output clock having a phase corresponding to the input pulse signal in a short time of 1 to 5 cycle width of the oscillation clock. Regarding a specific configuration of such a reset VCO, reference is made to Japanese Patent Laid-Open No. 5-227145.
JP-A-7-74737, "Clock extraction circuit and oscillation circuit", Japanese Patent Application No. 6-380580 "Clock oscillation circuit and gate circuit used in clock oscillation circuit" And drawings, Japanese Patent Application No. 7-35669, "Clock Oscillation Circuit and Voltage Controlled Oscillation Circuit Using It", and the drawings.

Specifically, the reset VCO circuit 4 takes in the clock from the selector 3 to the phase control signal input terminal, takes in the frequency control voltage signal from the multiplication PLL circuit 2, and outputs it according to the pulse phase of the phase control signal. The clock phase is forcibly controlled, and by inputting a pulse signal having an n-phase phase, an n-phase output clock corresponding to each is generated. Further, the reset VCO circuit 4 performs free-running oscillation at a frequency determined by the frequency control voltage signal from the multiplication PLL circuit 2 when the phase control signal is not input. Here, the multiplication PL
By making the VCO forming the L circuit and the VCO forming the reset VCO circuit 4 have the same circuit configuration, the reset VCO 4 performs free-running oscillation at a frequency that substantially matches the oscillation frequency of the multiplication PLL circuit 2.

Further, the reset VCO circuit 4 has three clocks, that is, a certain reference phase clock, a clock adjacent to the reference clock and having a leading phase, and a clock adjacent to the reference clock and having a delayed phase. Output as phase clocks 0, -1, +1. This reset VC
The three-phase clocks-1, 0, +1 of the O circuit 4 are the three-phase clock input terminals-1, 0, -1, 0 of the timing determination circuit 5, respectively.
Give to +1 input.

The timing judgment circuit 5 takes in the reception data whose phase is unknown from the reception data input terminal 7, and
The three-phase clock from the reset VCO 4 is fetched, and the determination result signal is output with respect to the phase relationship between the input three-phase clock 0 and the data. The determination result signal displays the following three types of states. That is, the timing determination circuit 5
If the phase relationship is appropriate, it is judged "as is", and if it is not suitable, it is judged whether the clock phase should be "advanced" or "delayed", and the result is output as a judgment result signal and the selector is output. It is given to the judgment result signal input terminal of the control circuit 6.

Further, the timing judgment circuit 5 latches the input reception data at the three-phase clock 0, outputs the latch output from the data output terminal, and supplies this output data to the reproduction data output terminal 8. At the same time, the clock used for latching the input reception data is output from the clock output terminal and given to the reproduction data clock output terminal 9.

(Operation): Next, the operation will be described with reference to the operation timing charts of FIGS. In FIGS. 4 and 5, the frequency division ratio m = 8 to the bit rate of the received data of the reference clock and the number of phases of the multi-phase clock are n = 5. Therefore, first, a clock (FIG. 4, FIG. 5A) that is m times (m> 0) the same frequency as the bit rate of the received data (FIG. 4, FIG. 5L) is given to the multiplication PLL circuit 2. In the multiplication PLL circuit 2, a clock having the same frequency as the bit rate of received data is generated. Further, a multiphase clock (FIGS. 4 and 5B to 5F) having a phase difference obtained by dividing one clock width of the multiplied clock into n equal parts is generated, and the selector 3
And selector control circuit 6. Further, in this multiplication PLL circuit 2, a control voltage for controlling the frequency of the VCO is generated, and a reset VC is generated as a frequency control voltage signal.
Given to O4.

When the multi-phase clock is applied to the selector control circuit 6, the timing determination circuit 5 starts from the time when the selector control circuit 6 previously changed the selection control signal of the selector 3.
A protection time for accurately reflecting the determination result signal of is taken, and the selection control signal (FIGS. 4 and 5 (g)) is output corresponding to the determination result signal input thereafter, and is given to the selector 3. . Since this selection control signal is individually prepared for each of the selected signals 1 to n of the selector 3,
Individually controlled. As the protection time in this selector control circuit 6, selector control circuit 6 → selector 3 → reset V
A feedback time longer than the path of CO4 → timing determination circuit 5 → selector control circuit 6 is required. This feedback time depends on the configuration of the reset VCO 4 and the timing determination circuit 5 and is equal to 3 of the oscillation clock of the multiplication PLL 2.
A short feedback time with a period width of -10 is possible.

On the other hand, in the selector 3 to which the multi-phase clock is applied, the clock of any phase of the multi-phase clock is selected by the selection control signal from the selector control circuit 6, and the signal output terminal (FIGS. 4 and 5). (H)),
It is given to the reset VCO 4. In addition, in the selector 3,
When a plurality of selection control signals become high level, a logical sum signal for the corresponding selected signals is output.
The output signal from the selector 3 is taken in from the phase control signal input terminal of the reset VCO circuit 4, the phase of the output clock is forcibly controlled by the phase of the pulse of this signal, and the pulse signal having the phase of n phase is input. As a result, n-phase clocks corresponding to the respective clocks are generated.
When no pulse signal is input to the phase control signal input terminal, free-running oscillation is performed at a frequency determined by the frequency control voltage signal from the multiplication PLL circuit 2, and three-phase clocks 0, -1, +1 ( 4 and 5 (i) to (k))
Is generated and given to the timing determination circuit 5.

In the phase control of the reset VCO circuit 4, if the phase control signal is active high,
The selection control signal is latched in the opposite phase of the corresponding multi-phase clock that is the selected signal in the preceding stage output from the selection control signal output terminal. When a plurality of selection control signals become high level, the selector 3 outputs the logical sum of the selected signals corresponding thereto.

When switching the selection by the selector 3,
There may be a case where only one pulse of the phase control signal input to the reset VCO circuit 4 is missing, but during that period, the reset VCO circuit 4 does not perform phase control and performs free-running oscillation according to the frequency control voltage signal. Further, in the reset VCO circuit 4, when the phase control signal is active low, the positive phase of the corresponding multi-phase clock which is the selected signal is used as the clock of the latch stage of the control signal.

When the received data is given to the timing judgment circuit 5, the three-phase clock 0,-
If the clock phase is appropriate with respect to the phase relationship of the received data by 1 or +1, the received data and the
The phase clock 0 is output to the reproduction data output terminal 8 and the reproduction data clock output terminal 9. However, when the phase relation of the data is inappropriate, the determination result signals (FIG. 4, FIG. 5 (n), (o)) are generated so as to adjust the clock phase and are given to the selector control circuit 6. The timing judgment circuit 5 latches the received data at the three-phase clock 0 and outputs it as reproduced data (FIGS. 4 and 5 (m)). The clock used for this latch is output to the terminal 9 as a reproduction data clock.

Further, in the selector control circuit 6, when the judgment result signal within the protection time includes both the information for advancing the phase of the reset VCO circuit 4 and the information for delaying it.
It is determined that the received data is overlaid with noise, the input value is an undefined value due to input line disconnection, or the output clock of the reset VCO circuit 4 has caused a tracking error with respect to the received data. A timing error signal is output from the error output terminal, and the reception data identification error output terminal 10 (FIGS. 4 and 5 (p))
Output from

(Detailed Configuration of Multiplication PLL Circuit 2): FIG. 6 is a detailed functional configuration diagram of an example of the multiplication PLL circuit 2 used in FIG. 1 described above. In FIG. 6, the multiplication P
The LL circuit 2 includes voltage controlled delay inverting circuits 211 to 21n and FETs 251 to 25n that form a ring oscillator.
, Phase frequency detection circuit 22 and charge pump circuit 2
3, a low pass filter 24, and an m frequency dividing circuit 25.

The phase frequency detection circuit 22 provides the charge pump circuit 23 with the phase comparison result signals U and D obtained by performing a phase comparison with the m-divided clock from the m-divided circuit 25 when supplied with the reference clock. . The charge pump circuit 23 performs signal charge pumping from the phase comparison result signals U and D from the phase frequency detection circuit 22 using an analog circuit element and a digital circuit element or the like, and is a signal obtained by waveform-shaping the phase comparison result signals U and D. To the low pass filter 24. The low pass filter 24 includes the charge pump circuit 2
A signal obtained by low-passing the signal given from No. 3 is given to the gate terminals of the FETs 251 to 25n forming the VCO, and the signal after passing the low-pass is outputted from the frequency control voltage output terminal.

The voltage controlled delay inverting circuits 211 to 21n of the VCO circuit and the FETs 251 to 25 shown by the dotted lines in FIG.
When n receives a signal after passing the low band from the low-pass filter 24, it oscillates and forms an n-phase clock and outputs it to the multi-phase clock output terminal.
Return to the frequency dividing circuit 25. That is, the voltage control delay inverting circuit 21
The output signals of 1 to 21n are output to the multi-phase clock output terminals, and the output signal of the voltage controlled delay inverting circuit 21n is given to the m frequency dividing circuit 25. The m frequency dividing circuit 25 frequency-divides the output signal of the voltage controlled delay inverting circuit 21n by m (m is a real number of 1 or more) and supplies it to the phase frequency detecting circuit 22. With such a configuration, it is possible to generate a multi-phase clock by using the reference clock as an input signal and generate and output a frequency control voltage signal.

(Detailed configuration of the reset VCO circuit 4):
FIG. 7 is a detailed functional configuration diagram of an example of the reset VCO circuit 4 of FIG. 1 described above. In FIG. 7, reset V
The CO circuit 4 is composed of a ring oscillator circuit like the VCO circuit of the multiplication PLL circuit 2 of FIG.
That is, the reset VCO circuit 4 has the voltage control delay 2 input N
An OR circuit 41, voltage control delay inverting circuits 42-4n,
It is composed of FETs 411 to 41n. The frequency control voltage signal given to the frequency control voltage input terminal is FE
The signal is supplied to the gate terminals of T411 to 41n, and the drain currents of the FETs 411 to 41n are controlled by this signal to control the propagation delays of the voltage controlled delay 2-input NOR circuit 41 and the voltage controlled delay inverting circuits 42 to 4n.

The phase control signal applied to the phase control signal input terminal is applied to the voltage control delay 2-input NOR circuit 41 to control the phase of the oscillation signal. Voltage control delay 2 inputs N
A three-phase clock is generated by the ring oscillator circuit including the OR circuit 41 and the voltage controlled delay inverting circuits 42 to 4n and output to the three-phase clock output terminal. That is, from the output of the voltage control delay 2-input NOR circuit 41 to the 3-phase clock-1
From the output of the voltage controlled delay inverting circuit 43
Phase clock-0 is generated and output, and the voltage controlled delay inverting circuit 4
Generates and outputs the 3-phase clock + 1 from 5.

With such a configuration, the reset VCO circuit 4
By configuring the above, it is possible to generate and output the clocks of three adjacent phases by the phase control signal and the frequency control voltage signal. Also, this reset VC
Since the VCO forming the O circuit 4 and the VCO forming the multiplication PLL circuit 2 have the same circuit configuration,
The reset VCO circuit 4 can perform free-running oscillation at a frequency that substantially matches the oscillation frequency of the multiplication PLL circuit 2. Therefore, the time and effort of circuit design can be reduced.

(Detailed Configuration of First Embodiment of Timing Determination Circuit 5): FIG. 8 is a detailed functional configuration diagram of the first embodiment of the timing determination circuit 5 in FIG. 1 described above. In FIG. 8, the timing determination circuit 5 is
Flip-flop circuits 511 to 513, 516, 517
And exclusive OR circuits 514 and 515.

Received data is supplied to the data input terminals D of the D flip-flop circuits 511 to 513, the three-phase clock-1 is supplied to the clock input terminal C of the D flip-flop circuit 511, and the D flip-flop circuit 512 is supplied.
3 phase clock 0 is given to the clock input terminal C of
The 3-phase clock + 1 is applied to the clock input terminal C of the D flip-flop circuit 513. The D flip-flop circuit 511 outputs a latch output signal for the received data from the data output terminal Q and supplies it to the exclusive OR circuit 515.

The D flip-flop circuit 512 outputs a latch output signal for the received data from the data output terminal Q, supplies it to the exclusive OR circuits 515 and 514, and outputs it to the data output terminal. The D flip-flop circuit 513 outputs a latch output signal for the received data from the data output terminal Q and supplies it to the exclusive OR circuit 514. The exclusive OR circuit 514 performs an exclusive OR operation from the latch output signal from the D flip-flop circuit 512 and the latch output signal from the D flip-flop circuit 513, and the operation result is the D flip-flop circuit 516. Data input terminal D.

The clock input terminal C of the D flip-flop circuit 516 is supplied with the three-phase clock -1, and the exclusive OR operation result is latched and output by this clock, and this latched output signal (advance the phase) is output. Signal) to the determination result signal output terminal 1.

On the other hand, the exclusive OR circuit 515 performs an exclusive OR operation on the latch output signal of the D flip-flop circuit 511 and the latch output signal from the D flip-flop circuit 512, and the operation result is D It is applied to the data input terminal D of the flip-flop circuit 517. The clock input terminal C of the D flip-flop circuit 517 has 3
The phase clock -1 is given, the exclusive OR operation result is latched and output by this clock, and this latch output signal (a signal that delays the phase) is output to the determination result signal output terminal 2.

With this configuration, the timing judgment circuit 5 takes in the received data whose phase is unknown and
If the three-phase clocks -1, 0, +1 from the reset VCO 4 are fetched and the phase relationship between the input three-phase clock 0 and the data is appropriate, the phase is changed as it is, or if it is inappropriate, the clock phase is changed. It is determined whether to proceed or to delay, and the result is output as a determination result signal. Further, the timing judgment circuit 5 latches the input reception data by the three-phase clock 0, outputs the latch output from the data output terminal, and simultaneously outputs the three-phase clock 0 used for latching the input reception data. To do.

(Detailed Configuration of First Embodiment of Selector Control Circuit 6): FIG. 9 is a detailed functional configuration diagram of the first embodiment of the selector control circuit 6 in FIG. 1 described above. In FIG. 9, the selector control circuit 6 includes D flip-flop circuits 61, 62, 66 to 69, 610, 6
21-62n and 2-input AND circuits 63-65, 618
1-inversion 2-input AND circuits 611 and 612, OR circuit 613, up-down counter 614, binary counter 615, JK flip-flop 616, and
It is composed of an input NOR circuit 617.

Of the two judgment result signals from the timing judgment circuit 5, one judgment result signal (a signal for advancing the phase) is given from the input terminal 1 to the clock input terminal C of the D flip-flop circuit 61, and the other. The determination result signal (signal for delaying the phase) is given from the input terminal 2 to the clock input terminal C of the D flip-flop circuit 62. D
A high level signal is applied to the data input terminals D of the flip-flop circuits 61 and 62, and when a rising edge is applied to the clock input terminal C, the high level signal is latched and output from the data output terminal Q.

The latch output signals of the D flip-flop circuits 61 and 62 are given to the 2-input ANDs 63 to 65, and the D flip-flop circuit 6 is provided except for the protection time determined by the count value of the binary counter 615.
It is latched by 7, 68 and the latch output signal is given to the D flip-flop circuits 69, 610. The circuit composed of the D flip-flop circuits 67 to 69 and 610 and the one-sided inversion two-input AND circuits 611 and 612 detects the rising edge of the determination result signal and forms a pulse of one clock width.

A pulse generated by detecting the rising edge of the signal for advancing the phase by the detection circuit is output from the one-sided two-input AND circuit 611 and given to the down input D of the up / down counter 614. On the other hand, the pulse generated by detecting the rising edge of the signal that delays the phase is output from the one-sided 2-input AND circuit 612 and is given to the up input U of the up / down counter 614.

When the down signal is input, the up / down counter 614 selects, for example, 3 → so that the clock whose phase is ahead of the currently selected clock is selected.
The countdown is performed in the order of 2 → 1 → n → (n−1), and the countdown signals are output from the output terminals Q1 to Qn and given to the D flip-flop circuits 621 to 62n.

On the contrary, when the up / down counter 614 is given an up signal, the up / down counter 614 selects a clock whose phase is delayed from the currently selected clock.
(N-1) → n → 1 → 2 → 3, and count-up signals are output from the output terminals Q1 to Qn and given to the D flip-flop circuits 621 to 62n. Outputs Q1 to Qn of the up / down counter 614
Are D flip-flop circuits 621 that operate at the timing of the opposite phase of the clock that is the selected signal controlled by the output, and are provided in the same number as the number of types of multiphase clocks.
~ 62n and output to the selection control signal output terminals 1 to n.

On the other hand, the binary counter 615 is cleared by the pulse that detects the rising edge of any of the judgment result signals, and a carry signal is output after a few counts, and the leading edge detection pulse from the preceding judgment result signal to the carry signal are output. As a protection time, the input signals of the D flip-flop circuits 67 and 68 are fixed to low level signals, and the logical product of the carry signal and the protection pulse is AND circuit 618.
The AND operation result signal is applied to the reset terminals R of the D flip-flop circuits 61 and 62 to be reset. The binary counter 615 is disabled by the carry signal RC. If both the signal for advancing the phase and the signal for delaying the phase are input, D
After being latched by the flip-flop circuit 66, a timing error signal is output from the data output terminal Q.

(Effects of the First Embodiment of the Bit Phase Synchronization Circuit of the Present Invention): According to the first embodiment of the present invention described above, no matter what phase the received data is taken in, It is possible to realize a bit phase synchronizing circuit that outputs data and a clock that are very stable and have a simple structure and very quickly bit phase synchronized.

Specifically, the reset VCO circuit 4 and the multiplication PLL circuit 2 are constructed by using VCOs having the same circuit configuration, and the frequency control voltage of the multiplication PLL circuit 2 is reset VC.
By applying it as the frequency control voltage of O, the free-running frequency of the reset VCO circuit 4 can be made substantially equal to the oscillation frequency of the multiplication PLL circuit 2.

Further, the phase control input of the reset VCO circuit 4 is selectively input by the selector to the clock of one phase of the multiphase clocks of the multiplication PLL circuit, and the output clock of the phase-controlled reset VCO circuit 4 and the received data are received. If it is determined that the timing is appropriate, the currently selected multiphase clock always controls the phase of the reset VCO circuit 4, and therefore the reset VC
The O circuit 4 can generate a stable output clock like the output clock of the multiplication PLL circuit 2.

Further, when the timing becomes improper, the reset VCO circuit 4 is set in the phase direction judged as proper.
Of the multi-phase clock, which is presumed to be appropriate, so that the output clock of the output signal of V.
The O circuit 4 can output the clock of the new phase at a very fast response speed of about 1 to 5 clock cycle width.

Furthermore, even if the received data is burst data, bit phase synchronization can be quickly established, and even when the received data includes jitter wander, it can be made to follow quickly similarly. Further, for stable received data, once the bit phase synchronization is completed, the reset VCO circuit 4 outputs a stable clock comparable to that of the multiplication PLL circuit 2, so that the continuous tolerance for the same code of data becomes almost infinite. can do.

Further, it is possible to easily detect the failure of the received data or the failure of the reset VCO circuit 4. From the above, in the device which reproduces the data from the received data, the above-mentioned bit phase synchronizing circuit is used. By using it, a device having very high performance can be easily realized at low cost.

[Second Embodiment of Bit Phase Synchronization Circuit of the Present Invention]: The second embodiment is a modification of the timing determination circuit 5 in the first embodiment of the bit phase synchronization circuit described above. The one configured by will be described. The other circuit configurations are the same.

FIG. 10 is a functional block diagram of the timing judgment circuit 5'of the second embodiment. In FIG. 10, the timing determination circuit 5 ′ includes delay circuits 521 and 52.
2, D flip-flops 523 to 525, and exclusive OR circuits 526 and 527.

A clock is applied to the clock input terminal C of each of the D flip-flops 523 to 525. Received data is applied to the data input terminal D of the D flip-flop 523, and latch output data is applied to the exclusive OR circuit 527 from the data output terminal Q. The delay circuit 521 takes in the received data, delays it, and then applies it to the data input terminal D of the D flip-flop 524. The D flip-flop 524 latches and outputs the delayed received data with a clock, supplies the delayed received data to the exclusive OR circuits 526 and 527, and outputs it to the data output terminal.

The input clock is also output as a clock output. The delay circuit 522 delays the delay data from the delay circuit 521 and supplies it to the data input terminal D of the D flip-flop 525. The D flip-flop 525 latches the delayed data from the delay circuit 522 with a clock and gives it to the exclusive OR circuit 526. Exclusive OR circuit 52
6 performs an exclusive OR operation on the latch output data from the D flip-flops 524 and 525, and outputs the operation result as a second determination result signal. Further, the exclusive OR circuit 527 is configured to detect the D flip-flops 523 and 524.
The exclusive OR operation of the latch signal is performed and the operation result is output as the first determination result signal.

(Effects of the Second Embodiment): According to the configuration of the second embodiment described above, the received data is fetched at what phase as in the first embodiment. Even in this case, it is possible to realize a bit phase synchronizing circuit that outputs data and a clock that are very stable and have a simple configuration and very quickly bit phase synchronized.

Further, since the timing judgment circuit 5'is configured as shown in FIG. 10, the received data having an unknown phase and the clock are acquired with a very simple structure, and the input clock and the data are compared. If it is appropriate for the phase relationship, output the clock as it is, and if it is inappropriate, determine whether the clock phase should be advanced or delayed, and output the result as a determination result signal. Can be realized.

[Third Embodiment]: In the third embodiment, the second embodiment of the selector control circuit in the bit phase locked loop circuit of the first embodiment will be described.
It realizes bit phase synchronization.

FIG. 13 is a detailed functional block diagram of the selector control circuit 6A of the second embodiment. In FIG. 13, the selector control circuit 6A includes D flip-flop circuits 61, 62, 66 to 69, 610, and 621a to 62na.
And 2-input AND circuits 63 to 65 and 618, and one-sided inversion 2
Input AND circuits 611 and 612, an OR circuit 613,
Up-down counter 614 and binary counter 61
5, a JK flip-flop 616, and a 2-input NOR circuit 617.

In FIG. 13, the configuration different from the selector control circuit 6 of the above-described first embodiment is the “circuit enclosed by the dotted line” in FIG. 13, which latches and outputs the multiphase clock. D flip-flop circuit 62 for
This is to give 1a to 62na to the reset input terminal so that the pulse can be reset (cleared) by the pulse detecting the rising edge of the determination result signal output from the 2-input exclusive OR circuit 613.

The specific operation is as follows. That is, in the selector control circuit 6A of the second embodiment, since the selector control circuit 6A changes the selection control signal of the selector 3 last time, the determination result signal of the timing determination circuit 5 is accurately reflected. A selector control circuit 6 is provided corresponding to the judgment result signal input after the protection time is taken.
A selection control signal is output from the A selection control signal output terminal. The selection control signal is individually provided for each of the signals 1 to n to be selected by the selector 3, and thus can be individually controlled.

Here, in the phase control of the reset VCO circuit 4, if the phase control signal is active high level, the control signal is a corresponding selected signal in the preceding stage output from the selection control signal output terminal. Latched on the opposite phase of the multi-phase clock. Then, the latch stage is asynchronously cleared from immediately before the control signal is changed until the control signal becomes stable.

The selector 3 outputs a low level signal which is an inactive signal of the reset VCO circuit 4 when all the control signals are at a low level. During that period, the reset VCO circuit 4 is not phase-controlled, and therefore, self-oscillation is performed according to the voltage applied to the frequency control voltage input terminal.

Next, the operation of the selector control circuit 6A in the second embodiment will be described focusing on the operation different from that in the above-described first embodiment. In the operation related to the D flip-flop circuits 621 to 62n, the D flip-flop circuits 621 to 62n are cleared by the pulse that detects the rising edge of the determination result signal output from the 2-input exclusive OR circuit 613, and the output of the up-down counter 614 is output. The signals are decoded and prepared in the same number as the number of phases of the multiphase clock, and each output is latched by the D flip-flop circuits 621 to 62n which operate at the timing of the opposite phase of the clock which is the selected signal controlled by the output. And a selection control signal is output.

11 and 12 are operation timing charts of the bit phase synchronizing circuit of the third embodiment. 11 and 12 are characterized in that FIG. 11 and FIG.
As shown in 2 (g), when the selection by the selector 3 is unselected before switching from 1 selection to 2 selection, the signal output from the signal output terminal (FIG. 11, FIG. 12 (h)) is h1.
Even if the signal is output like a pulse, this signal is fetched from the phase control signal input terminal of the reset VCO circuit 4 and the reset VCO is reset even if there is no signal between the h1 pulse and the h2 pulse. In the circuit 4, the three-phase clocks shown in (i) to (k) of FIGS. 11 and 12 can be self-oscillated by the frequency control voltage signal given from the multiplication PLL circuit 2 and stably and continuously output. it can. Then, from the signal output terminal from the selector 3 to FIG.
When the h2 pulse shown in (h) is output, the h2 pulse can be continuously output as a phase control signal to stably output the three-phase clock.

(Effect of Third Embodiment): According to the configuration of the third embodiment described above, in addition to the effect of the first embodiment described above, the phase control signal of the reset VCO circuit 4 is added. When switching the multi-phase clock input to, the mask is applied before and after the switching so that the active signal is not input to the phase control signal of the reset VCO circuit 4, and the new multi-phase clock after switching is reset to the reset VCO.
When inputting as the phase control signal of the circuit 4, the active area (for example, high-level area) is input so as not to be lost by the above-mentioned mask, so that the switching is performed regardless of the duty ratio of the multiphase clock. The phase of the reset VCO circuit 4 can be smoothly transitioned without noise entering the phase control input of the reset VCO circuit 4.

[Fourth Embodiment of Bit Phase Synchronization Circuit of the Present Invention]: FIG. 14 is a functional block diagram of the bit phase synchronization circuit of the fourth embodiment. In FIG. 14, the bit phase synchronization circuit includes a multiplication PLL circuit 2 and a selector 3
, Reset VCO circuit 4, and timing determination circuit 5
And a selector control circuit 6B and a missing clock generation circuit 11. A characteristic of the configuration of this bit phase synchronization circuit is that it is provided with the "missing clock generation circuit 11" and the improved selector control circuit 6B. Other configurations are the same as those in the above-described embodiment. Therefore, the function and operation will be described with reference to the operation timing charts of FIGS. 15 and 16.
Incidentally, in FIG. 15 and FIG. 16, the number of phases of the multi-phase clock n = 5
In the following description, the missing tooth cycle of the missing tooth clock generation circuit 11 is k = 4.

This "toothless clock generation circuit 11"
Takes in the multiphase clock from the multiplication PLL circuit 2,
Multiphase missing clock (Figs. 15 and 16 (c1) to (c)
5)) is output to the selector 3 and a switching timing signal (FIGS. 15 and 16 (m)) is output to the selector control circuit 6B. In the toothless clock generation circuit 11, a so-called toothlessness is generated in which only one clock pulse of k (k is an integer of 2 or more) cycles is made to stand for each clock of the input multiphase clocks 1 to n. Pulse (FIG. 15, FIG. 16 (c1) to (c5)), and the pulse generated for each phase is generated so as to fit within the two-clock period width of the multi-phase clock.

Here, the value of k depends on the difference between the oscillation frequency of the multiplication clock of the multiplication PLL circuit 2 and the free-running oscillation frequency of the reset VCO circuit 4 when the reset VCO circuit 4 is free-running oscillating. Although the oscillation phase deviates, the width is the number of cycles that does not matter. In addition, a switching timing signal (see FIGS. 15 and 16)
(M)) is generated such that an active pulse stands at an intermediate position between the pulse of the toothless clock and the pulse.

In the "selector control circuit 6B", a protection time for accurately reflecting the selection result signal of the timing judgment circuit 5 from the time when the selector control circuit 6A last changed the selection control signal of the selector 3 is taken, The determination result signal input after that (FIG. 15, FIG. 16 (k), (l))
The control signal (FIG. 15 and FIG. 16D) is output from the selection control signal output terminal of the selector control circuit 6B in response to the above.

Here, the selection control signal is latched by the multi-phase clock 1 at the stage before being output from the selection control signal output terminal, and the latch is switched by the switching timing signal (FIGS. 15 and 16 (m)). When it is active, it takes in a new selection control signal, and when the switching timing signal is inactive, it holds the value of the latch. That is, the control of the selector 3 is performed in the area where the switching timing signal is active, and at that timing, the input of the selected signals 1 to n of the selector 3 is a low level signal which is an inactive signal as the phase control signal of the reset VCO circuit 4. The value is stable. Therefore, when switching
Phase control signal input terminal of the reset VCO circuit 4 (see FIG.
5, no noise is input to FIG.

Further, the reset VCO circuit 4 receives the phase control almost once every k cycles regardless of the steady state where switching does not occur and at the time of switching, and the phase control signal (FIGS. 15 and 16 (e)). While the active pulse is not input, self-oscillation is performed at a frequency that substantially matches the oscillation frequency of the multiplication PLL circuit 2 according to the voltage applied to the frequency control input terminal (FIGS. 15 and 16 (f) to (h)). )I do.

(Detailed Configuration of Selector Control Circuit 6B):
FIG. 17 is a detailed functional block diagram of the selector control circuit 6B of the third embodiment. In FIG. 17, the selector control circuit 6B includes D flip-flop circuits 61, 62,
66-69, 610, "D flip-flop circuit with selector 621b-62nb", 2-input AND circuit 6
3 to 65, 618, and a single inversion 2-input AND circuit 611,
612, the OR circuit 613, and the up / down counter 6
14, a binary counter 615, a JK flip-flop 616, and a 2-input NOR circuit 617.

In FIG. 17, the configuration different from the selector control circuit 6 of the first embodiment is the “circuit of the portion surrounded by the dotted line” of FIG. From the D flip-flop circuits with selectors 621b to 62nb to generate and output an n-phase selection control signal.

The operation of the selector control circuit 6B will be specifically described. First, a signal for advancing the phase and a signal for delaying the phase as the determination result signal are input as clocks of the D flip-flop circuits 61 and 62, respectively. When the rising edge of the clock is input, the D flip-flop circuits 61 and 62 latch and output the high level output, and these latch output signals are output to the binary counter 61.
If it is other than the protection time determined by 5, it is latched by the D flip-flop circuits 67 and 68, respectively.

D flip-flop circuits 67 to 69, 61
A circuit composed of 0 and half-inverted 2-input AND circuits 611 and 612 detects the rising edge of the determination result signal and outputs a pulse having a width of 1 clock. The pulse generated by detecting the rising edge of the signal for advancing the phase in the detection circuit is given to the down input of the amplifier down counter 614. The pulse generated by detecting the rising edge of the signal that delays the phase in the detection circuit is given to the up input of the up / down counter 614. When the down signal is input, the amplifier down counter 614 counts down in the order of 3 → 2 → 1 → n → (n−1) in order to select the clock whose phase is ahead of the currently selected clock.

On the contrary, when the up signal is inputted, the clock is counted up in the order of (n-1) → n → 1 → 2 → 3 in order to select the clock whose phase is delayed from the clock currently selected. The output of the up / down counter 614 is decoded and prepared in the same number as the number of phases of the multi-phase clock. When the switching timing signal is at the high level, each output is provided with the D flip-flop circuits with selectors 621b-6.
At 2nb, it is latched out by the input clock. When the switching timing signal is at the low level, the D flip-flop circuits with selectors 621b to 62nb hold their own data.

On the other hand, by the pulse that detects the rising edge of any of the determination result signals. Binary counter 615
Is cleared, a carry signal is output after a few counts,
The inputs of the D flip-flop circuits 67 and 68 are fixed at a low level with the rising detection pulse of the determination result signal to the carry signal as the protection time, and the D flip-flop circuit is output by the AND operation result output signal of the carry signal and the protection pulse. Complete 61 and 62.

The binary counter 615 is disabled by the carry signal. Further, when both the signal for advancing the phase and the signal for delaying the phase are input, they are latched by the D flip-flop circuit 66 and then output as a timing error signal.

(Detailed Configuration of Toothless Clock Generation Circuit 11): FIG. 18 is a detailed functional configuration diagram of the toothless clock generation circuit 11 shown in FIG. In FIG. 18, the toothless clock generation circuit 11 is configured with toothless clock generation units 111 to 11n for each of the input multiphase clock signals, and is realized by the same circuit configuration. To describe the internal configuration as a representative, the toothless clock generation unit 111 includes a binary counter 1111, a half-inversion two-input AND circuit 1112, and
Input NOR circuit 1113 and 2-input AND circuit 1114
And a D flip-flop circuit 1115.

The binary counter 1111 operates with a clock having a phase opposite to that of the multi-phase clock 1, and a 2-input NOR signal that outputs a high-level signal only once every 4 clocks from the counter value.
A two-input AND circuit 1114 performs a logical product operation of the signal generated by the circuit 1113 and the multiphase clock 1 to generate a toothless clock. In addition, a signal in which a high level is set once in four clocks from the counter value and a high level is set in the middle of the missing clock is one-sided inversion 2 input A
It is output by the ND circuit 1112 and is generated as a switching timing signal. This switching timing signal is used only by the output of the toothless clock generation unit 111.

The chain reset input signal of the toothless clock generating unit 111 is input as the load signal of the binary counter 1111. In this binary counter 1111, the arrangement of the toothless clock generating unit and k (in integers of 2 or more). , The number of tooth loss cycles) is loaded. In addition, the chain reset input signal is the multiphase clock 1
It is latched and output by the D flip-flop circuit 1115 which operates in the opposite phase of, and is output as a chain reset output signal. This chain reset output signal starts from the toothless clock generation unit 11n, is output from the toothless clock generation unit, and then processes the adjacent phase-advanced multiphase clocks. Is input as a chain reset input signal of
1 closes the chain.

Here, how to determine the load value to the binary counter 1111 will be described. Missing clock generator 1
1n is used as the start-up clock of the reset chain, and when the value of the binary counter 1111 of the start-up clock generator 11n is 0, the code 0 signal is output, and the signal is the stop-out clock generator 11. (N-1) chain reset input signal n-1 is input, and the binary counter 1111 of the toothless clock generation unit 11 (n-1) is input.
Then, the value of the value of the binary counter 1111 of the preceding missing clock generating unit 11n, which is the missing clock generating unit, is 1
Is set as the load value, which is an incremented value of 1, and is loaded by the chain reset input signal n-1.

Similarly, a value obtained by incrementing the value loaded by the preceding clock-missing clock generation unit by 1 is used as a load value. When the load value becomes equal to k-1, The clock generator returns the load value to 0 and increases the load value by 1 again. With such a configuration, the positions of all the pulses of the toothless clock can be set within the two-clock cycle width.

(Effects of Fourth Embodiment): According to the configuration of the bit phase locked loop circuit of the fourth embodiment described above, in addition to the effects of the first embodiment, the reset VCO circuit is provided. The phase control signal input to 4 is set to a toothless clock, and all the multiphase toothed clocks input to the selector 3 are stable as the phase control signal of the reset VCO circuit 4 at the value of the inactive signal. By providing the region with a width of 0.5 clock cycles or more, the phase control signal can be output at the timing of the clock of the specific phase.

Further, by increasing the tooth loss cycle, the timing margin for outputting the selection control signal at the time of switching is increased, and as a result, the selector control circuit 6B.
It is possible to use only one type of clock for the above, which simplifies the circuit configuration and facilitates the timing circuit design.

[Fifth Embodiment of Bit Phase Synchronizing Circuit of the Present Invention]: FIG. 19 is a functional block diagram of a bit phase synchronizing circuit of the fifth embodiment. In FIG. 19, the bit phase synchronization circuit includes a multiplication PLL circuit 2A, a selector 3, a reset VCO circuit 4, and a timing determination circuit 5.
A selector control circuit 6B, a toothless clock generation circuit 11A, a "first multi-phase clock generation circuit 12, and a second multi-phase clock generation circuit 13".

The characteristic configuration of the configuration of FIG. 19 is that it is provided with a "first multi-phase clock generation circuit 12 and a second multi-phase clock generation circuit 13" and that the multiplication P
The LL circuit 2A has a single-phase clock output configuration instead of the multi-phase clock output, and the toothless clock generation circuit 1
1A has a single-phase clock output configuration instead of a multi-phase clock output. The other components use the functional components shown in the above embodiment. The toothless clock generation circuit 11A is realized by using one toothless clock generation unit 111 in the configuration of the toothless clock generation circuit 11 of FIG. 18 of the above-described fourth embodiment. can do.

The multiplication PLL circuit 2A takes in a reference clock and generates a clock obtained by multiplying the reference clock to generate a first multiphase clock generation circuit 12, a toothless clock generation circuit 11A, and a selector control circuit 6B. And a frequency control voltage signal is generated to reset V
Giving to CO4.

The "first multi-phase clock generation circuit 12" is
A delay amount control voltage signal is generated from the clock from the multiplication PLL circuit 2 and given to the delay amount control voltage input terminal of the second multi-phase clock generation circuit 13. The toothless clock generation circuit 11A generates a single-phase toothless clock from the clock from the multiplication PLL circuit 2 and supplies it to the second multiphase clock generation circuit 13, and also generates a switching timing signal to control the selector. It is given to the circuit 6B. The “second multi-phase clock generation circuit 13” is a toothless clock generation circuit 11
Based on the clock from A, the delay amount control voltage signal from the first multi-phase clock generation circuit 12 is used to generate the multi-phase missing clocks 1 to n and give them to the selector 3.

(Operation): Next, the operation of the bit phase synchronizing circuit of FIG. 19 will be described with reference to the operation timing charts of FIGS. Therefore, first, the reference clock input terminal of the multiplication PLL circuit 2A is input with a reference clock signal (FIG. 20, FIG. 21A) of 1 / m times (m> 0) times the same frequency as the bit rate of the received data. Then, in the multiplication PLL circuit 2A, a clock (FIGS. 20 and 21 (b)) having the same frequency as the bit rate of the received data is generated and output.

Further, the frequency control voltage for controlling the frequency of the VCO is output to be applied to the reset VCO circuit 4. In the first multiphase clock generation circuit 12, the principle of the ring oscillator is applied to compare the input clock with the clock obtained by delaying the input clock by the multistage gate circuit, and this phase difference becomes one clock cycle width. The delay amount control voltage signal for controlling the delay amount of the multi-stage gate circuit is generated and output.

In the toothless clock generation circuit 11A to which the clock from the multiplication PLL circuit 2A is input, only one of the clock pulses of k (k is a natural number of 2 or more) cycles is raised with respect to the input clock. A so-called toothless clock is generated. Here, the value of k is the multiplication PLL when the reset VCO circuit 4 self-oscillates.
Oscillation frequency of multiplied clock of circuit 2A and reset VC
Reset V due to the difference from the free-running oscillation frequency of O circuit 4
Although the oscillation phase of the CO circuit 4 deviates, its width is set to the number of cycles that does not matter.

Further, the switching timing signal is generated so that an active pulse rises at an intermediate position between the pulse of the toothless clock and the pulse. The missing clock output generated by the missing clock generating circuit 11A (see FIG. 2).
0, FIG. 21C shows the second multiphase clock generation circuit 1
3 is input. In the second multi-phase clock generation circuit 13, the second multi-phase clock generation circuit 13 is applied by applying the delay amount control voltage signal of one clock cycle width generated in the first multi-phase clock generation circuit 12. In, a multi-phase toothless clock having a phase difference obtained by dividing one clock width into n equal parts is generated. The multiphase missing clocks of the second multiphase clock generation circuit 13 (FIG. 20, FIG. 21 (d1) to (d1)
5)) is applied to the selected signal input terminal of the selector 3, respectively. In the selector 3, one of the signals input to the selected signal input terminal is output from the signal output terminal according to the selection control signal (FIG. 20, FIG. 21 (e)).

The signal output from the signal output terminal of the selector 3 (FIG. 20, FIG. 21 (f)) is input to the phase control signal input terminal of the reset VCO circuit 4. Reset VC
In the O circuit 4, the phase of the output clock is forcibly controlled by the phase of the pulse of the signal input from the phase control signal input terminal, and by inputting the pulse signal having the phase of n phase, the corresponding n Phase output clocks (FIGS. 20 and 21 (g)) are generated.

In addition, when the pulse signal is not input to the phase control signal input terminal, the reset VCO circuit 4 changes from the frequency control voltage output terminal of the multiplication PLL circuit 2A to the frequency control voltage input terminal of the reset VCO circuit 4. Free-running oscillation occurs at a frequency determined by the applied voltage. Here, by making the VCO forming the multiplication PLL circuit 2A and the VCO forming the reset VCO circuit 4 have the same circuit configuration, the reset VCO circuit 4 has its own frequency substantially equal to the oscillation frequency of the multiplication PLL circuit 2A. Run oscillation. The output clock of the reset VCO circuit 4 is input to the clock input terminal of the timing determination circuit 5.

Data of unknown phase transmitted from the opposite device is input to the reception data input terminal, and the data is input to the data input terminal of the timing judgment circuit 5 (FIGS. 20 and 21 (h)). Is entered.

The timing judgment circuit 5 judges whether the phase relationship between the input clock and data is appropriate if it is appropriate, and if it is inappropriate, it is judged whether the phase of the clock should be advanced or delayed. The result is output from the determination result signal output terminal (FIG. 20, FIG. 21 (j), (k)).

Further, the timing judgment circuit 5 latches the input data by the input clock and outputs the latch output from the data output terminal. This output signal is the reproduction data output terminal (FIG. 20, FIG. 21). (I)). The clock used for latching the input received data is output from the clock output terminal, and this output signal is output from the reproduction data clock terminal.
The determination result signal of the timing determination circuit 5 (see FIGS. 20 and 21).
(J) and (k) are input to the determination result signal input terminal of the selector control circuit 6B.

The selector control circuit 6B takes a protection time for accurately reflecting the selection result signal of the timing judgment circuit 5 from the time when the selector control circuit 6B changed the selection control signal of the selector 3 last time, and thereafter, A control signal is output from the selection control signal output terminal of the selector control circuit 6B in response to the determination result signal input to.

Here, the selection control signal is latched by the input clock in the stage before being output from the selection control signal output terminal, and the latch is activated when the switching timing signal (FIG. 20, FIG. 21 (l)) is active. To
When a new selection control signal is taken in and the switching timing signal is inactive, the value of the latch is held. That is, the control of the selector 3 is performed in the area where the switching timing signal is active, and the input of the selected signal of the selector 3 is input to the reset VCO circuit 4 at this timing.
The phase control signal is stable at a low level value which is an inactive signal. Therefore, noise is not input to the phase control signal input terminal of the reset VCO circuit 4 at the time of switching.

The reset VCO circuit 4 receives the phase control almost once every k cycles regardless of the steady state in which switching does not occur and during switching, and the frequency control input is applied while the active pulse of the phase control signal is not input. According to the voltage applied to the terminal, free-running oscillation is performed at a frequency that substantially matches the oscillation frequency of the multiplication PLL circuit 2A.

Further, in the selector control circuit 6B, when the judgment result signal within the protection time includes both the information for advancing the phase of the reset VCO circuit 4 and the information for delaying the phase, the received data is overlaid with noise. It is determined that the input value is an undefined value due to disconnection of the input line or the output clock of the reset VCO circuit 4 caused a tracking error with respect to the received data, and the timing error signal is output from the timing error output terminal. It is output and output from the reception data identification error output terminal.

(Detailed Configuration of First Multi-Phase Clock Generation Circuit 12): FIG. 22 shows the first multi-phase clock generation circuit 1.
It is a detailed functional block diagram of 2. In FIG. 22, the first
The multi-phase clock generation circuit 12 of FIG.
11 to 121n, a phase frequency detection circuit 122, a charge pump circuit 123, and a low pass filter circuit 124.
It is composed of

The clock applied to the clock input terminal is applied to the voltage controlled delay circuit 1211 and the phase frequency detection circuit 122. Voltage controlled delay circuits 1211 to 1
21n are connected in series by n pieces. The output signal of the voltage control delay circuit 121n is given to the phase frequency detection circuit 122. The phase frequency detection circuit 122 compares the phase of the input clock with the output signal from the voltage control delay circuit 121n, detects the phase comparison frequency signal, and supplies it to the charge pump circuit 123.

The charge pump circuit 123 applies a signal obtained by charge pumping the phase comparison frequency signal from the phase frequency detection circuit 122 to the low pass filter circuit 124.
The low-pass filter circuit 124 low-pass-processes the charge pump signal and supplies it to the gate terminals of the FETs 121a to 121na. As a result, the voltage control delay circuit 1211
~ 121n oscillate, and FET121a ~ 121na
The signal applied to the gate terminal of is output as a delay amount control voltage signal. Voltage controlled delay circuit 121
1-121n are connected in series, the total delay amount is about one clock cycle width, and the voltage control delay circuit 12
The input clock 11 and the output clock of the voltage control delay circuit 121n are controlled to be in phase with each other.

(Detailed Configuration of Second Multiphase Clock Generation Circuit 13): FIG. 23 shows the second multiphase clock generation circuit 1.
It is a detailed functional block diagram of 3. In FIG. 23, the second
The multi-phase clock generation circuit 13 is composed of voltage control delay circuits 1311 to 131 (n-1) connected in series.

In the second multi-phase clock generation circuit 13, the clock given from the clock input terminal is given to the voltage control delay circuit 1311, and the delay amount control voltage signal given from the delay amount control voltage input terminal is FET 1311a. ~
The gate terminal of 131 (n-1), and these F
The voltage control delay circuits 1311 to 131 (n-1) are controlled by the voltages of the gate terminals of the ETs 1311a to 131 (n-1).
Of the voltage control delay circuits 1311 to 1 by controlling the propagation delay of
The output signal of 31 (n-1) is output as an n-phase multi-phase clock output signal.

(Effects of the Fifth Embodiment): According to the bit phase synchronization circuit of the fifth embodiment described above, the effects of the first embodiment described above can be obtained, and
By using the first multi-phase clock generation circuit 12 and the second multi-phase clock generation circuit 13, it is not necessary for the multiplication PLL circuit 2A itself to generate the multi-phase clock, and the circuit system of the multiplication PLL circuit can be selected. The width (degree of freedom) can be expanded.

[Sixth Embodiment]: The bit phase synchronization circuit of the sixth embodiment is for achieving bit phase synchronization with respect to parallel reception data composed of a plurality of reception data of the same bit rate.

FIG. 24 is a functional block diagram of the bit phase synchronizing circuit of the sixth embodiment. In FIG. 24, the bit phase synchronization circuit includes a multiplication PLL circuit 2 and a selector 3
A reset VCO circuit 4, a selector control circuit 6,
The data latch circuits 14-i to 14-2 and the timing determination circuit 5 are included. Since the same functional components as those of the first embodiment described above are designated by the same reference numerals, the description of the same components will be omitted. The bit phase synchronization circuit takes in the parallel data 7i to 72 to 71, and while the timing judgment circuit 5 performs the timing judgment on the data 71 of these parallel data,
The reproduced data 8i to 82 to 81 which are bit phase synchronized are output.

The data latch circuit 14-i fetches the received data 7i and outputs the reproduced data 8i in synchronization with the bit phase by the three-phase clock from the reset VCO circuit 4. Similarly, the data latch circuit 14-2 also takes in the received data 72, reproduces the reproduced data 82 by synchronizing the bit phase with the three-phase clock from the reset VCO circuit 4.
Is output. The timing determination circuit 5 uses the received data 71
The reproduction data 81, the reproduction data clock, and the determination result signal are output in synchronization with the bit phase by the three-phase clock from the reset VCO circuit 4, and the determination result signal is used as the determination result of the selector control circuit 6. Apply to the signal input terminal.

(Operation): Next, the operation of the bit phase synchronizing circuit of FIG. 24 will be described. The i-parallel parallel data whose phase is unknown is input to the parallel data 71 to 7i (provided that the mutual phase relationships in the parallel data are synchronized and the phases are aligned with each other). Among them, the parallel data input signal 71 is master data as a representative of the timing information of the parallel data input, and the other data is slave data, and the parallel data input signal 71 is input to the data input terminal of the timing determination circuit 5. , Parallel data input signal 72-
7i are data latch circuits 14-2 to 14-i, respectively.
Is input to the data input terminal.

In the timing judgment circuit 5, the input 3
If the phase relationship between the phase clock 0 and the data is appropriate, it is determined as it is, and if it is inappropriate, it is determined whether the clock phase should be advanced or delayed, and the result is output as a determination result signal. Output from the terminal.

The timing judgment circuit 5 and the data latch circuits 14-2 to 14-i latch the input data by the input three-phase clock 0,
The latch output signals are output as reproduction parallel data output signals 81 to 8i from the respective data output terminals.

In the timing judgment circuit 5, the clock used for latching the input data is output from the clock output terminal, and the output is output as the reproduction parallel data clock 9. Here, the data latch circuits 14-2 to
In 14-i, the delay relationship is adjusted so that the timing relationship between the input data and the input clock is the same as the timing relationship between the input data and the input clock in the timing determination circuit 5. The determination result signal of the timing determination circuit 5 is input to the determination result signal input terminal of the selector control circuit 6.

(Effect of Sixth Embodiment) According to the bit phase synchronization circuit of the sixth embodiment, one of parallel data inputs is used as master data as a representative of timing information, Other data is used as slave data, and the timing judgment circuit 5 is used for the master data.
Timing determination is performed with the master data, and the output of the reset VCO circuit 4 is used to latch the slave data in the same manner as the master data. Bit phase synchronization for parallel data can be performed without adding hardware.

[Seventh Embodiment of Bit Phase Synchronizing Circuit of the Present Invention]: The bit phase synchronizing circuit of the seventh embodiment is for achieving bit phase synchronization with parallel received data. The bit phase synchronization based on the timing determination is performed on all the received data.

FIG. 25 is a functional block diagram of the bit phase synchronizing circuit of the seventh embodiment. In FIG. 25, the bit phase synchronization circuit includes a multiplication PLL circuit 2 and a selector 3
A reset VCO circuit 4, a selector control circuit 6,
Timing determination circuits 51 to 5i and determination result OR circuit 1
And 5.

The timing judgment circuit 51 uses the received data 7
1 is taken in and the reproduction parallel data, the reproduction parallel data clock, and the judgment result signal are output by synchronizing the bit phase using the three-phase clock from the reset VCO circuit 4, and the judgment result signal is the judgment result OR circuit. Given to 15. The timing determination circuit 5i uses the received data 7i
Is taken in, the reproduction parallel data and the judgment result signal are output by synchronizing the bit phase using the three-phase clock from the reset VCO circuit 4, and the judgment result signal is given to the judgment result OR circuit 15. Judgment result OR circuit 15
Performs a logical sum operation of the decision result signals from the timing decision circuits 51 to 5i and gives the operation result signal to the decision result signal input terminal of the selector control circuit 6.

(Operation): Next, the operation of the bit phase synchronization circuit of FIG. 25 will be described. The reception parallel data input terminals 71 to 7i receive i parallel reception parallel data whose phase is unknown (however, it is assumed that the mutual phase relations in the reception parallel data are synchronized and the phases are almost uniform. .) And the parallel data thereof are input to the data input terminals of the timing determination circuits 51 to 5i, respectively.

In each of the timing judgment circuits 51 to 5i, with respect to the phase relationship between the clock and the data input individually,
If it is appropriate, it is determined as it is, and if it is inappropriate, it is determined whether the clock phase should be advanced or delayed, and the result is output from the determination result signal output terminal.

In the timing judgment circuits 51 to 5i, each input data is latched by the input three-phase clock 0, the latch output is output from the data output terminal, and the output is the reproduction parallel data output signal. 81 to 8i, and the timing determination circuit 51 is output.
Outputs the clock used for latching the input data from the clock output terminal, and the output is output as the clock for reproduced parallel data.

The decision result signals of the timing decision circuits 51 to 5i are input to the decision result signal inputs of the decision result OR circuit 15, respectively. In the decision result OR circuit 15, all the inputted decision result signals are ORed and the result is outputted from the decision result signal output terminal. This signal is inputted to the decision result signal input terminal of the selector control circuit 6. Given.

(Effect of Seventh Embodiment): According to the bit phase synchronization circuit of the seventh embodiment described above, bit phase synchronization can be performed for all bit lines of parallel received data. Therefore, even with respect to the reception parallel data in which the phase skew (phase shift) has occurred, the effect for the serial data in the above-described first embodiment to fifth embodiment is obtained, and large hardware is added. It can be applied without doing.

[Eighth Embodiment of Bit Phase Synchronous Circuit of the Present Invention]: In the eighth embodiment, the received data in the burst cell format with unknown phase and the reset for displaying the boundary of the burst cell In a system to which a signal and a reference clock having a frequency that is the same as the bit rate of received data or that is m times (m> 0) close to each other are input, a multiplication PL that generates a first multiphase clock of n phases
An L circuit, a toothless clock generation circuit, an n: 1 selection selector circuit, and a reset VCO circuit that can control an oscillation phase of an output clock by a phase control signal and generate an n-phase second multi-phase clock , A stable phase selection circuit, a timing determination circuit, and a selector control circuit.

The stable phase selection circuit latches the input burst data with the second multi-phase clock, and uses a fixed pattern or a combination of a plurality of fixed patterns arranged at the head of the burst cell for the latched data. When the detection is performed and it is detected simultaneously in three or more adjacent phases, the data latched in any three continuous phases among them is selectively output without losing the data, including the detected fixed pattern. Further, the data latched in the intermediate phase of the three phases is output as reproduction data, and these operations are configured to perform "multi-phase clock selection type bit phase operation" in which a single operation is performed after the reset signal is input.

Further, the multiplication PLL circuit, the toothless clock generation circuit, the n: 1 selection selector circuit, and the reset VCO.
The reference clock is input to the multiplication PLL circuit by the circuit, the timing determination circuit, and the selector control circuit. Then, the multiplication PLL circuit multiplies the frequency to the same as or close to the bit rate of the received data and generates the first multi-phase clock, and the pulses and pulses of the toothless clock are generated from the first multi-phase clock. A switching timing signal is generated such that an active pulse rises at an intermediate position of. Select an arbitrary phase with the selector circuit from the multi-phase missing clock,
Resets the clock selected and output by the selector circuit VC
It is input as a phase control signal for the O circuit.

In the reset VCO circuit, when there is a phase control signal, oscillation phase control is performed, and when there is no phase control signal, self-oscillation is performed and a second multiphase clock is generated. Further, in the timing determination circuit, the phase relationship between the clock phase selected by the stable phase selection circuit and the burst transmission data is determined by the data latched by the three-phase clock output from the stable phase selection circuit. Then, the selector control circuit generates a selection control signal so as to select a clock having a phase according to the determination result of the timing determination circuit.

This selection control signal is configured to perform the "following bit phase synchronization operation" for controlling the selector circuit when the switching timing signal input from the toothless clock generation circuit is active.

The above-mentioned "multiphase clock selection type bit phase operation" and "following type bit phase synchronization operation" are controlled so as not to operate at the same time, and the multiphase clock selection type bit phase is set at the head of the burst cell. The bit phase synchronizing circuit is configured so that the synchronization is established by the synchronizing operation and then the synchronization is maintained by the follow-up type bit phase synchronizing operation.

FIG. 26 is a functional block diagram of the bit phase synchronization circuit of the eighth embodiment. In FIG. 1, the present bit phase synchronization circuit includes a multiplication PLL circuit 2, a selector control circuit 3, a reset VCO circuit 4A, a timing determination circuit 5A, a selector control circuit 6C, and a toothless clock generation circuit 11. , And a stable phase selection circuit 16.

A feature of the eighth embodiment is that the stable phase selection circuit 16 is provided for detecting the timing of the stable phase at the beginning of the burst cell and for synchronizing the bit phase. That is. Furthermore, the stable phase selection circuit 16 resets the multi-phase clock used for early detection of the stable phase, and the VCO circuit 4A.
To import from. For this reason, the reset VCO circuit 4 is configured so as to output a multiphase clock as shown in FIG. Furthermore, the timing determination circuit 5A is configured so that the three phase data outputs 1 to 3 from the stable phase selection circuit 16 can be fetched and a determination result signal can be output. Further, the selector control circuit 6C is configured so that it can be controlled by fetching the enable signal from the stable phase selection circuit 16 for controlling the transition from the multi-phase clock selection type bit phase synchronization operation to the follow-up type bit phase synchronization operation.

FIG. 27 is a functional block diagram of the reset VCO circuit 4A. 17 is different from the configuration (FIG. 7) of the reset VCO circuit 4 of the above-described embodiment in that the stable phase selection circuit 16 has multiphase clocks 1 to n.
In order to provide the above, the multi-phase clock 1 is output from the output of the voltage control delay 2-input NOR circuit 41, the multi-phase clock 2 is output from the output of the voltage control delay inverting circuit 43, and the voltage control delay inverting circuit 4 (n− The multiphase clock n is output from the output of 1), and the multiphase clock (n + 1) / 2 +1 is output from the output of the voltage control delay inverting circuit 42.

The stable phase selection circuit 16 takes in the reset signal from the reset signal input terminal 17, then takes in the burst cell data from the data input terminal 7, and uses the multiphase clocks 1 to n to burst cell data (for example, The preamble PR (for example, about 16 bits) in which the synchronization pattern of the head portion of (2 + 53 bytes) is arranged, the timing of the stable phase is detected early, and the data and clock synchronized with the input burst cell data are detected. Is output. As the synchronization data, the data of the most stable phase and adjacent phases are also collectively output as data outputs 1 to 3, and the timing determination circuit 5A
The data output 2 having the most stable phase is applied to the data output terminal 8. Further, the stable phase selection circuit 16 is
The synchronous clock is also given to the clock output terminal 9.

Furthermore, the stable phase selection circuit 16 outputs the enable signal inactive (high level) when the reset signal is input so that the follower type bit phase synchronization operation is not performed on the selector control circuit 6C. When synchronization is achieved by the above-described multi-phase clock selection type bit phase synchronizing operation, the enable signal is activated (low level) and the selector control circuit 6C is controlled so that the follow-up type bit phase synchronizing operation can be performed.

FIG. 28 is a functional block diagram of the stable phase selection circuit 16. In FIG. 28, the stable phase selection circuit 1
Reference numeral 6 includes a phase align circuit 161, a shift register circuit 162, a detector circuit 163, a priority encoder circuit 164, and a selector circuit 165.

The phase align circuit 161 takes in the burst cell data, takes in the multiphase clocks 1 to n, latches the input burst cell data at the respective multiphase clocks 1 to n, and outputs these latched output signals. Is used as the master clock, for example, the multiphase clock 1 is used, and the phase of the multiphase clock 1 is transferred to the shift register circuit 162.

The shift register circuit 162 uses the multi-phase clock 1 as the master clock to shift-register the n latch output signals phase-shifted by the multi-phase clock 1 from the phase align circuit 161 to the detector. It is given to the circuit 163 and the selector circuit 165. That is, this shift registration operation is an operation for extracting the preamble signal of the head portion of the input burst cell data as a parallel signal.

The detector circuit 163 combines the shift register signals of the n systems provided from the shift register circuit 163 with a logic gate circuit and the like, and preambles while overlapping the shift register signals of the three systems for each system from the first system. The pattern recognition for detecting the signal is performed, the recognition result signal is output in the n-system, and is given to the priority encoder circuit 164. That is, if the same signal is detected in three phases by pattern recognition for the shift registration signals of three adjacent phases, the recognition result signal is effectively output as if the stable phase is detected.

The priority encoder circuit 164 is
If the reset signal is received before receiving the input burst cell data, the enable signal is set to high level (inactive).
Then, the selector control circuit 6C is controlled so that the multi-phase clock selection type bit phase synchronizing operation is performed and the follow-up type bit phase synchronizing operation is not performed. Which of the n systems the system in which the n-system recognition result signal is effectively output corresponds to is read and a selection signal is given to the selector circuit 165. In addition to outputting this selection signal, the enable signal to the selector control circuit 6C is output at a low level (active) to stop the multi-phase clock selection type bit phase synchronization operation and perform the follow-up bit phase synchronization operation. .

The selector circuit 165 provides the most stable and reliable data of the three adjacent systems centering on the phase data designated by the selection signal from the n systems of shift register signals provided from the shift register circuit 162. Is output to the data output terminals 1 to 3.

The timing judgment circuit 5A takes in data outputs 1 to 3 and clocks of three phases from the stable phase selection circuit 16 and uses the clocks to judge the phase relationship between the data outputs 1 to 3 The logic levels 3 to 3 are identified, a determination result signal for controlling the phase is generated, and given to the selector control circuit 6C.

FIG. 29 is a functional block diagram of the timing determination circuit 5A. In FIG. 29, the timing determination circuit 5A includes D flip-flop circuits 523 to 525 and exclusive OR (Ex-OR gate) circuits 526 and 527. This configuration is similar to that of the above-described embodiment shown in FIGS. 8 and 10, and is particularly different in that data 1 to 3 are taken into different D flip-flop circuits 523 to 525, respectively, and each data is clocked. Of the exclusive OR circuit 526, 5
Is given to 27.

With such a configuration, when the values of data 1 and data 2 are different, the exclusive OR circuit 5
27 outputs a high level signal and controls so as to delay the oscillation phase, and when the values of data 2 and data 3 are different, the exclusive OR circuit 526 outputs a high level signal to change the oscillation phase. The exclusive OR circuits 526 and 52 are controlled so as to proceed, and when the values of the data 1 to 3 match.
7 outputs a low level signal and controls so as to maintain the oscillation phase.

The selector control circuit 6C takes in the enable signal from the stable phase selection circuit 16, controls so as to disable the follow-up bit phase synchronization operation when this signal is at the high level, and controls it when the signal is at the low level. Control to enable the phase synchronization operation. Also,
The selector control circuit 6C determines from the timing determination circuit 5A when performing the follow-up type bit phase synchronization operation by the multiplication PLL circuit 2, the toothless clock generation circuit 11, the selector circuit 3, and the reset VCO circuit 4A. The result signal is fetched, and the signal is used to delay, advance, or hold the oscillation phase.

This selector control circuit 6C can be specifically realized by slightly changing the selector control circuit 6B of FIG. 17 of the above-mentioned embodiment. For example, the enable signal can be controlled by the selector control circuit of FIG. It can be realized by giving the up-down counter circuit 614 of the circuit and controlling the operation of the counter by this.

(Operation): Next, the operation of the bit phase synchronizing circuit and stable phase selecting circuit 16 of FIG. 26 will be described.
First, at the reference clock input terminal 1, 1 / m (m> 0) of the same frequency as the bit rate of burst transmission reception data
Is input, and this clock is input to the reference clock input terminal of the multiplication PLL circuit 2.

In the multiplication PLL circuit 2, a clock having the same frequency as the bit rate of the burst transmission reception data is generated. In this multiplication PLL circuit 2, a VCO capable of generating a multiphase clock such as a ring oscillator is used to multiply a multiphase clock having a phase difference obtained by dividing one clock width of the multiplication clock into n equal parts (n ≧ 3). It is output from the multiphase clock output terminals 1 to n of the circuit 2.

Here, the phase relationship between the multiphase clocks 1 to n is a signal in which the multiphase clock 1 is the head of the phase and the phase is delayed as the argument increases. In addition, the control voltage for controlling the frequency of this VCO is set to the reset VCO circuit 4
It is output from the frequency control voltage output terminal in order to be applied to.

Multiphase clocks 1 to n of the multiplication PLL circuit 2
Are selected signal input terminals 1 to 1 of the selector circuit 3, respectively.
n and the multi-phase clock input terminals 1 to n of the selector control circuit 6, respectively.

In the toothless clock generation circuit 11, k is input for each of the input multiphase clocks 1 to n.
A so-called toothless clock, in which only one of the clock pulses of (k is an integer of 2 or more) cycles is made to stand, and the pulse generated for each phase is 2 It is generated so as to fit within the clock cycle width.

Here, the value of k is the value of the reset VCO circuit 4
When the self-oscillation occurs, the deviation of the oscillation phase of the reset VCO circuit 4 occurs due to the difference between the oscillation frequency of the multiplied clock of the multiplication PLL circuit 2 and the free-running oscillation frequency of the reset VCO circuit 4, but its width is not a problem. The number of cycles.

The switching timing signal is generated so that an active pulse rises at an intermediate position between the pulses of the toothless clock. The selector circuit 3 outputs one of the signals input to the selected signal input terminals 1 to n according to the selection control signal from the signal output terminal.
The signal output from the signal output terminal of the selector circuit 3 is
It is input to the phase control signal input terminal of the reset VCO circuit 4.

In the reset VCO circuit 4, the phase of the output clock is forcibly controlled by the phase of the pulse of the signal input from the phase control signal input terminal, and by inputting the pulse signal having the phase of n phase, respectively. An n-phase output clock corresponding to is generated. The reset VCO circuit 4 is applied from the frequency control voltage output terminal of the multiplication PLL circuit 2 to the frequency control voltage input terminal of the reset VCO circuit 4 when the pulse signal is not input to the phase control signal input terminal. Self-oscillating at a frequency determined by voltage.

Here, the VC which constitutes the multiplication PLL circuit 2
The reset VCO circuit 4 has the same circuit configuration for O and the VCO that configures the reset VCO circuit 4.
Performs free-running oscillation at a frequency substantially matching the oscillation frequency of the multiplication PLL circuit 2.

The reset VCO circuit 4 outputs multiphase clocks having a phase difference obtained by equally dividing one clock width into n from the multiphase clock output terminals 1 to n. The multiphase clocks 1 to n of the reset VCO circuit 4 are input to the multiphase clock input terminals 1 to n of the stable phase selection circuit 16, respectively.

The received data input terminal 7 is supplied with the data of the burst cell format whose phase is unknown, which is transmitted from the opposite device, and the data is inputted to the data input terminal of the stable phase selection circuit 16.

In the stable phase selection circuit 16, the input data is latched by the multi-phase clocks 1 to n, and the data is multi-phase clock 1 (here, it is not necessary to be the multi-phase clock 1; To n)) to detect an arbitrary fixed pattern. The arbitrary fixed pattern is, for example, a preamble pattern provided for timing extraction in a burst cell, or a frame pattern inserted in generally used data transmission.

When the detection of this fixed pattern occurs simultaneously in three adjacent phases, it is judged that the intermediate phase is a phase in which data can be latched at stable timing, and the data latched in these three phases are The data is output to the data output terminals 1 to 3, respectively. Here, it is assumed that the smaller the number of arguments, the data latched by the clock of the faster phase.

The above operation is an operation that is performed once after the reset signal is input, and the reset VC
Since the stable phase selection circuit 16 may malfunction when the O circuit 4 receives the phase control, the enable signal is made inactive and the operation of the selector control circuit 6 is disabled. By controlling in this way, the initial bit phase synchronization can be established without losing the data including the fixed pattern to be detected.

Data output terminal 2 of stable phase selection circuit 16
Data is output to the reproduction data output terminal 8. The multiphase clock 1 is output to the reproduction data clock output terminal 9. The enable signal is also input to the enable signal input terminal of the selector control circuit 6.

When the data 1 and the data 2 are different with respect to the input data 1 to 3, the timing judgment circuit 5A judges to delay the oscillation phase of the multi-phase clock of the reset VCO circuit 4A. When the result signal is output and the values of the data 3 and the data 2 are different, the determination result signal is output so as to accelerate the oscillation phase of the multi-phase clock of the reset VCO circuit 4A, and the data 1 to 3 are output. If the values match, the determination result signal is output so that the oscillation phase of the multiphase clock of the reset VCO circuit 4 is held.

The determination result signal of the timing determination circuit 5A is input to the determination result signal input terminal of the selector control circuit 6C. In the selector control circuit 6C, since the last time the selector control circuit 6C changed the selection control signal of the selector circuit 3, a protection time is taken so as to be accurately reflected in the determination result signal of the timing determination circuit 5A, and thereafter, A selection control signal is output from the selection control signal output terminal of the selector control circuit 6C in response to the determination result signal input to. However, if the enable signal is inactive, its operation is forced to be disabled. The selection control signal is a signal that can individually control the selector circuit 3 because it is individually prepared for each of the selected signals 1 to n of the selector circuit 3.

Here, as the protection time in the selector control circuit 6C, from the selector control circuit 6C to the selector circuit 3
→ Reset VCO circuit 4A → Stable phase selection circuit 16 → Timing determination circuit 5A → Selector control circuit 6C requires a time longer than the feedback time in the path.

Here, the above-mentioned selection control signal is output from the selection control signal output terminal in the multiplication PLL.
It is latched by the multi-phase clock 1 output from the circuit 2, and the latch takes in a new selection control signal when the switching timing signal is active, and holds the value of the latch when the switching timing signal is inactive. To do.

That is, the selector circuit 3 is controlled in a region where the switching timing signal is active, and at that timing, the selected signals 1 to n of the selector circuit 3 are controlled.
The input of is stable as an inactive value as the phase control signal of the reset VCO circuit 4. Therefore, at the time of switching, noise is not input to the phase control signal input terminal of the reset VCO circuit 4.

The reset VCO circuit 4 receives the phase control almost once every k cycles regardless of the steady state in which the switching does not occur and the switching, and the frequency control input while the active pulse of the phase control signal is not input. According to the voltage applied to the terminal, free-running oscillation is performed at a frequency that substantially matches the oscillation frequency of the multiplication PLL circuit 2.

(Effects of the eighth embodiment of the present invention):
According to the eighth embodiment of the present invention described above, since a high-speed clock that is an integral multiple of the transmission rate is not used to generate a multi-phase clock, when configured as an LSI, data of this transmission rate is digitally processed. It can be realized with as many devices as possible.

Further, the stable phase selection circuit can establish the bit phase synchronization in a short cycle without losing data from the beginning of the burst cell data which is the transmission data. After that, the oscillation phase of the reset VCO circuit is set. By controlling, it is possible to follow the fluctuation of the phase of the burst cell data.

That is, by combining the multi-phase clock selection type bit phase synchronization method and the follow-up type bit phase synchronization method, there is a phase fluctuation of one clock cycle width or more between the received burst cell data and the reference clock. Even if it occurs, the burst cell data can be reproduced without the loss of synchronization. This has the effect of increasing the degree of freedom in the clock distribution design of the transmission system and the cell length design of the burst cell. The clock distribution design is a design for determining a distribution wiring method when distributing a reference clock from a reference clock generation unit to a unit including a plurality of bit phase synchronization circuits in a transmission system.

Further, specifically, by adopting the configuration as shown in FIG. 28 for the stable phase selection circuit, it can be realized by combining a gate circuit and a logic circuit, and it is necessary to perform complicated processing. Since it does not exist, high-speed operation can be realized, it is suitable for LSI, and miniaturization is easy.

More specifically, the follow-up bit phase synchronization operation is mainly performed mainly by the multiplication PLL circuit 2, the toothless clock generation circuit 11, the selector circuit 3, and the reset VCO circuit 4A.
Since the timing determination circuit 5A and the selector control circuit 6C are configured to perform the above, it is possible to effectively perform the synchronization holding function with respect to the phase variation and frequency variation of the received burst cell data.

Therefore, no matter what phase the received data is fetched, it is very stable, and the bit phase synchronization for outputting the synchronization data and the synchronization clock in which the bit phase synchronization is achieved very quickly with a simple structure. A circuit can be realized. In particular, it is very effective for bit phase synchronization in high speed data transmission.

(Other Embodiments) (1) In the above embodiment, the frequency control voltage of the VCO forming the multiplication PLL circuit is applied to the frequency control voltage signal of the reset VCO circuit. If the free-running frequency of the VCO circuit is adjusted by an external input or the like so as to be close to the oscillation frequency of the multiplying PLL circuit, the frequency control voltage signal of the reset VCO circuit is used as a VCO that constitutes the multiplying PLL circuit.
It can be realized without applying the frequency control voltage signal.

(2) Further, the reference clock input terminal is
A clock having a frequency m times (m> 0) that is the same as the bit rate of the received data is input, but a frequency close to (neighboring) may be used.

(3) Further, although the VCO capable of obtaining the output of the multi-phase clock is used for the multiplication PLL circuit, the multiplication PLL circuit which cannot obtain the output of the multi-phase clock is combined with the multi-phase clock generation circuit. A multiplying PLL circuit that can output multi-phase clocks can be used as an alternative.

(4) Furthermore, the VCO of the multiplication PLL circuit
And the VCO of the reset VCO circuit have the same circuit configuration V
Although CO is used, different circuit configurations may be used.

(5): In the eighth embodiment, the reset VCO circuit 4A supplies the n-phase clock to the stable phase selection circuit 16 to detect the stable phase timing of the received burst cell data. The n-phase clock is a multiplication PLL.
The output of the circuit 2 is an n-phase corresponding to the n-phase clock. As another embodiment, even if the output of the multiplication PLL circuit 2 is output in the n-phase, the reset VCO circuit 4A outputs in the n-phase. The present invention is not limited to this, and a multi-phase clock having three or more phases is sufficient. For example, the output of the multiplication PLL circuit 2 is output in 6 phases, the output of the reset VCO circuit 4A is thinned out and output in 3 phases, or the output of the multiplication PLL circuit 2 is set to 4 phases and the output of the reset VCO circuit 4A is set to 3 outputs. It is also possible to output in phase.

(6) Furthermore, in the above-described eighth embodiment, burst cell data is taken as an example of the received data, but the preamble PR signal is added to the variable length packet even if the cell structure is not used. It can also be applied in a form. Further, the preamble PR signal is preferably pattern data having two or more data changes. Further, the present invention can be applied not only to bit phase synchronization for burst data but also for bit synchronization for continuously transmitted data.

(7) Furthermore, in FIG. 26 of the above-described eighth embodiment, the toothless clock generation circuit 11 is provided between the multiplication PLL circuit 2 and the selector circuit 3, but another embodiment is provided. Alternatively, the multi-phase clock output from the multiplication PLL circuit 2 may be directly applied to the selector circuit 3.

[0192]

As described above, according to the first aspect of the invention, the n-phase clock and the frequency control signal are generated from the reference clock by the PLL circuit, and the clock of any one of these n-phase clocks is selected. Selectively output with a control signal, and take in the clock that is selectively output as a phase control signal,
The frequency control signal is also taken in, the phase control and the frequency control are performed by the reset VCO circuit to generate the first clock as the synchronous clock, the phase difference between the first clock and the received data is detected, and the phase difference is detected. Since the selection control signal is generated based on the signal, and the received data is latched and output at the first clock to output the bit phase synchronization data,
It is possible to realize a bit phase synchronization circuit that outputs data and a clock with very stable bit phase synchronization with a very simple structure and very quickly no matter what phase the received data is captured. . In particular, it is very effective for bit phase synchronization in high speed data transmission.

A second aspect of the invention is provided with the bit phase synchronization circuit of the first aspect of the invention described above, and further, the bit phase synchronization is achieved with respect to any one of the parallel reception data, and the remaining reception is performed. The data is latched and output using the first clock, which is a synchronous clock,
Since the bit phase synchronization data for each received data is output, the bit phase synchronization for any one of the parallel received data can be achieved, making the bit phase synchronization for the entire parallel received data very stable. Moreover, it can be performed very quickly with a simple structure.

Further, in the third invention, the initial bit phase is synchronized with the bit data of the head portion of the received data by comparison detection with the phase-shifted multi-phase clock for stable phase detection, and the initial bit phase is obtained. After synchronization is established, fluctuation tracking control for phase fluctuations or frequency fluctuations of received data after the first bit data is performed and the bit phase synchronization state is maintained, so not only bit phase synchronization for continuous transmission data, but especially It is possible to realize a bit phase synchronization circuit that performs bit phase synchronization on burst data in a very short cycle.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram of a bit phase synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional bit phase synchronization circuit.

FIG. 3 is an explanatory diagram of a reset VCO in the bit phase locked loop circuit according to the first embodiment.

FIG. 4 is an operation timing chart (No. 1) of the bit phase locked loop circuit according to the first embodiment.

FIG. 5 is an operation timing chart (No. 2) of the bit phase locked loop circuit according to the first embodiment.

FIG. 6 is a functional configuration diagram of a multiplication PLL circuit of the bit phase synchronization circuit according to the first embodiment.

FIG. 7 is a detailed functional configuration diagram of a reset VCO of the bit phase locked loop circuit according to the first embodiment.

FIG. 8 is a functional configuration diagram of a timing determination circuit of the bit phase synchronization circuit according to the first embodiment.

FIG. 9 is a functional configuration diagram of a selector control circuit of the bit phase synchronization circuit of the first embodiment.

FIG. 10 is a functional configuration diagram of a timing determination circuit in the bit phase synchronization circuit according to the second embodiment of the present invention.

FIG. 11 is an operation timing chart (No. 1) of the bit phase locked loop circuit according to the third embodiment of the present invention.

FIG. 12 is an operation timing chart (No. 2) of the bit phase synchronization circuit according to the third embodiment.

FIG. 13 is a functional configuration diagram of a selector control circuit of the bit phase synchronization circuit of the third embodiment.

FIG. 14 is a functional configuration diagram of a bit phase synchronization circuit according to a fourth embodiment of the present invention.

FIG. 15 is an operation timing chart (No. 1) of the bit phase synchronization circuit according to the fourth embodiment.

FIG. 16 is an operation timing chart (No. 2) of the bit phase synchronization circuit according to the fourth embodiment.

FIG. 17 is a functional configuration diagram of a selector control circuit of the bit phase synchronization circuit according to the fourth embodiment.

FIG. 18 is a functional configuration diagram of a toothless clock generation circuit of the bit phase synchronization circuit according to the fourth embodiment.

FIG. 19 is a functional configuration diagram of a bit phase synchronization circuit according to a fifth embodiment of the present invention.

FIG. 20 is an operation timing chart (No. 1) of the bit phase synchronization circuit of the fifth embodiment.

FIG. 21 is an operation timing chart (No. 2) of the bit phase synchronization circuit of the fifth embodiment.

FIG. 22 is a functional configuration diagram of a first multi-phase clock generation circuit of the bit phase synchronization circuit of the fifth embodiment.

FIG. 23 is a functional configuration diagram of a second multiphase clock generation circuit of the bit phase synchronization circuit of the fifth embodiment.

FIG. 24 is a functional configuration diagram of a bit phase synchronization circuit according to a sixth embodiment of the present invention.

FIG. 25 is a functional configuration diagram of a bit phase synchronization circuit according to a seventh embodiment of the present invention.

FIG. 26 is a functional configuration diagram of a bit phase synchronization circuit according to an eighth embodiment of the present invention.

FIG. 27 is a functional configuration diagram of a reset VCO circuit of the bit phase locked loop circuit according to the eighth embodiment.

FIG. 28 is a functional configuration diagram of a stable phase selection circuit of the bit phase synchronization circuit of the eighth embodiment.

FIG. 29 is a functional configuration diagram of a timing determination circuit of the bit phase synchronization circuit of the eighth embodiment.

[Explanation of symbols]

1 ... Reference clock input terminal, 2 ... Multiplication PLL circuit, 3 ...
Selector 4, 4A ... Reset VCO circuit 5, 5A ...
Timing determination circuit, 6, 6A, 6B, 6C ... Selector control circuit, 7 ... Received data input terminal, 8 ... Reproduced data output terminal, 9 ... Reproduced data clock output terminal, 10 ... Received data identification error output terminal, 11 ... Missing tooth clock generation circuit, 14-2 to 14-i ... data latch circuit, 1
6 ... Stable phase selection circuit, 211-21n ... Voltage control delay inverting circuit, 22 ... Phase frequency detection circuit, 23 ... Charge pump circuit, 24 ... Low pass filter circuit, 25 ... M frequency dividing circuit, 41 ... Voltage control delay 2 Input NOR circuit, 42-
4n ... Voltage controlled delay inverting circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuichi Matsumoto 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (10)

[Claims] 1. A bit phase synchronizing circuit for performing bit phase synchronization between received data and a first clock having a clock frequency a times (a is a natural number) or 1 / a times the bit rate of the received data, M times the clock frequency of the first clock (m> 0)
N phase in which the 1-bit width of the received data is shifted to the n phase (n is a natural number of 2 or more) at a clock frequency that is a times or 1 / a times the bit rate of the received data from the reference clock of the frequency And a n-phase clock generating means for generating a frequency control signal by the PLL circuit, and a selecting means for selectively outputting a clock of any one of the n-phase clocks by a selection control signal. A clock generating means for generating the first clock while performing the phase control and the frequency control by the reset VCO circuit while capturing the clock selected and output by the selecting means as a phase control signal and also capturing the frequency control signal. , A phase difference between the first clock and the received data is detected, and the selection control signal is generated based on the phase difference signal. Together give the selection means, the bit phase locked loop circuit is characterized in that a timing determination output means for outputting a bit phase synchronization data latches outputting said received data at the first clock. 2. The clock generation means, when a significant phase control signal is input, controls the phase of the first clock according to the phase of the significant phase control signal,
2. The bit phase synchronization according to claim 1, wherein when the significant phase control signal is not input, the reset VCO circuit is self-oscillated at a frequency determined by the frequency control signal to generate the first clock. circuit. 3. The selection means sets a predetermined protection time as a time from when the selection switching output is performed until the phase difference signal is obtained by the timing determination output means, and within the predetermined protection time after the selection switching. 3. The bit phase synchronization circuit according to claim 1, wherein the mask processing is performed so as not to give a significant clock to the clock generation means. 4. A bit phase synchronizing circuit for performing bit phase synchronization between received data and a first clock having a clock frequency a times (a is a natural number) or 1 / a times the bit rate of the received data, M times the clock frequency of the first clock (m> 0)
N phase in which the 1-bit width of the received data is shifted to the n phase (n is a natural number of 2 or more) at a clock frequency that is a times or 1 / a times the bit rate of the received data from the reference clock of the frequency And a n-phase clock generation means for generating a frequency control signal by this PLL circuit, and an n-phase clock for which each phase clock of the n-phase clock is subjected to a toothless process. An n-phase tooth-missing clock generating means for generating a tooth-missing clock, a selecting means for selectively outputting a clock having any phase of the n-phase tooth-missing clocks by a selection control signal, and a selecting output by the selecting means. The reset VCO circuit performs the phase control and the frequency control while taking in the generated clock as the phase control signal and also taking in the frequency control signal. A clock generating means for generating a clock, a phase difference between the first clock and the received data is detected, the selection control signal is generated based on the phase difference signal and given to the selecting means, and A bit phase synchronization circuit, comprising: timing determination output means for latching and outputting the received data with a first clock to output bit phase synchronization data. 5. A bit phase synchronizing circuit for performing bit phase synchronization between received data and a first clock having a clock frequency a times (a is a natural number) or 1 / a times the bit rate of the received data, M times the clock frequency of the first clock (m> 0)
A first clock for generating a second clock having a clock frequency which is a times or 1 / a times the bit rate of the received data from a reference clock having a frequency of 1) by a PLL circuit and a frequency control signal by the PLL circuit. Means, a toothless clock generating means for generating a toothless clock that has been subjected to toothless processing from the second clock, and a 1-bit width of the received data is n (n is 2) from the second clock. A delay amount control signal for generating an n-phase toothless clock shifted to the above natural number) phase is generated, and the n-phase tooth is generated using the toothless clock and the delay amount control signal. An n-phase missing clock generating means for generating a missing clock, and a selecting means for selectively outputting a clock having any one phase of the n-phase missing clocks by a selection control signal, A clock second generation means for generating the first clock while taking in the clock selected and output by the selecting means as a phase control signal and also taking in the frequency control signal and performing the phase control and the frequency control in the reset VCO circuit. A phase difference between the first clock and the received data is detected, the selection control signal is generated based on the phase difference signal, and the selection control signal is given to the selecting means. A bit phase synchronization circuit, comprising: timing determination output means for latching and outputting data to output bit phase synchronization data. 6. A circuit for performing bit phase synchronization with respect to parallel reception data composed of a plurality of reception data having the same bit rate, wherein the parallel reception data and the bit rate of each reception data are a times (a is a natural number) or A bit phase synchronizing circuit for performing bit phase synchronization with a first clock having a clock frequency of 1 / a times, wherein the bit phase synchronizing circuit according to any one of claims 1 to 5 includes: Bit phase synchronization is performed for any one of the received data, and latch output is performed for the other remaining received data using the first clock, and bit phase synchronized data for each received data is output. Characteristic bit phase synchronization circuit. 7. A circuit for performing bit phase synchronization on parallel reception data composed of a plurality of reception data having the same bit rate, wherein the parallel reception data and the bit rate of each reception data are a times (a is a natural number) or 1 A bit phase synchronization circuit for performing bit phase synchronization with a first clock having a clock frequency of / a times, which is m times (m> 0) the clock frequency of the first clock.
PLL circuit and reset VC from the reference clock of frequency
A clock generating means for generating the first clock while performing the phase control and the frequency control by the O circuit, the selection circuit, the frequency control signal, and the selection control signal, and the position of the first clock and the received data. The phase difference is detected, and the selection control signal is generated based on the respective phase difference signals and given to the clock generation means, and at the same time, the received data is latched out by the first clock to output the bit phase synchronization data. A bit phase synchronizing circuit comprising: a timing judgment output means for outputting. 8. A bit phase synchronizing circuit which outputs a synchronizing clock bit-synchronized with received data and synchronizing data, wherein a stable phase is detected for bit data at a leading portion of the received data. Initial bit phase synchronization means for synchronizing the initial bit phase by detecting the comparison with the phase-shifted multi-phase clock and outputting the synchronous data and the synchronous clock, and the bit data of the head portion after the initial bit phase synchronization is established. A fluctuation tracking type bit phase synchronizing means for performing fluctuation tracking control for subsequent phase fluctuations or frequency fluctuations of received data, maintaining the bit phase synchronization state, and continuously outputting the synchronization data and the synchronization clock. A bit phase synchronization circuit characterized by. 9. The initial bit phase synchronization means samples the received data by a phase-shifted N-phase (N is a natural number of 3 or more) multiphase clock, and the sampled data is The most stable recognition of the bit data of the leading portion from the received data phase changing section for changing the phase with each of the clocks of that phase and outputting it, and the received data of the N phase system with the changed phases. 9. The bit phase synchronization according to claim 8, further comprising: a stable phase data selection unit that selectively outputs the synchronization data of the possible phase system and the synchronization clock, and outputs an initial bit phase synchronization establishment signal. circuit. 10. The fluctuation tracking type bit phase synchronizing means generates a multi-phase clock of M phases (M is a natural number of 3 or more) shifted from the reference clock by a PLL circuit, and controls the frequency by the PLL circuit. A M-phase clock generation / selection unit that generates a signal and selectively outputs a clock of one of the M-phase clocks by a selection control signal; and a clock of the selected phase as a phase control signal, The frequency control signal is also taken in and reset V
While performing phase control and frequency control in the CO circuit, the above N
An N-phase clock generator that generates and provides a multi-phase clock for each phase, detects a phase difference between the synchronous clock and the synchronous data, and provides the initial bit phase synchronization establishment signal based on the phase difference signal. 10. The bit phase according to claim 8 or 9, further comprising: a phase difference detection / selection control unit that generates and provides the selection control signal for selecting a clock having a phase for ensuring the bit phase synchronization. Synchronous circuit.