JPH09149017A - Pll circuit and bit phase synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bit phase synchronization circuit and a functional phase locked loop(PLL) circuit to realize the bit phase synchronization circuit in which data and a clock subject to bit phase synchronization are outputted quickly with a simple configuration and malfunction against noise is improved very stably even when received data are received at any phase. SOLUTION: A phase control circuit 4b receives a phase control signal and a phase switching signal and when the phase switching signal is given at a high level (active), a reset VCO circuit 4a is oscillated in the phase shift mode by the phase control signal. Furthermore, when the phase switching signal is given at a low level (inactive), a phase frequency detection circuit 42 is controlled by the phase control signal to conduct multiplication PLL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop).
The p) circuit and the bit phase synchronization circuit are suitable for bit phase synchronization in high-speed data transmission such as a transmission system or a switching system.

[0002]

2. Description of the Related Art Generally, as a technique of a bit phase synchronizing circuit, for example, there is a method of selecting a clock of a phase from which a timing with data is judged to be proper from a multiphase clock. The outline of the technique of this system will be described with reference to the explanatory diagram of FIG. In FIG. 2, the multiphase clock is input to the selector circuit A, and the selector circuit A outputs one of the multiphase clocks input according to the selector control signal, and the clock is the timing determination circuit B.
And the received data is input to the timing determination circuit B. The timing judgment circuit B judges whether or not the timings of the input clock and the input data are proper, outputs the judgment result signal, and the judgment result signal is input to the clock selection control circuit C. This clock selection control circuit C
Then, a selector control signal is generated from the determination result signal and output to the selector circuit A. By repeating such operations, bit phase synchronization is established.

[0003]

However, in the above-mentioned conventional circuit configuration, since the clock is switched by the selector circuit A, noise is superimposed on the clock in general selector control, and this is prevented. In order to achieve this, it is necessary to complicate the selector control and elaborately make the clock selection control circuit and the selector circuit for timing adjustment, and such a technology is extremely difficult. There is a problem that is very difficult.

From the above, no matter what phase the received data is taken in, it is very stable and the data and clock can be output in a bit phase synchronized quickly with a simple structure, and noise is generated. There is a demand for providing a bit phase synchronization circuit capable of improving the malfunction of the above and a functional PLL circuit for realizing such a bit phase synchronization circuit.

[0005]

Therefore, the invention of claim 1 comprises a reset VCO circuit and a phase comparison control circuit, and supplies an input phase control signal to the phase comparison control circuit to perform a PLL operation. In the above, the above-mentioned problems are solved by the following characteristic configurations.

That is, according to the invention of claim 1, the "phase switching signal input terminal" for applying the phase switching signal and the phase control signal when the phase switching signal applied to the phase switching signal input terminal is in a predetermined state. A signal is applied to the reset VCO circuit to control the oscillation of only the reset VCO circuit to perform an oscillation operation in the phase shift mode, and the phase switching signal applied to the phase switching signal input terminal is in a state other than the predetermined state. In the state, the phase control signal is provided to the phase comparison control circuit, and the "phase control means" for controlling the PLL operation is provided.

By adopting such a configuration, not only the PLL operation is performed only by the phase control signal as in the conventional case, but also the state of the newly provided phase switching signal (for example, by the newly provided phase control means) (for example, The 1/0 signal) enables the oscillation operation in the phase shift mode and the normal PLL operation. Therefore, it is possible to realize a functional PLL circuit which is not available in the past. Furthermore, it is possible to expect an effect of performance improvement when such a PLL circuit is applied to a bit phase synchronization circuit. The phase comparison control circuit includes a charge pump circuit and a low pass filter circuit.

According to the invention of claim 2, received data,
A bit phase synchronization circuit for establishing a bit phase synchronization with a first clock having a clock rate of 1 / a or a times the bit speed of the received data, wherein the first phase M times the clock frequency of the clock (m
A clock frequency of a times or 1 / a of the bit rate of the received data from the reference clock having a frequency of> 0), and 1 bit width of the received data is n (n is an integer of 2 or more)
A phase-shifted n-phase clock is generated by a PLL circuit n
The phase clock generating means generates an n-phase tooth-missing clock obtained by performing tooth-missing processing on each of the n-phase clocks, and between the pulses of the tooth-missing clock. An n-phase missing clock generating means for generating a switching timing signal, a selecting means for selectively outputting a clock having any one of the n-phase missing clocks by a selection control signal, the first clock and the above A phase difference from the received data is detected, the selection control signal is generated based on the phase difference signal and the switching timing signal, and the selection control signal is given to the selection means.
In the bit phase synchronizing circuit including the timing determination output means for latching the received data with the clock and outputting the bit phase synchronizing data, the above problem is solved by the following characteristic configuration. .

That is, the invention of claim 2 comprises the PLL circuit of claim 1, wherein the clock selected and output by the selecting means is fetched as a phase control signal and a phase switching signal is fetched. Whether the PLL circuit of the clock generating means is in a locked state based on the "clock generating means" for generating the first clock, the clock generated by the n-phase clock generating means, and the first clock. And a "lock determination means" for outputting a lock determination result signal, wherein the timing determination output means generates a phase switching signal from the switching timing signal, the lock determination result signal and the phase difference signal. It is provided to the PLL circuit of the clock generation means.

By adopting such a configuration, when the normal PLL circuit of the n-phase clock generation means and the PLL circuit of claim 1 of the clock generation means are in the unlocked state, claim 1 is described. The PLL circuit can be stably locked in. Further, since the lock operation state of the PLL circuit according to claim 1 of the clock generation means is monitored from the clocks of both the PLL circuits, a phase switching signal from the lock state and the other switching timing signal and the phase difference signal. And a clock generation means for generating the clock signal.
The PLL circuit described can be made to oscillate in the phase shift mode, and the normal PLL operation can be performed.

Therefore, no matter what phase the received data is taken in, the data and the clock that are bit-phase synchronized can be output very stably and quickly with a simple structure to improve the malfunction due to noise. You will be able to do that.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. [Embodiment of Phase Immediate Shift PLL Circuit 4]: Therefore, the PLL circuit is configured as follows. That is, at the 1 / m (m> 0) of the desired frequency, the phase control signal having a pulse width that is half or less than one cycle width of the clock having the desired frequency and the phase switching signal are input.
In the LL circuit, a reset VCO, a phase frequency detection circuit, a charge pump circuit, a low-pass filter circuit, an m divider circuit, a 2-input AND circuit, and first and second half-inverting 2-input AND circuits. Composed of.

Then, the phase control signal and the phase switching signal are input to the 2-input AND circuit, and the output is reset to V
Input to the CO and input the phase control signal to the first half-inverting 2 input A
The phase switching signal is input to the non-inverting terminal of the ND circuit, the phase switching signal is input to the inverting terminal, and the divided pulse output of the m frequency dividing circuit is input to the non-inverting terminal of the second half-inverting 2-input AND circuit to switch the phase. A signal is input to the inverting terminal, and the reset VCO, the phase frequency detection circuit, the charge pump circuit, the low-pass filter circuit, and the m divider circuit constitute a multiplication PLL circuit.

Further, the reference clock input terminal of the phase frequency detection circuit inputs the output of the first half-inverted 2-input AND circuit, and the comparison target clock input terminal of the second half-inverted 2-input AND circuit. When the output is input and the phase switching signal is in the active state (high level), the phase control signal is taken into the reset VCO to shift the oscillation phase, during which phase frequency comparison is not performed and the phase switching signal is In the active state (low level), it is configured to operate as a multiplication PLL using the phase control signal as a reference clock. This PLL circuit is called a "phase immediate shift PLL circuit".

FIG. 1 is a functional block diagram of the phase immediate shift PLL circuit 4. In FIG. 1, the phase immediate shift PL
The L circuit 4 includes a reset VCO circuit 4a, a phase control circuit 4b, a phase frequency detection circuit 42, a charge pump circuit 43, a low pass filter circuit 44, and an m divider circuit 4.
And 5. The reset VCO circuit 4a is
Voltage-controlled delay 2-input NOR circuit 411, voltage-controlled delay inverting circuits 412 to 41n, voltage-controlled delay 2-input NOR circuit
Field effect transistor FET4 for controlling the circuit 411
91 and FETs 492 to 49n for controlling the voltage controlled delay inverting circuits 412 to 41n.

The principle of the reset VCO circuit 4a will be described with reference to FIG. The reset VCO circuit 4a inputs timing information (phase control signal) as shown in FIG. 3, and can directly control the oscillation phase of the VCO by the phase control signal to delay or delay the control phase. Is a VCO capable of generating an output clock having a phase corresponding to the input pulse signal in a short time of 1 to 5 cycle width of the oscillation clock.

Regarding a concrete configuration of such a reset VCO, reference is made in JP-A-5-227145, "Clock oscillator circuit and clock extraction circuit", JP-A-7-7.
4737 Publication "Clock extraction circuit and oscillation circuit", Japanese Patent Application No. 6-38580 "Clock oscillation circuit and gate circuit used for clock oscillation circuit", and their drawings, Japanese Patent Application No. 7-35669 "Clock oscillation circuit and The voltage control oscillation circuit using the same can be applied, but the circuit configuration as shown in FIG. 1 is adopted in the present embodiment.
Regarding the reset VCO circuit, Japanese Patent Application No. 7-2
It is also shown in the specification and drawings of 38637.

Therefore, the reset VCO circuit 4a shown in FIG.
Is a ring oscillator circuit, and the low-pass signal from the low-pass filter circuit 44 is fed to the FET 491.
˜49n gate terminal
The voltage control delay 2-input NOR circuit 491 and the voltage control delay inverting circuit 4 are controlled by controlling the drain currents of T491 to 49n.
It controls the propagation delay of 92 to 49n.

The clock from the voltage control delay inverting circuit 41n is applied to one input terminal of the voltage control delay 2-input NOR circuit 411, and the phase control signal from the phase control circuit 4b is applied to the other input. The reset VCO circuit 4a is oscillated in the phase shift mode by the phase control signal. The reset VCO circuit 4a outputs an oscillation clock in three phases.

That is, the first phase clock is applied from the voltage controlled delay inverting circuit 412 to the three phase clock output terminal -1,
The second phase clock (certain reference phase clock) is applied from the voltage controlled delay inverting circuit 414 to the three phase clock output terminal 0, and the third phase clock is applied from the voltage controlled delay inverting circuit 416 to the three phase clock output terminal +1. To do. The clock of the first phase from the voltage controlled delay inverting circuit 412 is adjacent to the clock of the reference phase, and the phase is advanced. Further, the clock of the third phase from the voltage controlled delay inverting circuit 416 is adjacent to the clock of the reference phase and is delayed in phase.

The m frequency dividing circuit 45 is a reset VCO circuit 4
The output clock from a is divided by a predetermined division ratio, and the divided clock is converted into a half-inverted 2-input AND circuit 4 of the phase control circuit 4b.
Give 8 In the multiplication PLL operation mode (the phase switching signal is inactive), the phase frequency detection circuit 42 takes in the m-divided clock from the m-divided circuit 25 from the half-inverted 2-input AND circuit 48 to the V terminal and The control signal is fetched from the one-sided two-input AND circuit 47 to the R terminal (reference terminal) and the phase / frequency comparison result signals U (up signal) and D (down signal) obtained by comparing the phases and frequencies are charged by the charge pump. It is given to the circuit 43.

The charge pump circuit 43 can be composed of a simple transistor circuit, and flows in / out a current proportional to the phase difference signal. That is, the charge pump circuit 23 uses the phase / frequency from the phase frequency detection circuit 42.
When the frequency comparison result signals U and D are given, the low-pass filter circuit 44 is provided with a charge pump signal obtained by charging the U signal and discharging the D signal. The low-pass filter circuit 44 generates a low-pass signal from this charge pump signal with a simple circuit including a resistor and a capacitor, and the FET of the reset VCO circuit 4a.
491 to 49n.

The phase control circuit 4b is a 2-input AND circuit 4
6 and one-sided inversion two-input AND circuits 47 and 48. The phase control circuit 4b takes in a frequency-divided clock obtained by dividing the output clock from the voltage-controlled delay inverting circuit 49n of the reset VCO circuit 4a by m into the half-inverting 2-input AND circuit 48, and outputs the phase control signal and the phase switching signal. , And when the phase switching signal is active (high level), the reset VCO circuit 4a is controlled to oscillate in the phase shift mode by the phase control signal. When the phase switching signal is inactive (low level), the phase control signal controls the phase frequency detecting circuit 42 to perform the multiplication PLL operation.

In order to realize such an operation, the phase control signal is applied from the input terminal to one input terminal of the 2-input AND circuit 46, and the other input terminal is applied with the signal from the phase switching signal input terminal. . That is, 2-input AND
The circuit 46 resets the phase control signal V when the phase switching signal is active (high level).
The voltage control delay 2 input of the CO circuit 4a is given to the NOR circuit 411, and the phase switching signal is inactive (low level).
, The low level signal is supplied to the voltage control delay 2-input NOR circuit 411 without passing the phase control signal.

The phase switching signal is sent from the input terminal
In addition to being applied to the 2-input AND circuit 46, it is also applied to the half-inverted 2-input AND circuits 47 and 48. The one-sided two-input AND circuit 47 does not pass the phase control signal when the phase switching signal is active (high level), and passes the phase control signal when the phase switching signal is inactive (low level) to detect the phase frequency detection circuit 22. To control the oscillation operation of the multiplication PLL operation mode.

Further, the one-sided 2-input AND circuit 48 is given the phase switching signal and the m-divided clock from the m-divided circuit 45, and when the phase switching signal is active (high level), the m-divided clock. When the signal is inactive (low level) without passing through, the frequency-divided clock m is passed and given to the phase frequency detection circuit 22,
It controls the oscillation operation of "multiplication PLL mode".

(Operation): Next, referring to the operation timing chart of FIG. 4, the phase immediate shift PLL circuit 4 of FIG.
Will be described. 4A shows the operation timing of the phase control signal, FIG. 4B shows the operation timing of the phase switching signal, FIG. 4C shows the operation timing of the voltage control delay inverting circuit 41n, and FIG. (D) is one-sided inversion 2
The operation timing of the input AND circuit 47 is shown in FIG.
(E) is the operation timing of the one-sided two-input AND circuit 48.

In FIG. 4, the phase immediate shift PLL circuit 4 is reset in synchronization with the pulse rising timing of the phase control signal when the phase switching signal (FIG. 4 (b)) is inactive (low level). V
The CO circuit 4a oscillates in the "multiplication PLL mode" (FIG. 4 (c)). At this time, since the phase control signal is not given to the reset VCO circuit 4a, it is not controlled to the "phase shift mode". Then, when the phase switching signal (FIG. 4 (b)) is given active (high level), this time the phase control signal is given to the voltage control delay 2-input NOR circuit 411 of the reset VCO circuit 4a,
Oscillation phase is 2 input AND circuit 4 in "Phase shift mode"
6 is forcibly controlled by the output signal (phase control signal) 6 (FIG. 4 (c)) to output the oscillation clock (FIG. 4 (c)).

Therefore, depending on the level state of the phase switching signal, the "phase shift mode" in which the phase immediate shift PLL circuit 4 is instantly forcibly controlled by the phase control signal to oscillate the phase, and the "multiplication PLL mode" in which the phase control signal is used. 』And can be switched to.

(Effect of Embodiment of Phase Immediate Shift PLL Circuit 4): According to the phase immediate shift PLL circuit 4 as described above, the "phase shift mode" and the "multiplication PLL" are provided by the newly provided phase switching signal. Mode ”. Moreover, even when such switching is performed, there is an effect that the clock can be stably output without any interruption and without noise accumulation.

Moreover, the newly added phase control circuit 4b
Since is a very simple circuit, miniaturization can also be realized. Since such an effect can be obtained, improvement in bit phase synchronization performance can be expected when applied to a bit phase synchronization circuit.

[First Embodiment of Bit-Phase Synchronization Circuit of the Present Invention]: In the first embodiment of the bit-phase synchronization circuit of the present invention, the bit-phase synchronization circuit is configured as follows. That is, the bit phase synchronization circuit basically receives the received data with an unknown phase and the reference clock having a frequency equal to or close to the bit rate of the received data, or 1 / m (m> 0). In the system, a multiplication PLL circuit that generates an n-phase multiphase clock, a toothless clock generation circuit, an n: 1 selection selector circuit, and a reset VCO that can control the phase of an output clock by a phase control signal. A phase immediate shift PLL circuit configured by using, a timing determination circuit that latches input data with an input clock and determines the timing of the input data and the input clock, and a selection control signal that is generated from the determination signal. When active, the selector control circuit that outputs a selection control signal at the timing of the input clock and the multiplication PLL circuit Phase immediate shift PL to lock
It is composed of a lock determination circuit for determining whether or not the L circuit is locked.

In the basic configuration of such a bit phase synchronizing circuit, the reference clock is further input to the multiplication PLL circuit, and the multiplication PLL circuit multiplies it to a frequency equal to or close to the bit rate of the received data, and , A means for generating a multi-phase clock and, from the multi-phase clock, with a toothless clock generation circuit, make only one of the clock pulses of k (k is an integer of 3 or more) cycles rise for each clock. The pulse generated for each phase is generated so as to fit within the two-clock cycle width of the multi-phase clock, and the pulse of the toothless clock is generated. And means for generating a switching timing signal such that an active pulse rises at an intermediate position of the pulse.

Further, means for selecting an arbitrary phase in the selector circuit from the multiphase missing clock and a clock selected and output in the selector circuit are immediately phase-shifted PLL.
Input as a circuit phase control signal and immediately shift the phase PL
In the L circuit, when the phase switching signal is in the active state, the phase control signal is taken into the reset VCO circuit to shift the phase, and when the phase switching signal is in the inactive state, the phase control signal is used as the reference clock. As means for performing the operation of the "multiplication PLL mode", the multiplication P
The LL circuit and the phase immediate shift PLL circuit are provided with means for determining whether or not they are in a locked state.

Furthermore, in the timing judgment circuit,
Received data is latched with the output clock from the phase immediate shift PLL circuit, and at that time, the latch timing is determined,
Outputs a judgment signal that indicates whether to advance, delay, or keep the phase of the clock, and the latched data,
The clock used for the latch is a means for outputting the reproduced data and the clock for the reproduced data, respectively, and the result of latch timing determination is the selector control circuit, which controls the previous selector circuit, and the protection time until the result is fed back. If it is later, as a valid judgment signal,
The selector control circuit generates a selection control signal so as to select a clock having a phase in accordance with the selection control signal. The selection control signal is multiplied when the switching timing signal input from the toothless clock generation circuit is active. PL
Output at the timing of any one of the L multiphase clocks, and when the lock determination result is determined to be the unlocked state, the selection control signal is fixed and the selector circuit is controlled. Then, when the selection control signal changes, the phase switching signal includes means for outputting an active pulse having a fixed width at the timing of the switching timing signal.

FIG. 5 is a functional block diagram of the bit phase synchronizing circuit. In FIG. 5, the bit phase synchronization circuit includes a multiplication PLL circuit 2, a selector circuit 3, and a phase immediate shift P.
It is composed of an LL circuit 4, a timing determination circuit 5, a selector control circuit 6, a toothless clock generation circuit 11, and a lock determination circuit 16.

The multiplication PLL circuit 2 takes in the clock from the reference clock input terminal 1 to the reference clock input terminal. This reference clock is 1 / m (m> 0) of the same frequency as the bit rate of received data. The multiplication PLL circuit 2 generates a clock having the same frequency as the bit rate of received data. Moreover, the multiplication PLL circuit 2 uses a VCO capable of generating a multi-phase clock such as a ring oscillator or a multivibrator, and divides one clock width of the multiplication clock into n equal parts (n is an integer of 3 or more) to provide a multiphase phase difference. The clock is output from the multi-phase clock output terminals (1 to n). Regarding the phase relationship of the multi-phase clock, it is assumed that the multi-phase clock 1 is the head of the phase and the phase is delayed as the argument increases.

The missing clock generating circuit 11 has a multiplication P
Given the multiphase clocks 1 to n from the LL circuit 2,
A pulse generated for each phase, which is a so-called toothless clock in which only one of k (k is an integer of 3 or more) clock pulses is made to stand for each clock. Is generated so that it fits within the two-clock cycle width of the multiphase clock. Further, the switching timing signal is generated so that the active pulse is set at an intermediate position between the pulses of the toothless clock. Then, the multiphase missing clocks 1 to n are applied to the selected signal input terminals 1 to n of the selector circuit 3, respectively, and the switching timing signal is applied to the switching timing signal input terminal of the selector control circuit 6.

The selector control circuit 6 fetches the switching timing signal from the toothless clock generation circuit 11 into the switching timing signal input terminal, and the multiplication PLL circuit 2
The clock from the multi-phase clock output terminal 1 is loaded into the clock input terminal, the lock determination result signal from the lock determination circuit 16 is loaded into the lock determination result signal input terminal,
The timing judgment result signal is fetched from the timing judgment circuit 5 to the timing judgment result signal input terminal, the selection control signal is generated and output from the selection control signal output terminal and given to the selector circuit 3, and the phase switching timing signal is generated. When the timing error occurs, the received data identification error signal is output from the timing error output terminal to the received data identification error output terminal 10.

The selector circuit 3 takes in the multiphase missing clocks 1 to n from the missing clock generating circuit 11 into the selected signal input terminals 1 to n, and outputs the multiphase missing clocks 1 to n. Any one of the multiphase missing clocks is selectively output based on the selection control signal given from the selector control circuit 6 and given to the phase control signal input terminal of the phase immediate shift PLL circuit 4.

As described above, the phase immediate shift PLL circuit 4 takes in the toothless clock selected and output from the selector circuit 3 into the phase control signal input terminal, and phase-shifts the phase switching signal supplied from the selector control circuit 6. Operates in the "phase shift mode" in which the oscillation phase of the internal reset VCO is forcibly controlled by the phase of the pulse of the phase control signal while the phase control signal is active (high level) To do.

While the phase switching signal is inactive (low level), the phase control signal is used as an input clock to operate in the "multiplication PLL mode". By operating in any of these modes, the obtained oscillation clock is output as a three-phase clock. That is, the clock 0 of a certain reference phase is adjacent to the clock of this reference phase,
In addition, the clock −1 whose phase is advanced and the clock +1 which is adjacent to the clock of the reference phase and whose phase is delayed are output to output the three-phase clock input terminals -1, 0, +1 of the timing determination circuit 5. Give to.

The lock determination circuit 16 is the multiplication PLL circuit 2
It is determined whether the phase immediate shift PLL circuit 4 is in the locked state from the oscillation clock (master clock) of 1) and the oscillation clock of the phase immediate shift PLL circuit 4 (slave clock). If it is determined by this determination that the lock state is set, an active (high level) signal is output as the lock determination result signal, and if it is determined that the lock state is not set,
Inactive as lock determination result signal (low level)
A signal is output and given to the lock determination result signal input terminal of the selector control circuit 6.

The timing judgment circuit 5 fetches the three-phase clock from the phase immediate shift PLL circuit 4 into the three-phase clock input terminals -1, 0, +1 and the received data from the received data input terminal 7 to the data input terminal. If it is appropriate for the phase relationship between the fetched and input three-phase clock 0 and the received data, it is determined as it is, and if it is inappropriate, it is determined whether the clock phase should be advanced or delayed, and the result is determined. Is output from the timing determination result signal output terminal and applied to the timing determination result signal input terminal of the selector control circuit 6. Further, the timing judgment circuit 5 latches the received data at the three-phase clock 0, outputs the latch output from the data output terminal and applies it to the reproduction data output terminal 8, and also the three-phase clock 0 used for this latch. Bits are applied to the reproduction data clock output terminal 9.

(Operation): Next, the operation of the above-described bit phase synchronizing circuit of FIG. 5 will be described with reference to the operation timing charts of FIGS. 6 and 7, (a) is the operation timing of the reference clock, and (b1) to (b)
5) is the operation timing of the multi-phase clock of the multiplication PLL circuit 2, (c1) to (c5) is the operation timing of the multi-phase missing clock of the tooth loss clock generation circuit 11, and (d) is the tooth It is the operation timing of the switching timing signal of the missing clock generation circuit 11, (e) is the operation timing of the selection control signal of the selector circuit 3,
(F) is the operation timing of the output signal of the selector circuit 3, (g) is the operation timing of the 3-phase clock-1 of the phase immediate shift PLL circuit 4, and (h) is 3 of the phase immediate shift PLL circuit 4. It is the operation timing of the phase clock 0, (i) is the operation timing of the three-phase clock + 1 of the phase immediate shift PLL circuit 4, (j) is the operation timing of the received data, and (k) is the operation of the reproduced data. Is the timing, and (l) is the first of the timing determination circuit 5.
(M) is the operation timing of the second determination result signal of the timing determination circuit 5, and (n) is the operation timing of the phase switching signal of the selector control circuit 6.

In the operations of FIGS. 6 and 7, the frequency division ratio is m = 4, the number of phases of the multi-phase clock is n = 5, and the tooth-missing cycle of the tooth-missing clock is k = 4.

First, at the reference clock input terminal 1, for example, 1 / m of the same frequency as the bit rate of the received data.
When the reference clock (a) of (m> 0) is applied, it is given to the reference clock input terminal of the multiplication PLL circuit 2. In this multiplication PLL circuit 2, a clock having the same frequency as the bit rate of received data is generated. In this multiplication PLL circuit 2, a VCO capable of generating a multiphase clock such as a ring oscillator or a multivibrator is used, and a multiphase clock having a phase difference obtained by dividing one clock width of the multiplication clock into n equal parts (n is an integer of 3 or more). (B1) to (b5) are multiplied PLL
The signals are output from the multiphase clock output terminals 1 to n of the circuit 2, respectively.

Multiphase clocks 1 to n of the multiplication PLL circuit 2
Is input to the multiphase clock input terminals 1 to n of the toothless clock generation circuit 11, and the multiphase clock 1 of the multiplication PLL circuit 2 is input to the clock input terminal of the selector control circuit 6. In the toothless clock generation circuit 11, for each clock of the input multiphase clocks 1 to n, k (k
Generates a so-called toothless clock (c1) to (c5) in which only one of the clock pulses of an integer of 3 or more) stands, and the pulse generated for each phase is It is generated so as to fit within the two-clock cycle width of the multiphase clock. Further, the switching timing signal is generated so that an active pulse is set at an intermediate position between the pulses of the toothless clock.

The multiphase missing clocks 1 to n of the missing clock generating circuit 11 are input to the selected signal input terminals 1 to n of the selector circuit 3, respectively. In the selector circuit 3, one of the signals input to the selected signal input terminals 1 to n is output from the signal output terminal according to the selection control signal (e).
Is input to the phase control signal input terminal.

The phase immediate shift PLL circuit 4 has two modes depending on the phase switching signal (n).
When the phase switching signal is in the active state, it operates in the "phase shift mode", and when it is inactive, it operates in the "multiplication PLL mode". In the "phase shift mode", while the phase switching signal (n) is in the active state, the reset VC which constitutes the phase immediate shift PLL circuit 4 is configured by the phase of the pulse of the signal input from the phase control signal input terminal.
The oscillation phase of O is forcibly controlled, and a pulse signal having an n-phase phase is selectively input to generate a clock of an n-phase oscillation phase corresponding to each.

In the "multiplication PLL mode", while the phase switching signal is inactive, the multiplication PLL operation is performed using the pulse of the signal input from the phase control signal input terminal as the reference clock. This phase immediate shift PLL
In the circuit 4, a clock having a certain reference phase, a clock adjoining the reference clock, a clock advancing in phase, a clock adjoining the reference clock, and a clock lagging in phase are respectively provided in three phases. Clock 0 (h),-
Output as 1 (g) and +1 (i). The three-phase clocks -1, 0, +1 of the phase immediate shift PLL circuit 4 are respectively the three-phase clock input terminals -1, -1, of the timing judgment circuit 5.
It is input to 0 and +1.

The received data input terminal 7 receives data of unknown phase transmitted from the opposite device,
The data (j) is input to the data input terminal of the timing determination circuit 5. In the timing judgment circuit 5, if the phase relationship between the input three-phase clock 0 (h) and the data is appropriate, if it is not appropriate, if it is not appropriate, the clock phase should be advanced or delayed. Is determined and the results (1) and (m) are output from the timing determination result signal output terminal.

Further, the timing judgment circuit 5 latches the input data (j) at the three-phase clock 0 (h), outputs the latch output from the data output terminal (k), and reproduces the output. Output from the data output terminal 8,
The clock used to latch the input data is output from the clock output terminal, and the output is output from the reproduction data clock output terminal 9.

The timing judgment result signals (l) and (m) of the timing judgment circuit 5 are input to the timing judgment result signal input terminal of the selector control circuit 6. In the selector control circuit 6, since the selection control signal (e) of the selector circuit 3 was changed last time, the protection for being accurately reflected in the determination result signals (l) and (m) of the timing determination circuit 5 A control signal (e) is output from the selection control signal output terminal of the selector control circuit 6 in response to the determination result signal input after a certain time.

Here, the protection time in the selector control circuit 6 needs to be longer than the feedback time of the path of the selector control circuit 6 → selector circuit 3 → phase immediate shift PLL circuit 4 → timing determination circuit 5 → selector control circuit 6. Become. The selection control signal (e) is latched by the multi-phase clock 1 before the output from the selection control signal output terminal, and the latch outputs the new selection control signal (e) when the switching timing signal is active. Capture,
When the switching timing signal is inactive, the latch value is retained.

That is, the selector circuit 3 is controlled in the area where the switching timing signal (d) is active,
At that timing, the input of the selected signals 1 to n of the selector circuit 3 is stable at a value that is an inactive signal as the phase control signal of the phase immediate shift PLL circuit 4. Therefore, at the time of switching, noise is not input to the phase control signal input terminal of the phase immediate shift PLL circuit 4.

The phase switching signal (n) outputs an active signal indicating the state of switching at the same time as the selection control signal (e) changes, and an inactive signal is generated by the switching timing signal (d) that follows. Output. Here, the phase immediate shift PLL circuit 4 deactivates the phase switching signal (n) by the switching timing signal immediately after, because the phase control is terminated by the single-shot pulse of the phase control signal (f). In the case of the phase immediate shift PLL circuit 4 that requires a plurality of pulses, the phase switching signal is deactivated by the switching timing signal (d) after that number.

Further, in the selector control circuit 6, when the judgment result signal within the protection time includes both the information for advancing the phase of the phase immediate shift PLL circuit 4 and the information for delaying the phase, the received data has noise. It has been determined that the product has been accumulated, the input value has become an indefinite value due to input line disconnection, or the output clock of the phase immediate shift PLL circuit 4 has caused a tracking error with respect to the received data, and the timing error output terminal Outputs a timing error signal from the received data identification error output terminal 10.

Further, in the selector control circuit 6, when the lock determination result signal of the lock determination circuit 16 is inactive indicating the unlocked state, the phase immediate shift PLL is performed.
In order not to disturb the lock-in operation of the circuit 4, the value of the selection control signal is not changed regardless of the value of the timing determination result signal.

In the lock determination circuit 16, the multi-phase clock 1 of the multiplication PLL circuit 2 is used as a master clock, the three-phase clock 0 of the phase immediate shift PLL circuit 4 is used as a slave clock, and the phase immediate shift PLL circuit 4 is in a locked state. Whether or not it is determined that the active signal is output when the lock state is determined, and the inactive signal is output when the unlock state is determined.

(Detailed Configuration of Multiplication PLL Circuit 2): FIG. 8 is a detailed functional configuration diagram of an example of the multiplication PLL circuit 2 used in FIG. 5 described above. In FIG. 8, the multiplication P
The LL circuit 2 includes voltage controlled delay inverting circuits 211 to 21n, field effect transistor FETs 251 to 25n, and a phase frequency detection circuit 22 that form a ring oscillator.
, Charge pump circuit 23, and low-pass filter 24
And m frequency dividing circuit 25.

The phase frequency detection circuit 22 receives the reference clock, compares the phase frequency with the m-divided clock from the m-divided circuit 25, and outputs the phase frequency comparison result signals U and D obtained by the charge pump circuit 23. Give to. The charge pump circuit 23 can be configured by a simple transistor circuit, and flows in / out a current proportional to the phase difference signal. That is, the charge pump circuit 23 is operated by charging the U signal and discharging it by the D signal when the phase / frequency comparison result signals U and D from the phase frequency detection circuit 42 are given. To the low-pass filter circuit 24. The low-pass filter circuit 24 generates a low-pass signal of this charge pump signal by a simple circuit including a resistor and a capacitor and gives it to the FETs 251 to 25n of the VCO circuit.

The voltage controlled delay inverting circuits 211 to 21n and the FETs 251 to 25 of the VCO circuit shown by the dotted line in FIG.
When n receives a signal after passing the low band from the low-pass filter 24, it oscillates and forms an n-phase clock and outputs it to the multi-phase clock output terminal.
Return to the frequency dividing circuit 25. That is, the voltage control delay inverting circuit 21
The output signals of 1 to 21n are output to the multiphase clock output terminals 1 to n, and the output signal of the voltage controlled delay inverting circuit 21n is given to the m frequency dividing circuit 25. The m frequency dividing circuit 25 frequency-divides the output signal of the voltage controlled delay inverting circuit 21n by m (m is a real number of 1 or more) and supplies it to the phase frequency detecting circuit 22. With such a configuration, a multi-phase clock can be generated using the reference clock as an input signal.

(Detailed Configuration of Toothless Clock Generation Circuit 11) FIG. 9 is a detailed functional configuration diagram of the toothless clock generation circuit 11. In FIG. 9, the toothless clock generation circuit 11 is composed of toothless clock generation units 111 to 11n for each of the input multiphase clock signals, and is realized by the same circuit configuration. To describe the internal configuration as a representative, the toothless clock generation unit 111 includes a binary counter 1111, a single-inversion 2-input AND circuit 1112, and a 2-input NOR circuit 1113.
And a 2-input AND circuit 1114 and a D flip-flop circuit 1115.

The binary counter 1111 operates with a clock having a phase opposite to that of the multi-phase clock 1 and a 2-input NOR signal that outputs a high level signal only once every four clocks from the counter value.
A two-input AND circuit 1114 performs a logical product operation of the signal generated by the circuit 1113 and the multiphase clock 1 to generate a toothless clock. In addition, a signal in which a high level is set once in four clocks from the counter value and a high level is set in the middle of the missing clock is one-sided inversion 2 input A
It is output by the ND circuit 1112 and is generated as a switching timing signal. This switching timing signal uses only the output of the toothless clock generation unit 111.

The chained reset input signal of the toothless clock generation unit 111 is input as a load signal of the binary counter 1111. In this binary counter 1111, the arrangement of the toothless clock generation unit and k (an integer of 2 or more is used). , The number of tooth loss cycles) is loaded. In addition, the chain reset input signal is the multiphase clock 1
It is latched and output by the D flip-flop circuit 1115 which operates in the opposite phase of, and is output as a chain reset output signal. This chain reset output signal starts from the toothless clock generation unit 11n, is output from the toothless clock generation unit, and then processes the adjacent phase-advanced multiphase clocks. Is input as a chain reset input signal of
1 closes the chain.

Here, how to determine the load value to the binary counter 1111 will be described. Missing clock generator 1
1n is used as the start-up missing clock generator for the reset chain, and when the value of the binary counter 1111 of the missing clock generator 11n is 0, a code 0 signal is output, and the signal is the missing clock generator 11. (N-1) chain reset input signal n-1 is input, and the binary counter 1111 of the toothless clock generation unit 11 (n-1) is input.
Then, the value of the value of the binary counter 1111 of the preceding missing clock generating unit 11n, which is the missing clock generating unit, is 1
Is set as the load value, which is an incremented value of 1, and is loaded by the chain reset input signal n-1.

Similarly, a value obtained by incrementing 1 to the value loaded by the previous clock-missing clock generation unit is set as a load value. When the load value becomes equal to k-1, The clock generation unit returns the load value to 0 and increases the load value by 1 again. With this configuration, the positions of all the pulses of the tooth-missing clock can be set within the two-clock cycle width.

(Detailed structure of the timing judgment circuit 5):
FIG. 10 is a detailed configuration diagram of the timing determination circuit 5.
10, the timing determination circuit 5 includes D flip-flop circuits 511 to 513, 516, and 517,
It is composed of exclusive OR circuits 514 and 515.

Received data is supplied to the data input terminals D of the D flip-flop circuits 511 to 513, the three-phase clock-1 is supplied to the clock input terminal C of the D flip-flop circuit 511, and the D flip-flop circuit 512 is supplied.
3 phase clock 0 is given to the clock input terminal C of
The 3-phase clock + 1 is applied to the clock input terminal C of the D flip-flop circuit 513. The D flip-flop circuit 511 outputs a latch output signal for the received data from the data output terminal Q and supplies it to the exclusive OR circuit 515.

The D flip-flop circuit 512 outputs a latch output signal for the received data from the data output terminal Q, supplies it to the exclusive OR circuits 515 and 514, and outputs it to the data output terminal. The D flip-flop circuit 513 outputs a latch output signal for the received data from the data output terminal Q and supplies it to the exclusive OR circuit 514. The exclusive OR circuit 514 performs an exclusive OR operation from the latch output signal from the D flip-flop circuit 512 and the latch output signal from the D flip-flop circuit 513, and the operation result is the D flip-flop circuit 516. Data input terminal D.

The three-phase clock -1 is applied to the clock input terminal C of the D flip-flop circuit 516, and the exclusive OR operation result is latched and output by this clock, and the latch output signal (advance the phase). Signal) to the determination result signal output terminal 1.

On the other hand, the exclusive OR circuit 515 performs an exclusive OR operation on the latch output signal of the D flip-flop circuit 511 and the latch output signal from the D flip-flop circuit 512, and the operation result is D It is applied to the data input terminal D of the flip-flop circuit 517. The clock input terminal C of the D flip-flop circuit 517 has 3
The phase clock -1 is given, and the exclusive OR operation result is latched and output by this clock, and this latch output signal (signal for delaying the phase) is output to the determination result signal output terminal 2.

With this configuration, the timing judgment circuit 5 takes in the received data whose phase is unknown and
If the three-phase clocks -1, 0, +1 from the reset VCO 4 are fetched and the phase relationship between the input three-phase clock 0 and the data is appropriate, the phase is changed as it is, or if it is inappropriate, the clock phase is changed. It judges whether to proceed or to delay, and outputs the result as a judgment result signal. Also, the timing determination circuit 5
Is for latching the input reception data at the three-phase clock 0, outputting the latch output from the data output terminal, and at the same time outputting the three-phase clock 0 used for latching the input reception data.

(Detailed Structure of Lock Determination Circuit 16):
FIG. 11 is a detailed functional block diagram of the lock determination circuit 16. In FIG. 11, the lock determination circuit 16 includes binary counters 161 to 163, a D flip-flop circuit 164, a JK flip-flop circuit 165, a 2-input NAND circuit 166, and a half-inverted 2-input AND circuit 167.
And OR circuits 168 and 169, and a NOT circuit 170.

In the lock determination circuit 16, the binary counters 161 and 163 and the D flip-flop circuit 16 are provided.
4 and the JK flip-flop circuit 165 operate with a master clock, and the binary counter 162 operates with a slave clock. Binary counter 16
At 1, the counter value is N (N is an arbitrary natural number) and N +
At 2, N + 4, active pulses are output, and from these pulses, a JK flip-flop circuit 165 is used to generate a pulse having a width of 4 clocks, whereby the binary counter 162 is disabled.

The counter value of the binary counter 161 is N
In the case of +2, the counter value of the binary counter 162 is monitored, and if the value is N or N + 1, the binary counter 163 is counted up, and if not, the counter value is reset to 0. Further, the binary counter 163 is provided to protect the M stages (M is an integer of 2 or more) so that the lock state is not mistakenly determined.
When the counter value reaches M, self-disable is applied and a low level signal indicating a locked state is output as a lock determination result signal.

(Detailed configuration of selector control circuit 6):
FIG. 12 is a detailed configuration diagram of the selector control circuit 6. In FIG. 12, the selector control circuit 6 includes D flip-flop circuits 61, 62, 66 to 69, 610, D flip-flop circuits with selectors 621 to 62n, 2-input AND circuits 63 to 65, 618, and one-sided inversion. 2-input AN
D circuits 611 and 612, an OR circuit 613, an up / down counter 614, a binary counter 615, and J
K flip-flop 616 and 2-input NOR circuit 617
, OR circuits 631 and 636, and D flip-flop 6
32, AND circuits 633 and 634, a one-sided AND circuit 635, and a JK flip-flop 637.

In particular, OR circuits 631 and 636, D flip-flop 632, AND circuits 633 and 634, one-sided AND circuit 635, and JK flip-flop 637.
The circuit consisting of and is a circuit for generating a phase switching signal for the phase immediate shift PLL circuit 4.

First, a signal for advancing the phase and a signal for delaying the phase are input as the clocks of the D flip-flop circuits 61 and 62, respectively, as the determination result signal. When the rising edge of the clock is input, the D flip-flop circuits 61 and 62 latch and output the high level output, and these latch output signals are output to the binary counter 61.
If it is other than the protection time determined by 5, it is latched by the D flip-flop circuits 67 and 68, respectively.

D flip-flop circuits 67 to 69, 61
A circuit composed of 0 and half-inverted 2-input AND circuits 611 and 612 detects the rising edge of the determination result signal and outputs a pulse having a width of 1 clock. The pulse generated by detecting the rising edge of the signal for advancing the phase in the detection circuit is given to the down input of the amplifier down counter 614. The pulse generated by detecting the rising edge of the signal that delays the phase in the detection circuit is given to the up input of the up / down counter 614. When the down signal is input, the amplifier down counter 614 counts down in the order of 3 → 2 → 1 → n → (n−1) in order to select the clock whose phase is ahead of the currently selected clock.

On the contrary, when the up signal is inputted, the clock is incremented in the order of (n-1) → n → 1 → 2 → 3 in order to select the clock whose phase is delayed from the currently selected clock. The output of the up / down counter 614 is decoded and prepared in the same number as the number of phases of the multi-phase clock. When the switching timing signal is at the high level, each output is provided with the D flip-flop circuits with selectors 621 to 62.
At n, it is latched out by the input clock. D with selector when switching timing signal is low level
The flip-flop circuits 621 to 62n hold their own data.

On the other hand, by the pulse that detects the rising edge of any of the determination result signals. Binary counter 615
Is cleared, a carry signal is output after a few counts,
The inputs of the D flip-flop circuits 67 and 68 are fixed at a low level with the rising detection pulse of the determination result signal to the carry signal as the protection time, and the D flip-flop circuit is output by the AND operation result output signal of the carry signal and the protection pulse. Complete 61 and 62.

The binary counter 615 is self-disabled by the carry signal. Further, when both the signal for advancing the phase and the signal for delaying the phase are input within the protection time, they are latched by the D flip-flop circuit 66 and then output as the timing error signal.

Further, the D flip-flop 63 is activated by the pulse that detects the rising edge of any of the determination result signals.
A high level signal is set to 2. A high-level signal is set in the JK flip-flop 637 by the switching timing signal input after that state, and the high-level signal in the active state is output as the phase switching signal.

A low level signal is set in the JK flip-flop 637 by the next switching timing signal, and the low level signal in the inactive state is output as the phase switching signal. Further, when the high level signal indicating the unlocked state is input to the lock determination result signal, the amplifier down counter 614 is disabled so as not to disturb the lock-in process of the phase immediate shift PLL circuit 4, Therefore, selector circuit 3
Is fixed and a low level signal is output as a phase switching signal.

(Effects of the first embodiment of the present invention):
According to the embodiments of the present invention described above, the reset VCO
The phase immediate shift PLL circuit 4 is configured by using
The multi-phase clock of the LL circuit 2 is converted into the multi-phase missing clock, and the multi-phase missing clock is immediately phase-shifted PL.
Selective input to the L circuit 4, and the phase immediate shift PLL circuit 4 fetches the phase control signal into the reset VCO circuit when shifting the phase and performs the phase shift, and when not shifting the phase, the phase control signal The phase immediate shift PL can be performed by operating in the multiplication PLL mode using the phase control signal as the reference clock without taking the reset VCO circuit into the reset VCO circuit.
The clock output of the L circuit 4 can always be stabilized.

Using the adjacent three-phase clocks among the clock outputs of the stable phase immediate shift PLL circuit 4,
If the timing of the received data is determined and if the timing is not appropriate, it is considered appropriate among the multi-phase clocks so that the output clock of the phase immediate shift PLL circuit 4 shifts in the phase direction determined to be appropriate. The selector circuit 3 selects and inputs one of the phase-missing clocks, which is used as the phase-missing clock, so that switching can be performed without noise, and the phase immediate shift PLL circuit 4 is used.
Has a very fast response speed of 1 to 5 clock cycle width, and can output the clock of the new phase without interruption and without the accumulation of noise. Therefore, even if the received data is burst data, the bit phase can be changed quickly. Synchronization can be established.

Further, even when the received data includes a jitter wander, it is possible to quickly follow the same. Moreover, for stable reception data, once the bit phase synchronization is completed, the phase immediate shift PLL circuit 4
Outputs a stable clock equivalent to that of the multiplication PLL circuit 2, so that the homo-code continuity tolerance of data can be made almost infinite. In addition, it is possible to easily detect the failure of the received data or the failure of the immediate phase shift PLL circuit 4.

From the above, by applying the present invention to an apparatus for reproducing digital data from received data, an apparatus having extremely high performance can be easily realized at low cost.

[Second Embodiment of Bit Phase Synchronous Circuit]: The bit phase synchronous circuit of the second embodiment achieves bit phase synchronization with parallel received data composed of a plurality of received data of the same bit rate. belongs to.

FIG. 13 is a functional block diagram of the bit phase synchronizing circuit of the second embodiment. In FIG. 13, the bit phase synchronization circuit includes a multiplication PLL circuit 2, a selector circuit 3, a phase immediate shift PLL circuit 4, a selector control circuit 6, data latch circuits 14-2 to 14-i, and timing determination. Circuit 5 and missing clock generation circuit 11
And a lock determination circuit 16. Since the same functional components as those of the first embodiment described above are designated by the same reference numerals, the description of the same components will be omitted. This bit phase synchronization circuit uses parallel data 7i ...
72 to 71 are fetched, and while the timing judgment circuit 5 performs the timing judgment on the data 71 of the parallel data, the reproduced data 8i to 82 to 81 synchronized with the bit phase are output.

The data latch circuit 14-i fetches the received data 7i, outputs the reproduced data 8i in synchronization with the bit phase by the three-phase clock from the reset VCO circuit 4. Similarly, the data latch circuit 14-2 also takes in the received data 72 and outputs the reproduced data 82 in synchronization with the bit phase by the three-phase clock from the phase immediate shift PLL circuit 4. The timing judgment circuit 5 takes in the received data 71, outputs the reproduction data 81, the reproduction data clock, and the judgment result signal in synchronization with the bit phase by the three-phase clock from the phase immediate shift PLL circuit 4, The judgment result signal is applied to the judgment result signal input terminal of the selector control circuit 6.

(Operation): Next, the operation of the bit phase synchronizing circuit of FIG. 13 will be described. The i-parallel parallel data whose phase is unknown is input to the parallel data 71 to 7i (provided that the mutual phase relationships in the parallel data are synchronized and the phases are aligned with each other). Among them, the parallel data input signal 71 is master data as a representative of the timing information of the parallel data input, and the other data is slave data, and the parallel data input signal 71 is input to the data input terminal of the timing determination circuit 5. , Parallel data input signal 72-
7i are data latch circuits 14-2 to 14-i, respectively.
Is input to the data input terminal.

In the timing judgment circuit 5, the input 3
If the phase relationship between the phase clock 0 and the data is appropriate, it is determined as it is, if it is inappropriate, it is determined whether the phase of the clock should be advanced or delayed, and the result is determined as a determination result signal. Output from the output terminal.

The timing judgment circuit 5 and the data latch circuits 14-2 to 14-i latch the input data by the input three-phase clock 0,
The latch output signals are output as reproduction parallel data output signals 81 to 8i from the respective data output terminals.

In the timing judgment circuit 5, the clock used for latching the input data is output from the clock output terminal, and the output is output as the reproduction parallel data clock 9. The determination result signal of the timing determination circuit 5 is input to the determination result signal input terminal of the selector control circuit 6.

(Effect of Second Embodiment of Bit Phase Synchronization Circuit): According to the bit phase synchronization circuit of the second embodiment described above, one of the parallel data inputs is used as a representative of the timing information. , Master data, other data as slave data, the timing judgment circuit 5 determines the timing of the master data, and the timing recovery is performed from the master data, and the phase immediate shift P
By using the output of the LL circuit 4 to latch slave data as well as master data, the effect of bit phase synchronization on serial data can be applied to parallel data without adding significant hardware.

[Third Embodiment of Bit Phase Synchronous Circuit]: The bit phase synchronous circuit of the third embodiment is for achieving bit phase synchronization with respect to parallel received data. Bit phase synchronization is performed for each of the data by timing determination.

FIG. 14 is a functional block diagram of the bit phase synchronizing circuit of the third embodiment. In FIG. 14, the bit phase synchronization circuit includes a multiplication PLL circuit 2, a selector circuit 3, a phase immediate shift PLL circuit 4, a selector control circuit 6, timing determination circuits 51 to 5i, and a toothless clock generation circuit. 11, a determination result OR circuit 15, and a lock determination circuit 16.

The timing judgment circuit 51 uses the received data 7
1 and outputs the reproduction parallel data, the reproduction parallel data clock, and the judgment result signal in synchronization with the bit phase using the three-phase clock from the phase immediate shift PLL circuit 4, and the judgment result signal is the judgment result. OR circuit 1
5 given. The timing judgment circuit 5i fetches the received data 7i, outputs the reproduction parallel data and the judgment result signal by bit phase synchronization using the three-phase clock from the phase immediate shift PLL circuit 4, and the judgment result signal is The determination result is given to the OR circuit 15. Judgment result O
The R circuit 15 performs a logical sum operation of the decision result signals from the timing decision circuits 51 to 5i and gives the operation result signal to the decision result signal input terminal of the selector control circuit 6.

(Operation): Next, the operation of the bit phase synchronizing circuit of FIG. 14 will be described. The reception parallel data input terminals 71 to 7i receive i parallel reception parallel data whose phase is unknown (however, it is assumed that the mutual phase relations in the reception parallel data are synchronized and the phases are almost uniform. .) And the parallel data thereof are input to the data input terminals of the timing determination circuits 51 to 5i, respectively.

In each of the timing judgment circuits 51 to 5i, the phase relationship between the clock and the data input individually is
If it is appropriate, it is determined as it is, and if it is inappropriate, it is determined whether the clock phase should be advanced or delayed, and the result is output from the determination result signal output terminal.

In the timing judgment circuits 51 to 5i, each input data is latched by the input three-phase clock 0, the latch output is output from the data output terminal, and the output is the reproduction parallel data output signal. 81 to 8i, and the timing determination circuit 51 is output.
Outputs the clock used for latching the input data from the clock output terminal, and the output is output as the clock for reproduced parallel data.

The determination result signals of the timing determination circuits 51 to 5i are input to the determination result signal input of the determination result OR circuit 15, respectively. In the decision result OR circuit 15, all the inputted decision result signals are ORed and the result is outputted from the decision result signal output terminal. This signal is inputted to the decision result signal input terminal of the selector control circuit 6. Given.

(Effects of the Third Embodiment): According to the bit phase synchronization circuit of the third embodiment described above, it is possible to perform bit phase synchronization for all bit lines of received parallel data. Therefore, even for the reception parallel data having the phase skew (phase shift), the effect for the serial data in the first embodiment to the second embodiment described above is obtained, and large hardware is added. It can be applied without doing.

(Other Embodiments) (1) A clock having a frequency of 1 / m (m> 0) of the same clock frequency as the bit rate of received data is input to the reference clock input terminal. However, it is clear that the frequencies may be close to each other.

(2) Further, the VCO of the multiplication PLL circuit and
A VCO having the same circuit configuration as the VCO of the reset VCO circuit
However, different circuit configurations may be used.

(3) Further, in explaining the operation, the operation was explained at the active high level, but any polarity can be applied as long as the polarities of the signals are logically consistent.

[0110]

As described above, the invention of claim 1 is a PLL circuit which comprises a reset VCO circuit and a phase comparison control circuit, and which performs an PLL operation by giving an input phase control signal to the phase comparison control circuit. When the phase switching signal input terminal for applying the phase switching signal and the phase switching signal applied to the phase switching signal input terminal are in a predetermined state, the phase control signal is given to the reset VCO circuit to reset the reset VCO circuit. Oscillation control in the phase shift mode, and when the phase switching signal applied to the phase switching signal input terminal is in a state other than the predetermined state, the phase comparison signal is controlled by the phase comparison control. By providing the circuit with a phase control means for controlling to perform the PLL operation, it is possible to realize a function which is not available in the past. Moreover PLL which can be expected the effect of performance improvement when applied to the bit phase synchronizing circuit
A circuit can be realized.

The invention according to claim 2 comprises the PLL circuit according to claim 1, wherein the clock selected and output by the selecting means is taken in as a phase control signal and a phase switching signal is taken in. It is determined whether or not the PLL circuit of the clock generation means is in the locked state based on the clock generation means for generating the first clock, the clock generated by the n-phase clock generation means, and the first clock, and the clock is locked. The timing determination output means generates the phase switching signal from the switching timing signal, the lock determination result signal, and the phase difference signal, and supplies the phase determination signal to the PLL circuit of the clock generation means. By giving it, no matter what phase the received data is taken in, it is very stable, and with a simple configuration, it can be quickly bited. And outputs a phase synchronized data and clock, it is possible to realize a bit phase synchronization circuit for improving the malfunction to noise.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram of an embodiment of a phase immediate shift PLL circuit of the present invention.

FIG. 2 is a configuration diagram of a conventional bit phase synchronization circuit.

FIG. 3 is an explanatory diagram of a reset VCO according to an embodiment of a phase immediate shift PLL circuit.

FIG. 4 is an operation timing chart of the embodiment of the phase immediate shift PLL circuit.

FIG. 5 is a functional configuration diagram of the first embodiment of a bit phase synchronization circuit.

FIG. 6 is an operation timing chart (1/2) of the first embodiment of the bit phase synchronization circuit.

FIG. 7 is an operation timing chart (2/2) of the first embodiment of the bit phase synchronization circuit.

FIG. 8 is a functional configuration diagram of the multiplication PLL circuit of the first embodiment of the bit phase synchronization circuit.

FIG. 9 is a functional configuration diagram of the toothless clock generation circuit of the first embodiment of the bit phase synchronization circuit.

FIG. 10 is a functional configuration diagram of the timing determination circuit of the first embodiment of the bit phase synchronization circuit.

FIG. 11 is a functional configuration diagram of a lock determination circuit of the first embodiment of the bit phase synchronization circuit.

FIG. 12 is a functional configuration diagram of a selector control circuit of the first embodiment of the bit phase synchronization circuit.

FIG. 13 is a functional configuration diagram of a second embodiment of a bit phase synchronization circuit.

FIG. 14 is a functional configuration diagram of a third embodiment of a bit phase synchronization circuit.

[Explanation of symbols]

1 ... Reference clock input terminal, 2 ... Multiplication PLL circuit, 3 ...
Selector control circuit, 4 ... Phase immediate shift PLL circuit, 4
a: reset VCO circuit, 5: timing determination circuit, 6
... selector control circuit, 7 ... received data input terminal, 8 ... reproduction data output terminal, 9 ... reproduction data clock output terminal, 10 ... reception data identification error output terminal, 11 ... missing clock generation circuit, 42 ... phase frequency Detection circuit, 4
3 ... Charge pump circuit, 44 ... Low pass filter circuit, 45 ... m frequency dividing circuit, 46 ... Phase control circuit.

Continued Front Page (72) Inventor Shuichi Matsumoto 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (5)

[Claims] 1. A phase switching signal input terminal for applying a phase switching signal, comprising a reset VCO circuit and a phase comparison control circuit, and applying an input phase control signal to the phase comparison control circuit to perform a PLL operation. When the phase switching signal applied to the phase switching signal input terminal is in a predetermined state, the phase control signal is applied to the reset VCO circuit to control only the reset VCO circuit for oscillation, and the oscillation operation is performed in the phase shift mode. When the phase switching signal applied to the phase switching signal input terminal is in a state other than the predetermined state, the phase control signal is given to the phase comparison control circuit to perform the PLL operation. A PLL circuit comprising: a phase control means for performing the phase control. 2. A bit phase synchronization for establishing a bit phase synchronization between the received data and a first clock having a clock rate of a times (a is a natural number) or 1 / a of the bit rate of the received data. A circuit, which is a times or 1 / times the bit rate of the received data from a reference clock having a frequency m times (m> 0) the clock frequency of the first clock.
a clock frequency of 1 and 1 of the received data
N-phase clock generation means for generating an n-phase clock in which a bit width is shifted to an n-phase (n is an integer of 2 or more) by a PLL circuit, and a missing tooth for each phase clock of the n-phase clock An n-phase missing clock generating means for generating a processed n-phase missing clock and a switching timing signal between the pulses of the missing clock, and the n-phase missing clock. Selecting means for selectively outputting a clock having any one of the phases of the clock signal by a selection control signal, and detecting a phase difference between the first clock and the received data, and based on the phase difference signal and the switching timing signal. Timing signal for generating the selection control signal and applying it to the selection means, latching the received data with the first clock, and outputting bit phase synchronization data. A bit phase synchronization circuit including output means, comprising the PLL circuit according to claim 1, wherein the clock selected and output by the selection means is fetched as a phase control signal and a phase switching signal is fetched. PLL of the clock generating means from the clock generating means for generating the first clock, the clock generated by the n-phase clock generating means, and the first clock.
And a lock determination means for determining whether the circuit is in a locked state and outputting a lock determination result signal, wherein the timing determination output means includes the switching timing signal, the lock determination result signal, and the phase difference signal. The bit phase synchronizing circuit is characterized in that the above-mentioned phase switching signal is generated from and is given to the PLL circuit of the clock generating means. 3. The predetermined protection time is the predetermined protection time after the selection is switched, with the predetermined protection time being the time from the selection switching output to the timing determination output means obtaining the phase difference signal. 3. The bit phase synchronizing circuit according to claim 2, wherein the inside is masked so as not to be given to the clock generating means as a significant clock. 4. A circuit for performing bit phase synchronization with respect to parallel reception data composed of a plurality of reception data having the same bit rate, wherein the parallel reception data is a times the bit rate of each reception data (a is a natural number) or 4. A bit phase synchronization circuit for establishing a bit phase synchronization with a first clock having a clock frequency of 1 / a to establish a synchronization state, the bit phase synchronization circuit according to claim 2 or 3, wherein: Bit phase synchronization is performed for any one of the received data, and the remaining remaining received data is latched and output using the first clock, and the bit phase synchronized data for each received data is output. A bit phase synchronization circuit characterized by being present. 5. A circuit for performing bit phase synchronization with respect to parallel reception data composed of a plurality of reception data of the same bit rate, wherein the parallel reception data and the bit rate of each reception data are a times (a is a natural number) or A bit phase synchronizing circuit for synchronizing a bit phase with a first clock having a clock frequency of 1 / a, the clock phase being m times (m> 0) the clock frequency of the first clock.
The phase is determined from the reference clock of the frequency of 1 by the PLL circuit, the toothless clock generation circuit, the selector circuit, the selector control circuit, the lock determination circuit, and the PLL circuit, the selection control signal, the phase control signal, and the phase switching signal according to claim Clock generation means for generating the first clock while performing control and frequency control, and detecting the phase difference between the first clock and each of the received data, and selecting based on each of the phase difference signals. And a timing determination output means for generating a control signal and giving it to the clock generation means, and for latching and outputting each of the received data with the first clock to output bit phase synchronization data. Synchronous circuit.