JPS5819055A - Clock reproducing circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of insensible section and to realize a stable clock reproduction, by stopping the detection without a timing component until the timing component arrives by predetermined numbers after arrival of a burst to the reception side. CONSTITUTION:A reception signal (p) is inputted to a burst detection circuit 21. The circuit 21 detects the section existing in the burst with the signal (p) and generates a pulse (q) indicating the head timing. The pulse (q) is used as the driving signal of an L notation counter 22 and sets the 4th FF23. If a pulse is generated to an output (r) of the counter 22, the FF23 is reset. At the section generated with a pulse to an output (s) of the FF23, an output (m) of an absence of timing detection circuit 13 is not given to the output of a circuit 24 with the 5th AND circuit 24. Then, at the leading process head reproducing the clock from a burst signal, no insensible section is generated and a smooth pull-in process can be realized.

Description

[Detailed description of the invention] For example, if the clock regeneration is required, the clock regeneration circuit can be used.

(3) scpc method (Single Channel pe
This invention relates to an improvement of a clock recovery circuit in a demodulator that demodulates an intermittent signal (hereinafter referred to as a burst signal) used in the R.R. Carrier system).

SCPC has been widely used in satellite communication systems in recent years.
In order to reduce transmission power, this method uses a so-called burst signal transmission method, in which radio waves are transmitted only in the section where the signal needs to be transmitted, and transmission is stopped in other sections. On the other hand, the receiving side receives all of the burst signals and reproduces the data on the transmitting side from this signal. Particularly when the transmitted signal is a distal signal, it is impossible to reproduce correct data unless the receiving side reproduces the block of the transmitted signal and a clock whose period is correct. Therefore, a clock regeneration circuit is prepared on the receiving side, but in general, it is impossible for this clock regeneration circuit to reduce the time (draw-in time) until the regeneration is completed (synchronization is completed) to zero. It takes a certain amount of time to pull in. During this pull-in process, the correct clock is not regenerated, and therefore it is impossible to regenerate the correct data (4). Therefore, on the transmitting side, a prefix is added and transmitted before the data that should be transmitted. However, a configuration is adopted in which the clock recovery is completed within this prefix on the receiving side, so that there is no hindrance to data recovery. However, such prefixes are a waste of time from the perspective of the information to be transmitted, so
I would like it to be shorter.

When receiving a burst signal and regenerating a clock, a digital phase synchronized circuit (Digital Phase Synchronous Circuit) is often used.
ital Phase Locked Loop +hereinafter referred to as DPLL. ) is used. This DPI,L is the oscillator, which will be explained in detail later. variable period counter,
The main components are two decoders and a phase comparison circuit. To this, a timing component absence detection circuit is added to prevent malfunctions when a timing component is missing in the clock component of a received signal. However, even with such a configuration, as will be explained in detail later, there is a non-sensing interval for the input timing component, making phase comparison impossible, which has a large effect on the synchronization pull-in time. Therefore, it has been impossible to rapidly and stably extract signals from burst-like received signals.

Therefore, an object of the present invention is to provide a clock regeneration circuit that can eliminate the dead period for input timing components in the lock regeneration circuit as described above, and can realize high-speed and stable pull-in characteristics from burst-like received signals. The purpose is to

The clock recovery circuit of the present invention stops detecting the absence of timing components until a predetermined number of timing components arrive after a burst arrives at the receiving side.
By preventing the occurrence of the non-sensing period, high-speed and stable lock playback can be realized.

By stopping detection of the absence of a timing component to prevent the occurrence of the non-sensing interval, high-speed and stable lock playback can be realized.

In other words, according to the present invention, the burst-like reception signal timing is set at a reference timing that almost coincides with this repetition timing;
A digital phase synchronization circuit that can achieve phase synchronization by controlling later timing or earlier timing, and this detection is performed by pseudo-detecting from this phase synchronization circuit that there is no timing component in the clock component of the received signal. and a timing component-free circuit having a detection means for generating a signal indicating the timing at which the timing component is detected. In the clock regeneration circuit in which the repetition timing of the synchronization circuit is prohibited from the slow timing and phase synchronization is achieved using the reference timing, the clock regeneration circuit further includes a burst signal detection for detecting and outputting the timing of the head of the received burst-like reception signal. a circuit, a means for driving by the output of the burst signal detection circuit and outputting a pulse while counting L (L is a natural number) clock components of the received signal; means for outputting a pulse for a period of time, and means for using the output signal of the means to negate the absence detection control. The present invention provides a clock regeneration circuit characterized in that phase synchronization is achieved by prohibiting the reference timing and canceling the prohibited slow timing.

Next, a detailed explanation will be given with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of a DPLL that is often used when receiving a burst signal and regenerating a clock. In FIG. 1, 1 is an oscillator, and 2 is an N-1 system controlled by external control.

A variable cycle counter that can select N-ary 2N+1-ary.

3 and 4 are the first. 2nd decoder, 5 is a phase comparator circuit, 6 and 7Fi are respectively 12th and 2nd flip-flops, 8 and 9 are each 1st. A second AND circuit is shown.

FIG. 2 is a time chart for explaining the operation of the circuit shown in FIG. The operation of the configuration shown in FIG. 1 will be explained below with reference to FIG. 2. The oscillation frequency of the oscillator 1 is selected to be approximately N times the frequency of the clock component a (FIG. 2) of the received signal. The reference signal which is the output of the oscillator 1 is guided to a variable period counter 2 and drives the counter. The outputs of the variable period counter 2 and cff are the first .
It is connected to second decoders 3 and 4. and the first
The decoder 3 is set to detect when the content of the variable period counter 2 becomes 0, and the second decoder 4 is set to detect when the content becomes a natural number (assumed to be M) closest to N/2. Therefore, the first. The second decoders 3 and 4 generate pulsed outputs d and e, respectively, when the contents of the variable period counter 2 become 0 and M, respectively (FIG. 2). The lowercase alphabento letters are used to indicate output lines and output signals, and will be used as appropriate below.

The output d of the first decoder 3 is the output d of the first decoder 3 in the phase comparison circuit 5.
It is connected to the reset terminal R of the second flip-flop 6.7 and resets both flip-flops. The output e of the second decoder 4 is connected to the set terminal S of the first flip-flop 6.

Set up this flip frozzo. Then, the clock component a of the received signal is sent to the second flip-flop 7, ! One terminal S is connected to set one flip-flop.

Therefore, as shown in FIG. 2, the outputs f and g of both flip-flops f6 and f7 are generated as output pulses corresponding to the phase difference between the outputs e and d and the phase difference between the outputs a and d, respectively.

The negative sign of the output f of the first flip-flop 60 and the output g of the second flip-flop f7 is 2 of the first AND circuit 8.
There will be two inputs, a match will be made, and an output will be generated. This output becomes the first output of the phase comparator 5, and as shown by the solid line in FIG.
is generated as a signal corresponding to the phase difference between the two timings only when the timing is later than the content of the variable period counter 2 becomes M. In this case, the cycle of the variable cycle counter 2 is selected to be N+1 base. Therefore, the next time the content becomes M is delayed by one period of the output frequency of the oscillator 1, so the phase difference between the output e of the second decoder 4 and the clock component a of the received signal is controlled to be smaller. Ru.

On the other hand, the negative sign of the output f of the first flip-flop 60, the output g of the second Norinob flop 7, and the two inputs of the second AND circuit 9 are matched.

Output 1 occurs. This signal 1 becomes the second output of the phase comparison circuit 5, and only when the clock component a of the received signal is faster than the content of the variable period counter 2 becomes M, as shown by the dotted line in FIG. It is generated as a signal corresponding to the phase difference between the two timings. In this case, the cycle of the variable cycle counter 2 is selected to be N-1. Therefore 1
Since the next timing when the content becomes M is accelerated by one period of the output frequency of the oscillator 1, the phase difference between the output e of the second decoder 4 and the clock component a of the received signal is controlled to be smaller. In other words, with the two-piece configuration, the phase difference between the output e of the second decoder 4 and the clock component a of the received signal is controlled in a direction that always decreases, and eventually the phase of both reaches a point where they almost match, and synchronization is not achieved. Complete. Note that the reference timing for the above-mentioned slow or fast timing may be referred to as the reference timing.

The above is the operating principle of the DPLL shown in FIG.
In the above description, the case where the clock component a of the received signal always has a timing component has been discussed.

However, it must be noted that in reality, the clock component a of the received signal does not always include a timing component.

FIG. 3 is a timing chart for explaining the operation of the circuit of FIG. 1 when the clock component of the received signal lacks a timing component. In this case 2, although the timing of the clock component a of the received signal is originally faster than the timing of the output e of the second decoder 4, a delayed pulse is generated and causes a malfunction. ing. Therefore, in the past, a system has been adopted in which a circuit is added to detect the absence of a timing component in the clock component a of the received signal.

FIG. 4 is a block diagram showing the configuration of a conventional clock recovery circuit to which such a detection circuit is added. In FIG. 4, 10 is the basic PLL shown in FIG. 1, but inside there is a third decoder 11 and a third AND
A circuit 12 is specifically provided. Reference numeral 13 denotes a timing signal absence detection circuit, which includes a fourth AND circuit 14 and a third flip-flop 15. In addition, (N
-1), (N).

(N+1.) represents (N-1)-ary selection, N-ary selection, and (N+1)-ary selection, respectively. It is a diagram showing a time chart. To explain below using FIG. 4 and FIG. 5, the third
The output j of is connected to the third decoder 11. For example, the third decoder 11 is configured such that the content of the variable period counter 2 is N-1.
At the point when , the output y/rus k is generated as shown in FIG.

This output becomes one input of the fourth AND circuit 14 in the timing component absence detection circuit 13. The other input of the fourth AND circuit 14 is connected to the first output of the phase comparison circuit 5 in the DPLL 1.0. In this signal, as mentioned above, the clock component a of the received signal is transmitted to the second decoder 4.
If the timing is later than the output e of
Even when there is no timing component, a pulse is generated, and in this case, the pulse continues until the contents of the variable period counter 12 become zero. Therefore, when there is no timing component in the clock component a of the received signal, the output e of the fourth AND circuit 14 contains the contents of the variable period counter 2 by N-1.
When the ie pulse occurs, the third flip-flop 15 is set.

The third Norinob flop 15 outputs the output d of the second decoder.
It will be reset by Book 3 Norinobu Flop 15
The timing does not need to be exact, as long as the content of the variable period counter 2 is after 0 and before M.

Therefore, the output m of the third flip-flop 15 is generated as a pulse in the interval shown in FIG. 5 when there is no clock component al'4 timing component of the received signal.

That is, the main signal m becomes the output signal of the timing component absence detection circuit 9.

In the configuration shown in FIG. 1, the first output of the one-phase comparison circuit 5 is directly connected to the variable period counter 2, but in the configuration shown in FIG. 4, it is connected to one input of the third AND circuit 12. . The other input signal of [Third AND circuit] 2 becomes the negative sign of the output m of the timing component absence detection circuit 13. The output n of the third AND circuit 12 becomes a control signal for the variable period counter 2. If 1 non-signal n generates an ie pulse at the time when the contents of the variable period counter 2 are N-1, the variable period counter 2 The N+1 base is selected and operates in the same manner as the configuration shown in FIG. On the other hand, the output m of the timing signal absence detection circuit 13 is also directly connected to the variable period counter 2, and if the signal mK/"rus exists, the variable period counter 2 is prohibited from being in N+1 base and is not in N base. selected, that is, if clock component a of the received signal has no timing component.

The variable period counter 2 is set to N-ary, which is a condition almost equal to the clock frequency of the received signal, and waits for the next timing component, thereby eliminating the drawback of the configuration shown in FIG.

However, although the circuit with the configuration shown in Figure 4 has been improved as described above, there is a non-sensing interval for the input timing component, which causes a large effect on the synchronization pull-in time as described next. O FIG. 6 shows an example of a time chart showing a case where the above-mentioned non-sensing interval occurs. That is, when the timing of the clock component a of the received signal arrives within the timing of the contents of the variable period counter 2 being N-1, the output mK pulse of the timing component absence detection circuit 13 is generated, and the timing component absence detection circuit 13 receives the input signal. Even if there is a timing component, there is a possibility that a pulse will be generated, and this is just a false detection of the absence of a timing component. At this time, N-ary is selected for the variable period counter 2, and the above-mentioned timing component is ignored. That is.

This is a non-sensing interval for input timing components.

Since this non-sensing section has a width of only about 1/N with respect to all phases and also has a large phase difference from the final pull-in point, it has almost no significant influence after the pull-in is completed. However, at the beginning of the pull-in process in which the clock is recovered from the burst signal, the phase distribution of the input timing information is considered to be uniform.

The probability that a timing component will occur in this section cannot be ignored. Moreover, once it occurs within two intervals, phase comparison at that point becomes impossible, and the variable period counter 2 becomes N.
Since the synchronization is fixed at a constant value, there is an extremely high possibility that this condition will continue for a long time, causing a significant impact on the synchronization pull-in time.

No. 7 is a block diagram showing the configuration of an embodiment of the present invention. In this FIG. 7, the components or outputs (signals) indicated by reference numerals up to 15 and alphabets up to n are exactly the same as in FIG. 4, and 21 is a burst detection circuit, 22 is an L A base counter (L is a plurality of natural numbers).

23 is a fourth slip-flop, and 24 is a fifth AND circuit.

FIG. 8 is a time chart for explaining the operation of the circuit shown in FIG. 7.

The operation of the circuit shown in FIG. 7 will be explained below with reference to FIG. 8. The received signal p is input to the burst detection circuit 2. The burst detection circuit 21 detects all sections in which a burst exists in the received signal p, and further generates a pulse indicating the start timing thereof as an output q. Main burst detection circuit 21
It is well known that this can be easily constructed by, for example, an envelope detection circuit, a differentiation circuit, and a threshold t value circuit, but other methods may also be used. Output q of this burst signal detection circuit 21
becomes a drive signal for the L-ary counter 22, and at the same time sets the fourth slip-flop 23.

The L-ary counter 22 becomes capable of counting by one at the same time as the output qK pulse of the burst signal detection circuit 21 is generated. The clock component a of the received signal is input as the signal to be counted by the advance counter 22.

When it counts L signals to be counted after it becomes possible to count, it generates an output pulse r and stops counting itself. That is, after the burst signal detection circuit 21 detects the head of the burst, the two-prong counter 22 counts the timing components a f L of the received signal, and then stops.

The output r of the L-ary counter 22 is connected to the reset terminal of the flip-flop f23, and when a pulse is generated at the output r of the L-ary counter 22, the flip-flop 23 is reset. That is, a pulse is generated at the output S of the fourth flip-flop 23 only during the interval in which L clock components a of the received signal are generated after the burst detection circuit 21 detects the head of the burst. This flip flop 23
The negative sign of the output S becomes one input of the AND circuit 24.

On the other hand, just like the configuration shown in FIG. 4 above, D
The first output of the phase comparison circuit 5 in the PLL 10.

Output d of second decoder 3, output 1 of third decoder 11 (timing component absence detection circuit controlled by)
The output m of No. 3 becomes the other input of the fifth AND circuit 24. Therefore, the period in which a pulse is generated at the output S of the f-Frog 23, ie, the period from when the burst detection circuit 21 detects the beginning of the burst until L timing components arrive, is as follows.

The output m of the timing component absence detection circuit 13 is not transmitted to the output of the fifth AND circuit 24 by the fifth AND circuit 24 . Thereafter, the output t of the fifth AND circuit 24 is replaced with the connection of the output m of the timing component absence detection circuit 13 in the configuration shown in FIG. 4, and is connected to DPLLlo as a new absence detection signal. The variable period counter is set to 2iN base, and its negative sign is the third
becomes the other input of the AND circuit 12, and the DPLL10'
e control.

As can be seen from the above explanation, the circuit configuration shown in FIG.
After the burst detection circuit 21 detects the beginning of the burst, while L timing components are generated, that is, for a predetermined period of time, there is no timing component.
Since the control of the PLL 10 is prohibited, the dead period does not occur at the beginning of the pull-in process for reproducing black and white from the burst signal as in the configuration shown in FIG.
A smooth pull-in process can be realized. In addition, as mentioned above, a prefix word suitable for clock reproduction is normally placed before the data at the beginning of a burst signal, but the two sections are most suitable for clock reproduction.・Mother turn 101010・
It is common that something with a timing component is arranged over the entire interval, such as ..., and there is no need to detect the absence of a timing component in one interval. Prohibiting the absence detection from the time until the arrival of the timing component does not impair the characteristics of the clock recovery circuit in any way.

Further, the length of the prefix word for clock recovery is usually determined in advance. In this case, there is no need to particularly count the timing component of the clock component of the received signal as shown in FIG.

A monostable circuit that is driven by the output q of the burst signal detection circuit 21 and generates a mother pulse for a predetermined time from that point is connected to the L-adic counter 22 and the fourth flip-flop 23 (including the wiring between the two). It may be placed instead.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the basic configuration of a digital phase locked loop (DPLL) used in the present invention, Figure 2 is a diagram showing a time chart for operating the circuit in Figure 1, and Figure 3 is FIG. 4 is a block diagram showing the configuration of a conventional clock recovery circuit; FIG. 5 is a diagram showing the timing chart of the circuit operation in FIG. Figure 4 is a diagram showing a time chart for explaining the operation of the conventional circuit, and Figure 6 is a time chart 1 showing a case where a non-sensing interval occurs in Figure 5.
FIG. 7 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 8 is a diagram showing a time chart of the operation of the circuit of FIG. 7 according to the present invention. Explanation of symbols: 1 is an oscillator that generates a reference signal, 2 is a variable period counter, 3 and 4 are decoders, 5 is a phase comparator, 10
is a digital phase comparison circuit (DPLL), 11
is a decoder, and 12 is an AND circuit. 13 is a timing detection circuit, 2] is a burst detection circuit,
22 is an L-adic counter, 23 is a Flinno flop, and 24 is an AND circuit. Figure 1 (23) Figure 2 Figure 3 Small/3 Figure 4 Figure 5 A r-11-------Left 111]1 1 1 1 1 (N-t)11 1cb, (N+t>(N)1 1 1 l
11
12 1 14 3 11 1 1 a 1
11 1 L----1---- 4 223 and S

Claims (1)

[Claims] 1. Upon receiving a burst-like received signal, the repetition timing is set to a reference timing that substantially matches this repetition timing, or a slow one, depending on the phase difference between the clock component of the received signal and the reference signal generated by itself. A digital phase synchronization circuit that can achieve phase synchronization by controlling the timing or fast timing. a timing component-free circuit having a detection means for generating a signal indicating the detected timing when the phase synchronization circuit pseudo-detects that there is no timing component in the clock component of the received signal; is obtained, this signal is used to detect the absence of the digital phase synchronized circuit, and the repetition timing of this phase synchronized circuit is inhibited from the slow timing, and the clock regeneration is performed such that phase synchronization is achieved using the reference timing. The circuit further includes a burst signal detection circuit that detects and outputs the timing of the head of the received burst-like reception signal, and a clock component of the reception signal driven by the output of this /S-st signal detection circuit to L( L is a natural number)), and means for negating the absence detection control using the output of the means (7 pulses), whereby the means outputs the i9 pulses. A clock regeneration circuit characterized in that phase synchronization is achieved by prohibiting the reference timing that had been used up to that time and canceling the prohibited slow timing. 2. Receives a burst-like received signal and controls the repetition timing to a reference timing that almost matches this repetition timing, a slow timing, or a fast timing according to the phase difference between the clock component of the received signal and the reference signal generated by itself. A digital phase-locked circuit that can achieve phase synchronization. a timing component-free circuit having a detection means for generating a signal indicating the detected timing when the phase synchronization circuit pseudo-detects that there is no timing component in the clock component of the received signal; is obtained, this signal is used to detect the absence of the Dinotal phase synchronized circuit, and the repetition timing of this phase synchronized circuit is inhibited from the slow timing, and the clock regeneration is performed so that the phase synchronization is achieved using the reference timing. The circuit further includes a first signal detection circuit that detects and outputs the timing of the beginning of the received burst signal, and a first signal detection circuit that detects and outputs the timing of the beginning of the received burst signal, and a second signal detection circuit that is driven by the output of this burst signal detection circuit and generates a signal for a predetermined period of time. and means for using the output pulse of the means to negate the absence detection control. 1. A clock regeneration circuit characterized in that phase synchronization is achieved by prohibiting slow timing and canceling prohibited slow timing.