JPH0738554A - Burst signal phase control circuit - Google Patents

Abstract

PURPOSE:To stabilize the establishment of synchronism by extracting phase information to be extracted from a received burst signal when a bit sequence is 50% Duty and continuous, and controlling the phase of a present station block corresponding to this phase information. CONSTITUTION:This circuit is composed of an oscillator 1 for generating an nf clock signal at the n-fold frequency of a received burst signal 101, Duty detection part 2 for detecting the part, where the Duty of a preamble bit is 50%, of the received burst signal, pulse interval check part 3 for confirming the Duty detection is performed at fixed intervals, continuous Duty detection part 4 for detecting the part where the Duty is 50% and made continuous, pattern detection part 5 to be reset by a clear pulse from the continuous Duty detection part 4 while counting a Duty detection pulse from the Duty detection part 2, and phase control part 6 for controlling the phase corresponding to a coincident pulse from the pattern detection part 5 and outputting a clock signal 101 which synchronism is established.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst signal phase control circuit, and more particularly to a burst signal phase control circuit which is a kind of optical data communication system and is used for bit synchronization of burst signals used in power distribution network systems of electric power companies. Regarding

[0002]

2. Description of the Related Art Conventionally, this type of burst signal is a digital signal and has a bit structure shown in FIG. This burst signal is arranged in the transmission path band by time division for a plurality of stations.
For example, in a distribution network system, an optical cable connects multiple substations in the area and a central substation that controls the area, and each substation bursts to its own band allocated on the transmission line band. It sends a signal and performs data communication with the substation.

The preamble bit at the head of the burst signal is used for a signal which does not cause any inconvenience even if a part of it is discarded as a rising portion of the signal, for example, it is used for a signal for bit synchronization or control. The next frame portion is used for frame synchronization and the like, and the next data portion is used for transmitting the data body.

Conventionally, the burst signal phase control circuit of this kind is bit-synchronized with the received burst signal and the local clock, and it is necessary to surely establish the synchronization early for each burst due to the nature of the burst signal. FIG. 4 is a block diagram showing a circuit configuration of a conventional example. In FIG. 4, the change point detection unit detects the change point (change point from 0 to 1 or 1 to 0) of the data pulse as phase information from the preamble bit arranged at the beginning of the received signal 401 which is a burst signal. , A change point detection pulse 404 is generated. The oscillator 42 generates a clock signal 403 having an oscillation frequency n times the received signal 401. Clock phase control unit 4
A counter circuit 3 receives the reception change point detection pulse 404 as a clear input, inputs the clock signal 403 and divides the frequency by n, and at the same time outputs the clock signal 402 substantially synchronized with the burst signal 401.

[0005]

In this conventional burst signal phase control circuit, the bit change point of the preamble bit is detected as phase information, and the phase of the own station clock is controlled by this phase information for synchronization. Therefore, if the bit string is disturbed due to noise on the transmission path of the burst signal, the bit change point will change and synchronization will be lost.

[0006]

The burst signal phase control circuit of the present invention comprises means for extracting a timing signal when the bit duty of the preamble bit portion of the received burst signal is 50% and continuous as phase information. It is provided with means for controlling the phase of the clock of its own station by the timing signal to establish bit synchronization between this own station clock and the received burst signal.

More specifically, n of the reception clock signal f
An oscillator for generating an nf clock signal having a frequency doubled, and a reception burst signal is read by the nf clock signal, and each time point when the duty of the preamble bit at the head of the reception burst signal is 50% is detected and a duty detection pulse is output. The duty detection section and the duty detection pulse are input and each pulse is input when the reception block signal is normal 1
A pulse interval check unit that outputs a check pulse delayed by the cycle time, and a continuous Du that sends a clear pulse when the duty is 50% but not continuous due to the duty detection pulse and the check pulse.
a ty detection section, a pattern detection section that outputs a coincidence pulse when the duty is 50% and is continuous by the duty detection pulse and the clear pulse, and the nf clock signal is frequency-divided by the coincidence pulse for phase control And a phase control section for generating and outputting a local station clock having an optimum phase for reading the received burst signal.

[0008]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the circuit configuration of this embodiment. FIG. 2 is a time chart showing the waveform of each signal in this embodiment. In FIG. 1, the oscillator 1 has a transmission rate f
A clock signal 102 having an oscillation frequency nf that is n times the received burst signal 101 is output. The duty detector 2 reads the received burst signal 101 with the clock signal 102 and outputs the duty detection pulse 103 at the time when the duty of the preamble bit is 50%. The pulse interval check unit 3 outputs a check pulse 14 for checking whether the duty detection pulses 103 are output at regular intervals.

The continuous duty detecting section 4 detects a portion where the duty is 50% and is continuous by the duty detection pulse 103 and the check pulse 104, and outputs a clear pulse 105 when the duty is not continuous. The pattern detection unit 5 is reset by the clear pulse from the continuous duty detection unit 4, counts the duty detection pulses 103 from the duty detection unit 2, and outputs the coincidence pulse 106 at the time point when the m number of the duty detection pulses 103 are counted. The phase controller 6 is a counter circuit, and the matching pulse 106 from the pattern detector 5
The counter is cleared by the clock signal 102
Count, divide this by n, and receive burst signal 1
Clock signal 107 with optimum phase for reading 01
Is output.

Next, the operation of this embodiment will be captured and described with reference to FIG. 2A and 2B show timings of pulses at respective parts, FIG. 2A is a time chart when a normal burst signal is received, and FIG. 2B is a time chart when an abnormal burst signal is received. Figure 2
In (a), the preamble bits of the received burst signal 101 are received in the normal state as shown. Du
The ty detection unit 2 outputs a Duty detection pulse 103 at each time point indicated by an arrow having a Duty of 50%. The pulse interval check unit 3 outputs a check pulse 104 obtained by delaying the Dyty detection pulse 103 by a time corresponding to one cycle of the received burst signal 101. Continuous Duty
When the detection pulse 103 and the check pulse 104 do not match in time, that is, the received burst signal 101 is Dut.
Clear pulse 10 when y50% and this is not continuous
5 is output.

A clear pulse 10 is sent from the pattern detecting section 5.
Duty detection pulse 10 from the point when cleared by 5
When 3 is counted and m (3 here) are counted, the coincidence pulse 106 is output as the final phase information. The phase control unit 6 starts counting the clock 102 having the frequency nf from the time when it is cleared by the coincidence pulse 106, and outputs the clock 107 divided by n.
This clock 107 is synchronized with the clock of the received burst signal 101, and is used as a local clock for reading the data signal following the preamble bit.

Next, FIG. 2B shows a case where the preamble bit of the received burst signal 101 is received in an abnormal state due to the influence of noise or the like on the transmission path.
As for the clear pulse 105, the received burst signal 101 is Dut
It is output at each time when y is 50% and the continuous condition is not satisfied. The coincidence pulse 106 is not output because the clear pulse 105 is input 3 counts before, and therefore the clock 107 is not output. In this state, the device is not activated, but if the received burst signal 101 is restored to the normal state of FIG. 10A, the synchronization establishment state is entered by the above-mentioned operation.

Since the phase information Duty of 50% of the received burst signal 101 is detected by the clock signal 102 of the frequency nf, the accuracy of the phase information becomes high and the phase control error can be made small by making this n larger. it can. Normally, this value is selected to be about 8 as a practical value. Further, if the value of m is set to a large value as the output condition of the coincidence pulse 106, the stability of synchronization establishment increases, but on the other hand, since it takes time to establish synchronization, it is usually selected to be about 3 to 6.

[0015]

As described above, according to the present invention, this bit is Duty from the preamble bit of the received burst signal.
Matching pulse 1 as phase information when 50% and continuous
06 is detected, and the phase of the own station clock is controlled by this coincidence pulse 106 to establish synchronization. Therefore, when the phase of the received burst signal is disturbed on the transmission line due to noise, etc., the phase information is not detected and it is detected after it is restored normally, so it is possible to prevent erroneous detection of the phase and establish synchronization of the own station clock. It has the effect of stabilizing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing the timing of each signal in the related art shown in FIG.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a time chart showing the timing of each signal in FIG.

[Explanation of symbols]

 1 Oscillator 2 Duty Detecting Section 3 Pulse Interval Checking Section 4 Continuous Duty Detecting Section 5 Pattern Detecting Section 6 Phase Control Section 101 Received Burst Signal 102 nf Clock Signal 103 Duty Detection Pulse 104 Check Pulse 105 Clear Pulse 106 Matching Pulse 107 Clock Signal

Claims (2)

[Claims] 1. A means for extracting, as phase information, a timing signal when the bit duty of the preamble bit portion of the received burst signal is 50% and continuous, and controlling the phase of the own station clock by this timing signal. A burst signal phase control circuit comprising means for bit-synchronizing a clock and the received burst signal. 2. A frequency n which is n times the frequency of the received clock signal f.
An oscillator for generating an f clock signal and a received burst signal are read by the nf clock signal, and the duty of the preamble bit at the head of the received burst signal is 5
D that detects each 0% time point and outputs a duty detection pulse
a duty detecting section, a pulse interval checking section for inputting the duty detecting pulse and outputting a check pulse obtained by delaying each pulse by the time of one cycle of the reception block signal in the normal state, the duty detecting pulse and the check pulse And a continuous duty detector for transmitting a clear pulse when the duty is 50% but not continuous,
D by the duty detection pulse and the clear pulse
A pattern detection unit that outputs a coincidence pulse when the duty is 50% and continues, and a local station clock of an optimum phase that divides the nf clock signal by the coincidence pulse and controls the phase to read the received burst signal A burst signal phase control circuit comprising: a phase control unit for generating and outputting.