JPH0425240A - Burst signal monitoring circuit - Google Patents

Abstract

PURPOSE:To realize a monitoring circuit with simple circuit constitution by detecting a silence period so as to detect the changing point of a burst signal due to a leading bit and predicting the leading bit position of a succeeding burst signal from the changing point. CONSTITUTION:A silence period detection section 1 counts the clocks of an input signal during silence period and outputs a carry '1' when the counted value reaches a prescribed number (n) till a '1' signal is loaded to a load terminal to predict the arrival of a reception burst signal. Upon the receipt of the carry signal '1' of the counter representing consecutive non burst signal for a prescribed number, an AND gate 11 is set to set a flip-flop 23 at the '1' signal of the data inputting at first via the gate, that is, at the leading bit of the reception burst signal and a Q output is brought into '1'. Thus, a data changing point due to the arrival of the burst data is detected. Then the normality of the reception burst data is always monitored by a simple circuit.

Description

[Detailed Description of the Invention] [Summary] Regarding a monitoring circuit that monitors the normality of a received burst signal, if the first bit of each received burst-like data is a normal "l"
The purpose of this circuit is to realize a received burst signal monitoring circuit with a simple circuit configuration that constantly monitors whether a burst signal with multiple bits and the first bit is "1" is received normally. The circuit monitors whether or not the burst signal is present, and includes a no-signal period detection section that detects a no-signal section between burst signals, and a change point detection section that detects the beginning of the received burst signal that appears next to the detected no-signal section. and a start position prediction unit that starts operation based on the detection result of the change point detection unit and predicts the start position of the subsequent burst signal, examines the received data at the predicted start position, and inserts “
a head detection section that outputs a normal signal and stops the operation of the change point detection section if there is "1" at the position, and turns off the normal signal and restarts the operation of the change point detection section if there is "0" at the position; This is a configuration having the following.

[Industrial application field]

The present invention relates to a monitoring circuit that monitors the normality of a received burst signal.

In two-wire digital subscriber line transmission, etc., a time-division ping-pong transmission method is used, in which transmission data is time-compressed and burst data is sent and received alternately while sharing the same line. In order to correctly reproduce time-compressed received data, the transmitting side sets the first bit of each burst data to “l”.
However, this first bit may not always reach the receiving side normally due to noise or the like. Since it is essential for this first bit to be "l" in order to reproduce the received burst data, it is necessary to check the existence of this first bit and constantly monitor that a correct burst signal that can be reproduced is being received. There is.

[Conventional technology]

In a communication system that transmits and receives burst data, it is necessary to detect the beginning position of the received burst data and process the data. For this purpose, a frame synchronization pulse of a specific pattern characterized by the leading bit is inserted in advance at the beginning of the burst in the transmitter, and the receiver detects the frame synchronization pulse to generate timing for reproducing the burst signal.

This circuit for burst timing extraction is similar to the frame detection circuit in PCM digital communication using continuous code strings, and uses frame synchronization using frame bits, etc.
Provides rear protection, etc.

FIG. 4 is a block diagram of this frame detection circuit.

In the figure, data and clock are applied to frame pulse detection circuit 61 and clock control circuit 62, respectively.

The frame detection circuit 61 includes a timing pulse generation circuit 6
Using the timing pulse from 3b, a continuous multi-bit pulse train is extracted from the added data, and if it matches a predetermined frame pulse train, frame synchronization has been achieved in the synchronization protection circuit 64 (if the beginning of the burst is The synchronization protection circuit 64 stores that frame synchronization has been achieved once. The synchronization protection circuit 64 determines that synchronization has been established when frame synchronization is achieved n times in a row, and prevents the circuit from operating even if a control signal is applied from the frame pulse detection circuit 61 after this synchronization is established.
A lock signal for locking the operation of the clock control circuit 62 is sent to this circuit 62 to provide backward protection.

After synchronization is established, if the pulse train detected 01 times in succession does not match the predetermined frame pulse, the synchronization protection circuit 64
determines that the frame is out of synchronization and sends out a lock release signal to release the lock signal, and the clock control circuit 62 is controlled by the control signal from the frame pulse detection circuit 61 to perform forward protection.

On the other hand, if it does not match the predetermined frame pulse train, the detection circuit 61 sends a control signal to the clock control circuit 62, which shifts the clock by, for example, 1 bit and adds it to the counter 63a in the timing generator 63.

The counter 63a measures the input clock and applies it to the timing pulse generation circuit 62b.

The timing pulse generation circuit 62b decodes the input count value and outputs a timing pulse necessary for frame pulse detection.

The frame pulse detection circuit 61 extracts a pulse train from the data using this timing pulse and checks whether a predetermined pulse train is present or not, and shifts the clock by, for example, one bit at a time, using a control signal until a predetermined pulse train is detected. .

[Problem to be solved by the invention]

Incidentally, there are cases where it is desired to monitor whether the received burst signal is a normal signal, regardless of the burst timing detection operation.

Conventionally, for this purpose, the frame detection circuit described above was used to detect the burst timing of the received data, and if this timing could not be detected, it was determined that the received data was not normal.

That is, in order to monitor whether or not normal data with "1" in the first bit is being received, the burst timing is detected by a frame detection circuit, and this result can be used to confirm the normality of the received data. there was. However, as mentioned above (the frame detection circuit is originally for detecting burst timing pulses, the registers and comparison circuits for holding multiple bits of data and checking in parallel for matching with a predetermined pattern are complicated). Also, since protection such as front and rear protection is required, the circuit is complicated and requires a large amount of hardware, making it expensive for the purpose of only monitoring the normality of received data. there were.

The present invention was created in view of the above problems, and provides a received burst signal monitoring circuit with a simple circuit configuration that constantly monitors whether the first bit of each received burst data is a regular "1". The purpose is to

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of a burst signal monitoring circuit according to the present invention.

As shown in Figure 1, the above problem is a circuit that monitors whether or not a burst signal having multiple bits and the first bit is "l" is being received normally. A no-signal period detection section 1 detects a no-signal section, a changing point detecting section 2 detects the beginning of a received burst signal that appears next to the detected no-signal section, and operates based on the detection results of the changing point detecting section 2. a head position prediction unit 3 that starts the burst signal and predicts the head position of the subsequent burst signal, and checks the received data at the predicted head position, and outputs a normal signal if there is "1" at the position, and detects the change point. The head detection section 4 stops the operation of the change point detection section 2, turns off the normal signal if there is "0" at the position, and restarts the operation of the change point detection section 2. The problem is solved by a burst signal monitoring circuit.

[Effect]

First, a no-signal period is detected, a change point due to the first bit of the burst signal is detected, and the position of the first bit of the next burst signal is predicted from this change point.

If the data input of the next burst signal is at the 'I' level at this predicted position, it is recognized that the next burst signal has been received normally and a normal signal is output.After that, the process continues without detecting the change point. Then, predict the leading edge position of the next burst signal and check the received data at the predicted position.

If the data at the predicted position is at the "0" level, it is determined that it is an abnormal burst signal, the normal signal is turned off, and the search for a change point is started from that point.

Since each part can be configured with a counter, a flip-flop, and a gate circuit, the monitoring circuit can be realized with a simple circuit configuration without using high-grade circuits such as a frame detection circuit with a protection function.

〔Example〕

The present invention will be described in detail below with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a timing chart showing the operation of the embodiment.

In FIG. 1, a received burst signal that has an n-bit pause period and is repeated at an m-bit length cycle is received by a signal receiving section (not shown), and receives received data IN converted to a TTL level and the received signal. Clock CLK extracted from
is input to the monitoring circuit.

1 is a no-signal period detection unit that detects a no-signal period between each burst signal, and includes a synchronous counter II that outputs a carry according to the number of bits n of the I burst signal, and an enable terminal that inverts the carry output of the counter. εN, and an inverter 12 to detect a no-signal period between each burst signal.

2 is a change point detection section, which is composed of an AND gate 11, an OR gate 12, and a D-type flip-flop 13;
The output changes at the start position of the received burst signal that appears next to the detected no-signal period, and the start position of the burst signal is detected.

Reference numeral 3 denotes a head prediction unit, which consists of a differentiation circuit 31 and a synchronous counter 32 modulo the number of bits m of the burst repetition period, and receives the next burst signal based on the head position of the burst signal detected in the previous stage. Predict the start position of the burst signal.

Reference numeral 4 denotes a head detection unit, which is composed of an AND gate 41 and a D-type flip-flop 42, and checks whether the head bit "1" of the next burst signal exists at the predicted head position and detects the normal signal OUT. Output.

Next, the operation of the monitoring circuit having the above configuration will be explained using the operation time chart of FIG.

Received data IN is input to the load terminal of counter 1, and it is initialized at the "1" level in the received data.
While the data is "0", the clock CLK is counted, and when n clocks are counted, a carry I" is output. This carry signal is sent to the subsequent stage and is also input to the EN terminal via the inverter 12. , the counter 11 stops counting.

That is, the no-signal period detection unit 1 counts clocks during the no-signal period of the input signal, and when the count value reaches a predetermined number n before being loaded with the ``l'' signal to the load terminal, a carry ``l'' is detected.
" is output to foretell the arrival of the received burst signal. This signal becomes "1" level immediately before the arrival of the received burst signal.

The normal reception signal OUT is input to the reset terminal R3 of the flip-flop 13 via the inverter 14, and in the initial state where OUT is "θ", this flip-flop 13 is in an operating state. Therefore, when the carry signal "l" from the counter at the previous stage indicating that no burst signal has continued for a predetermined number of times is input, the AND gate 11 is opened, and the "l" signal of the data that first enters through the gate is input. That is, the flip-flop 13 is set with the first bit of the received burst signal, and the Q output is set to "1". Since this output is federated to the data terminal via the OR gate 12, the flip-flop 23 remains active until "1" is input to the reset terminal R3, that is, until the normal signal OUT becomes "1". The Q output remains unchanged and held at "L". This means that the flip-flop 23 has detected a data change point due to the arrival of burst data.

This change point detection result is differentiated by a differentiating circuit 31 to become a pulse with a length of l clocks, which is input to a load terminal of an m-ary counter. The m-adic counter starts counting clocks by this load pulse, counts m clocks, and
Outputs the burst clock and carry for each burst period. Since the point in time when this carry is output corresponds to the beginning position of the next burst signal, if the received burst signal is normal, there should be "1" at the beginning of the burst signal in the data input as well.

The carry output corresponding to this leading position is input to the AND gate 41, which opens the gate for l clocks. If data "l" is present at this predicted position, it passes through the gate and "1" is input to the data input of the flip-flop 42. The burst clock BCK is a clock signal that uses, for example, the best Q combination output of the counter 32 and rises before the fall of the carry output every time a carry is output. It is intended to incorporate. As a result, the Q output of the flip-flop becomes "L" and outputs a normal signal OUT indicating that the received burst is normal.

"1" of this normal signal OUT is inverted by the inverter 44 and inputted to the reset terminal of the flip-flop 23 of the change point detection section, and the output of the flip-flop is "0" regardless of the input data, and the change is checked. Stop the output operation.

After that, the m-ary counter runs free and outputs a carry every m-bit burst period to predict the start position.
The head detection unit 4 checks the presence of "1" in the data input at this carry position, and outputs "l" to the normal signal OUT while there is a "bi" at the beginning of the burst signal, indicating that the received burst signal is normal. Show that something is true.

When an abnormal burst signal in which "1" does not exist at the beginning position of the burst signal is received, the output of the AND gate 41 is "0" because there is no data input at the carry output (predicted position).
”, the FF 42 is reset by the burst clock, and the normal signal OUT becomes “0”, indicating that the received burst is abnormal.

Further, as the normal signal OUT changes to "0", "l" is input to the reset terminal of the FF 23 of the change point detection section 2 via the inverter 14, so the FF 23 becomes operational and starts the burst signal again. Repeat the first operation to start detecting the change point.

As explained above, it is possible to constantly monitor the normality of received burst data with a simple circuit, and the structure can be constructed at a lower cost than the conventional method of detecting timing and monitoring the normality from the detection result.

〔Effect of the invention〕

As described above, according to the present invention, a received burst signal monitoring circuit that constantly monitors whether the first bit of each received burst data is a regular "L" can be realized with a simple circuit configuration. be.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the burst signal monitoring circuit of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a time chart showing the operation of the embodiment, and Fig. 4 is a conventional diagram. FIG. 1 is a block diagram of a frame detection circuit used in the monitoring method of FIG. In the figure, 1--non-signal period detection unit, 11-counter, 2--change point detection unit, 23-flip-flop, 3--heading position prediction unit, 31-differentiating circuit, 32-counter,
4-Head detection unit, flip-flop. Juto f) *N7) KT'MI l r tips L-JU times,
1/l 7”fl,,,'71] Fig. 4

Claims (1)

[Claims] A circuit that monitors whether a burst signal having multiple bits and whose first bit is "1" is being received normally, and detects a no-signal period between the burst signals. A no-signal period detection section (1), a change point detection section (2) that detects the beginning of the received burst signal that appears next to the detected no-signal section, and a change point detection section (2) that operates based on the detection results of the change point detection section (2). and a head position prediction unit (3) that predicts the head position of the subsequent burst signal; and a head position prediction unit (3) that examines the received data at the predicted head position and outputs a normal signal if there is "1" at the predicted position, and The operation of the point detection section (2) is stopped, and if there is "0" at the position, the normal signal is turned off and the change point detection section (2) is stopped.
1. A burst signal monitoring circuit comprising: a head detecting section (4) for restarting the operation of the burst signal monitoring circuit.