JP2849952B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit and, more particularly, to a frame synchronization circuit for eliminating erroneous pull-in by an input signal similar to a normal frame synchronization pattern signal in a multistage relay system.

[0002]

2. Description of the Related Art Conventionally, this kind of frame synchronization circuit has been disclosed in FIG.
As shown in (1), it is composed of a frame synchronization circuit main body 101 for outputting a frame synchronization signal error pulse signal 12, and a determination circuit 102 for counting the number of pulses. The frame synchronization circuit uses a one-bit immediate hunting method or the like in which the counter in the circuit is stopped according to the determination result of the determination circuit 102. FIG. 4 is a configuration diagram of the determination circuit 102. First, in FIG. 3, an input signal 11 is input to the frame synchronization circuit main body 101 and is also transmitted to a subsequent repeater. The frame synchronization circuit main body 101 outputs a frame synchronization signal error pulse 12 to the determination circuit 102 if an error is found, based on a comparison result between the frame synchronization signal pulse formed in the input signal 1 and a synchronization signal generated in itself. I do.

Next, the operation of the decision circuit 102 will be described with reference to FIG. The frame synchronization signal error pulse 12 is input to the error pulse counting circuit 104. Error pulse counting circuit 10
Reference numeral 4 counts the number of error pulses with the reset signal 17 generated by the interval generation circuit 105 using the frame synchronization signal error pulse 12 as a starting point of counting, and sends out a hunting control signal 14 when a predetermined threshold value is reached. The reset signal 6 is an integral multiple of the frame synchronization period. The hunting control signal 14 causes the frame synchronization circuit body 1
01 was stopped.

[0004]

In the above-described conventional frame synchronization circuit, it is assumed that a signal similar to a frame synchronization signal pattern formed in a digital signal format is input because the input signal is very random. For example, when the frame synchronization signal has an m-bit configuration, only the first pulse pattern signal is different from the frame synchronization signal pattern, and the subsequent m-1 pulse pattern signals are all the same as the normal frame synchronization signal pattern. It is assumed that such an input signal is input. If the threshold value of the decision circuit is set so as to transmit a hunting control signal when there is an error of 2 bits or more in one frame, the error pulse counting circuit sets the number of error pulses to one in one frame. Only counting is performed, and no hunting control signal is output. Therefore, there is a drawback that the synchronization pull-in is performed at a position different from the original synchronization pull-in position.

[0005]

SUMMARY OF THE INVENTION A frame synchronization circuit according to the present invention comprises a frame synchronization pattern signal formed in an input signal from a preceding relay station of a multistage relay system and a reference frame synchronization signal provided in a local repeater. Error pulse detection means for outputting an error pulse when an error is detected as compared with the pattern signal, and hunting control for inputting and counting the error pulse, and temporarily stopping synchronization when a predetermined threshold is reached. A determination circuit for outputting a signal, the error pulse detection means also outputting an error pulse position signal indicating position information of an error pulse of a pulse pattern constituting the frame synchronization pattern signal; A position signal and the error pulse are input and error pulses are counted for each pulse position of the frame synchronization pattern signal. Ri has a pulse position determining means.

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a frame synchronization circuit according to one embodiment of the present invention. FIG. 2 is a configuration diagram of a determination circuit which is a main part of the present embodiment. The embodiment of FIG. 1 is different from the conventional example of FIG. 3 in that a frame synchronization position signal 13 is output from a frame synchronization circuit body 1 in addition to a frame synchronization error pulse 12, and both signals (12, 13) are output. The determination circuit 2 is configured to prevent erroneous determination of synchronization pull-in by inputting. Note that the determination circuit 2 is configured to send a hunting control signal 14 for stopping the synchronization pull-in operation when the frame synchronization circuit 1 is asynchronous.

Next, the configuration and operation of the decision circuit 2 will be described with reference to FIG. The error pulse position determination circuit 3 includes a frame synchronization signal error pulse 12 and a frame synchronization position signal 13.
Is converted into an error signal corresponding to the position of the frame synchronization pulse, that is, if the synchronization pulse is m bits, the error signal is converted into an error signal for each of the first bit, the second bit to the m-th bit, and the error pulse is counted. The error signals 15A to 15C are output separately to the circuits 4A and 4B to 4C. The error pulse counting circuits 4A, 4B, and 4C determine the number of frame synchronization pulses in one frame when the number is m bits.
The number corresponding to the number is prepared. On the other hand, the error pulse counting circuits 4A to 4C receive the reset signal 17, which is the output signal of the interval generation circuit 5, and
, The number of error pulses is counted. When the counted value exceeds the set threshold value, each hunting control signal 16A, 16B to 16C is output. The OR circuit 6 calculates the logical sum of the hunting control signals 16A to 16C and outputs the result to the frame synchronization circuit main body 1 as a hunting control signal 18.

Now, as described in the section of the prior art, the input signal 11 is random and has an erroneous pattern signal similar to the frame synchronization signal pattern, for example, only the first pulse is different from the frame synchronization signal pattern. Assuming that the subsequent m-1 pulses are exactly the same as the frame synchronization pattern, the first error signal 15A is input to the error pulse counting circuit 4A. Since the error signal 15A is always output once per frame, the threshold value of the error pulse counting circuit 4A is set to, for example, 5
If the number is set to two or more in the frame, the hunting control signal 16A can be output, and as a result, the finally aggregated hunting control signal 14 can be output to the frame synchronization circuit main body 1. Further, in the present invention, the error pulse counting circuits 4A to 4C
Are prepared for the number of pulses of the maximum synchronization pattern.
As described above, regardless of the position where only one of the m pulses differs, the count value of the error pulse counting circuit (for example, 4C) at the corresponding position is equal to the threshold value (5C).
Hunting control signal 1
4 is output, and the synchronization pull-in operation can be immediately stopped. As the input signal 11 increases in randomness, the plurality of error pulse counting circuits 4A to 4C accumulate the error counts, and output the hunting control signals 16A to 16C from the circuit which has reached the threshold value to stop the synchronization pull-in. Therefore, stable frame synchronization can be established.

[0010]

As described above, according to the present invention, the judgment signal is provided with a plurality of error pulse counting circuits corresponding to the number of pulses of the frame synchronization pulse pattern. Even if a signal similar to the above is input, erroneous pull-in is stopped, so that there is an effect that stable frame synchronization can be established.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a frame synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a determination circuit of a main part of the embodiment.

FIG. 3 is a configuration diagram of a conventional frame synchronization circuit.

FIG. 4 is a configuration diagram of a conventional determination circuit.

[Explanation of symbols]

 Reference Signs List 1 frame synchronization circuit main body 2 judgment circuit 3 error pulse position judgment circuit 4A to 4C error pulse counting circuit 5 interval generation circuit 6 OR circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 7/08 H04J 3/06 H04L 7/00

Claims (2)

(57) [Claims] An error is detected when a frame synchronization pattern signal formed in an input signal from a preceding-stage relay station of a multistage relay system and a reference frame synchronization pattern signal provided in a local repeater are erroneous. A frame synchronization circuit comprising: an error pulse detection means for outputting a pulse; and a determination circuit for inputting and counting the error pulse, and outputting a hunting control signal for temporarily stopping synchronization when a predetermined threshold value is reached. The error pulse detecting means also outputs an error pulse position signal indicating the position information of the error pulse of the pulse pattern constituting the frame synchronization pattern signal, and inputs the error pulse position signal and the error pulse, and An error pulse position determination means for counting error pulses for each pulse position of the pattern signal is provided. Frame synchronization circuit. 2. The error pulse position determination circuit, wherein the error pulse position determination means receives the error pulse and the error pulse position signal and distributes the error pulse corresponding to each error pulse position. 2. The apparatus according to claim 1, further comprising: a plurality of error pulse counting circuits corresponding to the number of pulses of the synchronization pattern signal; and a logical sum circuit that inputs respective output signals of the error pulse counting circuit and performs a logical sum. A frame synchronization circuit as described.